forked from OSchip/llvm-project
[AArch64][GlobalISel] Add support for narrowScalar of G_ZEXT
We do this by merging the source with the high bits set to 0. Differential Revision: https://reviews.llvm.org/D66181 llvm-svn: 369480
This commit is contained in:
Amara Emerson
parent
d979a29935
commit
56606a4db3
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@ -615,6 +615,24 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_ZEXT: {
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if (TypeIdx != 0)
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return UnableToLegalize;
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if (SizeOp0 % NarrowTy.getSizeInBits() != 0)
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return UnableToLegalize;
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// Generate a merge where the bottom bits are taken from the source, and
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// zero everything else.
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Register ZeroReg = MIRBuilder.buildConstant(NarrowTy, 0).getReg(0);
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unsigned NumParts = SizeOp0 / NarrowTy.getSizeInBits();
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SmallVector<Register, 4> Srcs = {MI.getOperand(1).getReg()};
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for (unsigned Part = 1; Part < NumParts; ++Part)
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Srcs.push_back(ZeroReg);
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MIRBuilder.buildMerge(MI.getOperand(0).getReg(), Srcs);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_ADD: {
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// FIXME: add support for when SizeOp0 isn't an exact multiple of
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@ -341,7 +341,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
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unsigned DstSize = Query.Types[0].getSizeInBits();
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if (DstSize == 128 && !Query.Types[0].isVector())
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return false; // Extending to a scalar s128 is not legal.
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return false; // Extending to a scalar s128 needs narrowing.
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// Make sure that we have something that will fit in a register, and
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// make sure it's a power of 2.
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@ -363,8 +363,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
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return true;
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};
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getActionDefinitionsBuilder({G_ZEXT, G_ANYEXT}).legalIf(ExtLegalFunc);
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getActionDefinitionsBuilder(G_SEXT)
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getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
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.legalIf(ExtLegalFunc)
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.clampScalar(0, s64, s64); // Just for s128, others are handled above.
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@ -46,7 +46,9 @@ const RegisterBank &X86RegisterBankInfo::getRegBankFromRegClass(
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if (X86::GR8RegClass.hasSubClassEq(&RC) ||
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X86::GR16RegClass.hasSubClassEq(&RC) ||
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X86::GR32RegClass.hasSubClassEq(&RC) ||
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X86::GR64RegClass.hasSubClassEq(&RC))
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X86::GR64RegClass.hasSubClassEq(&RC) ||
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X86::LOW32_ADDR_ACCESSRegClass.hasSubClassEq(&RC) ||
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X86::LOW32_ADDR_ACCESS_RBPRegClass.hasSubClassEq(&RC))
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return getRegBank(X86::GPRRegBankID);
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if (X86::FR32XRegClass.hasSubClassEq(&RC) ||
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@ -1,25 +0,0 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=aarch64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: narrow_s128
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0, $x1
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; CHECK-LABEL: name: narrow_s128
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; CHECK: liveins: $x0, $x1
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
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; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s64)
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; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[ASHR]](s64)
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; CHECK: G_STORE [[MV]](s128), [[COPY1]](p0) :: (store 16)
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; CHECK: RET_ReallyLR
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%0:_(s64) = COPY $x0
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%1:_(p0) = COPY $x1
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%2:_(s128) = G_SEXT %0(s64)
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G_STORE %2(s128), %1(p0) :: (store 16)
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RET_ReallyLR
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...
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@ -0,0 +1,71 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=aarch64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: narrow_sext_s128
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0, $x1
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; CHECK-LABEL: name: narrow_sext_s128
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; CHECK: liveins: $x0, $x1
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
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; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s64)
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; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[ASHR]](s64)
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; CHECK: G_STORE [[MV]](s128), [[COPY1]](p0) :: (store 16)
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; CHECK: RET_ReallyLR
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%0:_(s64) = COPY $x0
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%1:_(p0) = COPY $x1
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%2:_(s128) = G_SEXT %0(s64)
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G_STORE %2(s128), %1(p0) :: (store 16)
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RET_ReallyLR
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...
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---
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name: narrow_zext_s128
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0, $x1
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; CHECK-LABEL: name: narrow_zext_s128
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; CHECK: liveins: $x0, $x1
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[C]](s64)
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; CHECK: G_STORE [[MV]](s128), [[COPY1]](p0) :: (store 16)
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; CHECK: RET_ReallyLR
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%0:_(s64) = COPY $x0
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%1:_(p0) = COPY $x1
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%2:_(s128) = G_ZEXT %0(s64)
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G_STORE %2(s128), %1(p0) :: (store 16)
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RET_ReallyLR
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...
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---
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name: narrow_zext_s192
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0, $x1
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; CHECK-LABEL: name: narrow_zext_s192
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; CHECK: liveins: $x0, $x1
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; CHECK: [[MV:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[COPY]](s64), [[C]](s64), [[C]](s64)
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; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[MV]](s192)
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; CHECK: G_STORE [[UV]](s64), [[COPY1]](p0) :: (store 8)
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; CHECK: RET_ReallyLR
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%0:_(s64) = COPY $x0
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%1:_(p0) = COPY $x1
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%2:_(s192) = G_ZEXT %0(s64)
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%3:_(s64), %4:_(s64), %5:_(s64) = G_UNMERGE_VALUES %2(s192)
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G_STORE %3, %1(p0) :: (store 8)
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RET_ReallyLR
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...
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@ -227,6 +227,7 @@
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# DEBUG-NEXT: .. the first uncovered type index: 2, OK
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# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
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# DEBUG-NEXT: G_SEXT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
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# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
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# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: G_SEXT_INREG (opcode {{[0-9]+}}): 1 type index, 1 imm index
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