forked from OSchip/llvm-project
[RISCV] Add test cases showing that we don't recognize the select form of NABS in SelectionDAGBuilder so we end up with branches. NFC
There's a FIXME that it should produce (sub 0, (abs)).
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5654a3dd0a
llvm/test/CodeGen/RISCV
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@ -24,6 +24,29 @@ define i32 @neg_abs32(i32 %x) {
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ret i32 %neg
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}
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define i32 @select_neg_abs32(i32 %x) {
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; RV32-LABEL: select_neg_abs32:
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; RV32: # %bb.0:
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; RV32-NEXT: bltz a0, .LBB1_2
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; RV32-NEXT: # %bb.1:
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; RV32-NEXT: neg a0, a0
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; RV32-NEXT: .LBB1_2:
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; RV32-NEXT: ret
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;
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; RV64-LABEL: select_neg_abs32:
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; RV64: # %bb.0:
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; RV64-NEXT: sext.w a1, a0
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; RV64-NEXT: bltz a1, .LBB1_2
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; RV64-NEXT: # %bb.1:
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; RV64-NEXT: negw a0, a0
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; RV64-NEXT: .LBB1_2:
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; RV64-NEXT: ret
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%1 = icmp slt i32 %x, 0
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%2 = sub nsw i32 0, %x
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%3 = select i1 %1, i32 %x, i32 %2
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ret i32 %3
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}
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define i64 @neg_abs64(i64 %x) {
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; RV32-LABEL: neg_abs64:
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; RV32: # %bb.0:
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@ -46,3 +69,29 @@ define i64 @neg_abs64(i64 %x) {
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%neg = sub nsw i64 0, %abs
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ret i64 %neg
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}
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define i64 @select_neg_abs64(i64 %x) {
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; RV32-LABEL: select_neg_abs64:
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; RV32: # %bb.0:
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; RV32-NEXT: bltz a1, .LBB3_2
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; RV32-NEXT: # %bb.1:
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; RV32-NEXT: snez a2, a0
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; RV32-NEXT: add a1, a1, a2
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; RV32-NEXT: neg a1, a1
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; RV32-NEXT: neg a0, a0
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; RV32-NEXT: .LBB3_2:
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; RV32-NEXT: ret
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;
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; RV64-LABEL: select_neg_abs64:
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; RV64: # %bb.0:
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; RV64-NEXT: bltz a0, .LBB3_2
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; RV64-NEXT: # %bb.1:
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; RV64-NEXT: neg a0, a0
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; RV64-NEXT: .LBB3_2:
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; RV64-NEXT: ret
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%1 = icmp slt i64 %x, 0
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%2 = sub nsw i64 0, %x
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%3 = select i1 %1, i64 %x, i64 %2
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ret i64 %3
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}
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