forked from OSchip/llvm-project
[AArch64][GlobalISel] Legalize G_INTRINSIC_TRUNC
Same patch as G_FCEIL etc. Add the missing switch case in widenScalar, add G_INTRINSIC_TRUNC to the correct rule in AArch64LegalizerInfo.cpp, and add a test. llvm-svn: 359021
This commit is contained in:
Jessica Paquette
parent
1670772adc
commit
56342642a0
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@ -1327,6 +1327,7 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
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case TargetOpcode::G_FEXP:
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case TargetOpcode::G_FEXP2:
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case TargetOpcode::G_FPOW:
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case TargetOpcode::G_INTRINSIC_TRUNC:
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assert(TypeIdx == 0);
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Observer.changingInstr(MI);
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@ -131,7 +131,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
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getActionDefinitionsBuilder(G_FREM).libcallFor({s32, s64});
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getActionDefinitionsBuilder(
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{G_FCEIL, G_FABS, G_FSQRT, G_FFLOOR, G_FRINT, G_FMA})
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{G_FCEIL, G_FABS, G_FSQRT, G_FFLOOR, G_FRINT, G_FMA, G_INTRINSIC_TRUNC})
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// If we don't have full FP16 support, then scalarize the elements of
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// vectors containing fp16 types.
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.fewerElementsIf(
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@ -0,0 +1,203 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc %s -verify-machineinstrs -mtriple=aarch64-unknown-unknown -run-pass=legalizer -simplify-mir -aarch64-neon-syntax=apple -mattr=-fullfp16 -o - | FileCheck %s --check-prefix=NO-FP16
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# RUN: llc %s -verify-machineinstrs -mtriple=aarch64-unknown-unknown -run-pass=legalizer -simplify-mir -aarch64-neon-syntax=apple -mattr=+fullfp16 -o - | FileCheck %s --check-prefix=FP16
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...
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---
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name: test_f16.intrinsic_trunc
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $h0
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; NO-FP16-LABEL: name: test_f16.intrinsic_trunc
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; NO-FP16: liveins: $h0
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; NO-FP16: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
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; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[COPY]](s16)
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; NO-FP16: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT]]
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; NO-FP16: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC]](s32)
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; NO-FP16: $h0 = COPY [[FPTRUNC]](s16)
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; NO-FP16: RET_ReallyLR implicit $h0
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; FP16-LABEL: name: test_f16.intrinsic_trunc
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; FP16: liveins: $h0
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; FP16: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
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; FP16: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[COPY]]
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; FP16: $h0 = COPY [[INTRINSIC_TRUNC]](s16)
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; FP16: RET_ReallyLR implicit $h0
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%0:_(s16) = COPY $h0
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%1:_(s16) = G_INTRINSIC_TRUNC %0
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$h0 = COPY %1(s16)
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RET_ReallyLR implicit $h0
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...
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---
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name: test_v4f16.intrinsic_trunc
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alignment: 2
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; NO-FP16-LABEL: name: test_v4f16.intrinsic_trunc
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; NO-FP16: liveins: $d0
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; NO-FP16: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
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; NO-FP16: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
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; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[UV]](s16)
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; NO-FP16: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT]]
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; NO-FP16: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC]](s32)
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; NO-FP16: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[UV1]](s16)
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; NO-FP16: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT1]]
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; NO-FP16: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC1]](s32)
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; NO-FP16: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[UV2]](s16)
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; NO-FP16: [[INTRINSIC_TRUNC2:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT2]]
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; NO-FP16: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC2]](s32)
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; NO-FP16: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[UV3]](s16)
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; NO-FP16: [[INTRINSIC_TRUNC3:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT3]]
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; NO-FP16: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC3]](s32)
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; NO-FP16: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[FPTRUNC]](s16), [[FPTRUNC1]](s16), [[FPTRUNC2]](s16), [[FPTRUNC3]](s16)
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; NO-FP16: $d0 = COPY [[BUILD_VECTOR]](<4 x s16>)
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; NO-FP16: RET_ReallyLR implicit $d0
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; FP16-LABEL: name: test_v4f16.intrinsic_trunc
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; FP16: liveins: $d0
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; FP16: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
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; FP16: [[INTRINSIC_TRUNC:%[0-9]+]]:_(<4 x s16>) = G_INTRINSIC_TRUNC [[COPY]]
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; FP16: $d0 = COPY [[INTRINSIC_TRUNC]](<4 x s16>)
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; FP16: RET_ReallyLR implicit $d0
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%0:_(<4 x s16>) = COPY $d0
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%1:_(<4 x s16>) = G_INTRINSIC_TRUNC %0
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$d0 = COPY %1(<4 x s16>)
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RET_ReallyLR implicit $d0
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...
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---
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name: test_v8f16.intrinsic_trunc
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alignment: 2
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $q0
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; NO-FP16-LABEL: name: test_v8f16.intrinsic_trunc
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; NO-FP16: liveins: $q0
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; NO-FP16: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
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; NO-FP16: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)
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; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[UV]](s16)
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; NO-FP16: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT]]
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; NO-FP16: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC]](s32)
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; NO-FP16: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[UV1]](s16)
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; NO-FP16: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT1]]
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; NO-FP16: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC1]](s32)
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; NO-FP16: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[UV2]](s16)
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; NO-FP16: [[INTRINSIC_TRUNC2:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT2]]
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; NO-FP16: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC2]](s32)
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; NO-FP16: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[UV3]](s16)
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; NO-FP16: [[INTRINSIC_TRUNC3:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT3]]
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; NO-FP16: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC3]](s32)
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; NO-FP16: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[UV4]](s16)
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; NO-FP16: [[INTRINSIC_TRUNC4:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT4]]
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; NO-FP16: [[FPTRUNC4:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC4]](s32)
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; NO-FP16: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[UV5]](s16)
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; NO-FP16: [[INTRINSIC_TRUNC5:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT5]]
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; NO-FP16: [[FPTRUNC5:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC5]](s32)
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; NO-FP16: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[UV6]](s16)
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; NO-FP16: [[INTRINSIC_TRUNC6:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT6]]
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; NO-FP16: [[FPTRUNC6:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC6]](s32)
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; NO-FP16: [[FPEXT7:%[0-9]+]]:_(s32) = G_FPEXT [[UV7]](s16)
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; NO-FP16: [[INTRINSIC_TRUNC7:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT7]]
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; NO-FP16: [[FPTRUNC7:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC7]](s32)
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; NO-FP16: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[FPTRUNC]](s16), [[FPTRUNC1]](s16), [[FPTRUNC2]](s16), [[FPTRUNC3]](s16), [[FPTRUNC4]](s16), [[FPTRUNC5]](s16), [[FPTRUNC6]](s16), [[FPTRUNC7]](s16)
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; NO-FP16: $q0 = COPY [[BUILD_VECTOR]](<8 x s16>)
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; NO-FP16: RET_ReallyLR implicit $q0
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; FP16-LABEL: name: test_v8f16.intrinsic_trunc
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; FP16: liveins: $q0
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; FP16: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
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; FP16: [[INTRINSIC_TRUNC:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC_TRUNC [[COPY]]
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; FP16: $q0 = COPY [[INTRINSIC_TRUNC]](<8 x s16>)
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; FP16: RET_ReallyLR implicit $q0
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%0:_(<8 x s16>) = COPY $q0
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%1:_(<8 x s16>) = G_INTRINSIC_TRUNC %0
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$q0 = COPY %1(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_v2f32.intrinsic_trunc
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alignment: 2
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; NO-FP16-LABEL: name: test_v2f32.intrinsic_trunc
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; NO-FP16: liveins: $d0
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; NO-FP16: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
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; NO-FP16: [[INTRINSIC_TRUNC:%[0-9]+]]:_(<2 x s32>) = G_INTRINSIC_TRUNC [[COPY]]
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; NO-FP16: $d0 = COPY [[INTRINSIC_TRUNC]](<2 x s32>)
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; NO-FP16: RET_ReallyLR implicit $d0
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; FP16-LABEL: name: test_v2f32.intrinsic_trunc
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; FP16: liveins: $d0
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; FP16: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
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; FP16: [[INTRINSIC_TRUNC:%[0-9]+]]:_(<2 x s32>) = G_INTRINSIC_TRUNC [[COPY]]
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; FP16: $d0 = COPY [[INTRINSIC_TRUNC]](<2 x s32>)
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; FP16: RET_ReallyLR implicit $d0
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%0:_(<2 x s32>) = COPY $d0
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%1:_(<2 x s32>) = G_INTRINSIC_TRUNC %0
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$d0 = COPY %1(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: test_v4f32.intrinsic_trunc
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alignment: 2
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $q0
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; NO-FP16-LABEL: name: test_v4f32.intrinsic_trunc
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; NO-FP16: liveins: $q0
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; NO-FP16: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; NO-FP16: [[INTRINSIC_TRUNC:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC_TRUNC [[COPY]]
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; NO-FP16: $q0 = COPY [[INTRINSIC_TRUNC]](<4 x s32>)
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; NO-FP16: RET_ReallyLR implicit $q0
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; FP16-LABEL: name: test_v4f32.intrinsic_trunc
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; FP16: liveins: $q0
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; FP16: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; FP16: [[INTRINSIC_TRUNC:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC_TRUNC [[COPY]]
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; FP16: $q0 = COPY [[INTRINSIC_TRUNC]](<4 x s32>)
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; FP16: RET_ReallyLR implicit $q0
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%0:_(<4 x s32>) = COPY $q0
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%1:_(<4 x s32>) = G_INTRINSIC_TRUNC %0
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$q0 = COPY %1(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_v2f64.intrinsic_trunc
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alignment: 2
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $q0
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; NO-FP16-LABEL: name: test_v2f64.intrinsic_trunc
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; NO-FP16: liveins: $q0
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; NO-FP16: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
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; NO-FP16: [[INTRINSIC_TRUNC:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC_TRUNC [[COPY]]
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; NO-FP16: $q0 = COPY [[INTRINSIC_TRUNC]](<2 x s64>)
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; NO-FP16: RET_ReallyLR implicit $q0
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; FP16-LABEL: name: test_v2f64.intrinsic_trunc
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; FP16: liveins: $q0
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; FP16: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
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; FP16: [[INTRINSIC_TRUNC:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC_TRUNC [[COPY]]
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; FP16: $q0 = COPY [[INTRINSIC_TRUNC]](<2 x s64>)
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; FP16: RET_ReallyLR implicit $q0
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%0:_(<2 x s64>) = COPY $q0
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%1:_(<2 x s64>) = G_INTRINSIC_TRUNC %0
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$q0 = COPY %1(<2 x s64>)
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RET_ReallyLR implicit $q0
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@ -88,7 +88,7 @@
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# DEBUG: .. the first uncovered type index: 2, OK
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#
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# DEBUG-NEXT: G_INTRINSIC_TRUNC (opcode {{[0-9]+}}): 1 type index
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# DEBUG: .. type index coverage check SKIPPED: no rules defined
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# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
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#
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# DEBUG-NEXT: G_INTRINSIC_ROUND (opcode {{[0-9]+}}): 1 type index
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# DEBUG: .. type index coverage check SKIPPED: no rules defined
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