Fix edge condition in DAGCombiner to improve codegen of shift sequences.

When canonicalizing dags according to the rule
(shl (zext (shr X, c1) ), c1) ==> (zext (shl (shr X, c1), c1))

remember to add the new shl dag to the DAGCombiner worklist of nodes.
If we don't explicitly add it to the worklist of nodes to visit, we
may not trigger later on the rule that folds the shift left + logical
shift right into a AND instruction with bitmask.

llvm-svn: 192883

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

@@ -3794,6 +3794,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
         EVT CountVT = NewOp0.getOperand(1).getValueType();
         SDValue NewSHL = DAG.getNode(ISD::SHL, SDLoc(N), NewOp0.getValueType(),
                                      NewOp0, DAG.getConstant(c2, CountVT));
+        AddToWorkList(NewSHL.getNode());
         return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N0), VT, NewSHL);
       }
     }

llvm/test/CodeGen/X86/dagcombine-shifts.ll

@@ -187,6 +187,8 @@ entry:
 ; Once the add is removed, the number of uses becomes one and therefore the
 ; dags are canonicalized. After Legalization, we need to make sure that the
 ; valuetype for the shift count is legal.
+; Verify also that we correctly fold the shl-shr sequence into an 
+; AND with bitmask.
 
 define void @g(i32 %a) {
   %b = lshr i32 %a, 2
@@ -197,5 +199,11 @@ define void @g(i32 %a) {
   ret void
 }
 
+; CHECK-LABEL: @g
+; CHECK-NOT: shr
+; CHECK-NOT: shl
+; CHECK: and
+; CHECK-NEXT: jmp
+
 declare void @f(i64)