forked from OSchip/llvm-project
[SparcV9] Add ctpop instruction for i64. Also, expand ctlz, cttz and bswap.
llvm-svn: 193941
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@ -1397,6 +1397,13 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::SETCC, MVT::i64, Expand);
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setOperationAction(ISD::SETCC, MVT::i64, Expand);
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setOperationAction(ISD::BR_CC, MVT::i64, Custom);
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setOperationAction(ISD::BR_CC, MVT::i64, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
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setOperationAction(ISD::CTPOP, MVT::i64, Legal);
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setOperationAction(ISD::CTTZ , MVT::i64, Expand);
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setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
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setOperationAction(ISD::CTLZ , MVT::i64, Expand);
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setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
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setOperationAction(ISD::BSWAP, MVT::i64, Expand);
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}
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}
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// FIXME: There are instructions available for ATOMIC_FENCE
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// FIXME: There are instructions available for ATOMIC_FENCE
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@ -169,6 +169,8 @@ def : Pat<(sub i64:$a, (i64 simm13:$b)), (SUBri $a, (as_i32imm $b))>;
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def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>;
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def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>;
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def : Pat<(ctpop i64:$src), (POPCrr $src)>;
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} // Predicates = [Is64Bit]
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} // Predicates = [Is64Bit]
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@ -285,3 +285,26 @@ entry:
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store i64 0, i64* %0, align 8
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store i64 0, i64* %0, align 8
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ret i64 0
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ret i64 0
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}
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}
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; CHECK-LABEL: bit_ops
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; CHECK: popc
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; OPT-LABEL: bit_ops
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; OPT: popc
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define i64 @bit_ops(i64 %arg) {
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entry:
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%0 = tail call i64 @llvm.ctpop.i64(i64 %arg)
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%1 = tail call i64 @llvm.ctlz.i64(i64 %arg, i1 true)
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%2 = tail call i64 @llvm.cttz.i64(i64 %arg, i1 true)
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%3 = tail call i64 @llvm.bswap.i64(i64 %arg)
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%4 = add i64 %0, %1
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%5 = add i64 %2, %3
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%6 = add i64 %4, %5
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ret i64 %6
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}
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declare i64 @llvm.ctpop.i64(i64) nounwind readnone
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declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
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declare i64 @llvm.cttz.i64(i64, i1) nounwind readnone
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declare i64 @llvm.bswap.i64(i64) nounwind readnone
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