forked from OSchip/llvm-project
[X86] Create some wrapper multiclasses to create AVX and SSE shift instructions with less repeated code. NFC
llvm-svn: 276085
This commit is contained in:
Craig Topper
parent
b66b621038
commit
55913ead3d
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@ -3915,37 +3915,6 @@ let Predicates = [HasAVX2] in
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IsCommutable, 0>, VEX_4V, VEX_L;
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}
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multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
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string OpcodeStr, SDNode OpNode,
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SDNode OpNode2, RegisterClass RC,
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ValueType DstVT, ValueType SrcVT,
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PatFrag ld_frag, ShiftOpndItins itins,
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bit Is2Addr = 1> {
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// src2 is always 128-bit
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def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, VR128:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
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itins.rr>, Sched<[WriteVecShift]>;
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def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, i128mem:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (DstVT (OpNode RC:$src1,
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(SrcVT (bitconvert (ld_frag addr:$src2))))))], itins.rm>,
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Sched<[WriteVecShiftLd, ReadAfterLd]>;
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def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
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(ins RC:$src1, u8imm:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))], itins.ri>,
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Sched<[WriteVecShift]>;
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}
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/// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
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multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
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ValueType DstVT, ValueType SrcVT, RegisterClass RC,
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@ -4053,152 +4022,101 @@ defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
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// SSE2 - Packed Integer Logical Instructions
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//===---------------------------------------------------------------------===//
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let Predicates = [HasAVX, NoVLX] in {
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defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
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VR128, v4i32, v4i32, loadv2i64,
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SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
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defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
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VR128, v2i64, v2i64, loadv2i64,
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SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
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defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
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VR128, v4i32, v4i32, loadv2i64,
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SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
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defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
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VR128, v2i64, v2i64, loadv2i64,
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SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
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defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
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VR128, v4i32, v4i32, loadv2i64,
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SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
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} // Predicates = [HasAVX, NoVLX]
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let Predicates = [HasAVX, NoVLX_Or_NoBWI] in {
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defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
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VR128, v8i16, v8i16, loadv2i64,
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SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
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defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
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VR128, v8i16, v8i16, loadv2i64,
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SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
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defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
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VR128, v8i16, v8i16, loadv2i64,
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SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
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} // Predicates = [HasAVX, NoVLX_Or_NoBWI]
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let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] ,
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Predicates = [HasAVX, NoVLX_Or_NoBWI]in {
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// 128-bit logical shifts.
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def VPSLLDQri : PDIi8<0x73, MRM7r,
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(outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
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"vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR128:$dst,
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(v16i8 (X86vshldq VR128:$src1, (i8 imm:$src2))))]>,
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VEX_4V;
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def VPSRLDQri : PDIi8<0x73, MRM3r,
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(outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
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"vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR128:$dst,
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(v16i8 (X86vshrdq VR128:$src1, (i8 imm:$src2))))]>,
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VEX_4V;
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// PSRADQri doesn't exist in SSE[1-3].
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} // Predicates = [HasAVX, NoVLX_Or_NoBWI]
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let Predicates = [HasAVX2, NoVLX] in {
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defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
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VR256, v8i32, v4i32, loadv2i64,
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SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
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defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
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VR256, v4i64, v2i64, loadv2i64,
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SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
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defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
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VR256, v8i32, v4i32, loadv2i64,
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SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
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defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
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VR256, v4i64, v2i64, loadv2i64,
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SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
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defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
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VR256, v8i32, v4i32, loadv2i64,
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SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
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}// Predicates = [HasAVX2, NoVLX]
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let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in {
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defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
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VR256, v16i16, v8i16, loadv2i64,
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SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
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defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
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VR256, v16i16, v8i16, loadv2i64,
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SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
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defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
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VR256, v16i16, v8i16, loadv2i64,
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SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
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}// Predicates = [HasAVX2, NoVLX_Or_NoBWI]
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let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift], hasSideEffects = 0 ,
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Predicates = [HasAVX2, NoVLX_Or_NoBWI] in {
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// 256-bit logical shifts.
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def VPSLLDQYri : PDIi8<0x73, MRM7r,
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(outs VR256:$dst), (ins VR256:$src1, u8imm:$src2),
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"vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR256:$dst,
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(v32i8 (X86vshldq VR256:$src1, (i8 imm:$src2))))]>,
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VEX_4V, VEX_L;
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def VPSRLDQYri : PDIi8<0x73, MRM3r,
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(outs VR256:$dst), (ins VR256:$src1, u8imm:$src2),
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"vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR256:$dst,
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(v32i8 (X86vshrdq VR256:$src1, (i8 imm:$src2))))]>,
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VEX_4V, VEX_L;
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// PSRADQYri doesn't exist in SSE[1-3].
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} // Predicates = [HasAVX2, NoVLX_Or_NoBWI]
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let Constraints = "$src1 = $dst" in {
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defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
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VR128, v8i16, v8i16, memopv2i64,
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SSE_INTSHIFT_ITINS_P>;
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defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
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VR128, v4i32, v4i32, memopv2i64,
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SSE_INTSHIFT_ITINS_P>;
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defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
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VR128, v2i64, v2i64, memopv2i64,
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SSE_INTSHIFT_ITINS_P>;
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defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
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VR128, v8i16, v8i16, memopv2i64,
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SSE_INTSHIFT_ITINS_P>;
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defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
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VR128, v4i32, v4i32, memopv2i64,
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SSE_INTSHIFT_ITINS_P>;
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defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
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VR128, v2i64, v2i64, memopv2i64,
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SSE_INTSHIFT_ITINS_P>;
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defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
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VR128, v8i16, v8i16, memopv2i64,
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SSE_INTSHIFT_ITINS_P>;
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defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
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VR128, v4i32, v4i32, memopv2i64,
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SSE_INTSHIFT_ITINS_P>;
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let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift], hasSideEffects = 0 in {
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// 128-bit logical shifts.
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def PSLLDQri : PDIi8<0x73, MRM7r,
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(outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
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"pslldq\t{$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v16i8 (X86vshldq VR128:$src1, (i8 imm:$src2))))],
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IIC_SSE_INTSHDQ_P_RI>;
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def PSRLDQri : PDIi8<0x73, MRM3r,
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(outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
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"psrldq\t{$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v16i8 (X86vshrdq VR128:$src1, (i8 imm:$src2))))],
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IIC_SSE_INTSHDQ_P_RI>;
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// PSRADQri doesn't exist in SSE[1-3].
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multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
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string OpcodeStr, SDNode OpNode,
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SDNode OpNode2, RegisterClass RC,
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ValueType DstVT, ValueType SrcVT,
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PatFrag ld_frag, bit Is2Addr = 1> {
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// src2 is always 128-bit
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def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, VR128:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
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SSE_INTSHIFT_ITINS_P.rr>, Sched<[WriteVecShift]>;
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def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, i128mem:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (DstVT (OpNode RC:$src1,
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(SrcVT (bitconvert (ld_frag addr:$src2))))))],
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SSE_INTSHIFT_ITINS_P.rm>, Sched<[WriteVecShiftLd, ReadAfterLd]>;
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def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
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(ins RC:$src1, u8imm:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))],
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SSE_INTSHIFT_ITINS_P.ri>, Sched<[WriteVecShift]>;
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}
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} // Constraints = "$src1 = $dst"
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multiclass PDI_binop_rmi_all<bits<8> opc, bits<8> opc2, Format ImmForm,
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string OpcodeStr, SDNode OpNode,
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SDNode OpNode2, ValueType DstVT128,
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ValueType DstVT256, ValueType SrcVT,
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Predicate prd> {
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let Predicates = [HasAVX, prd] in
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defm V#NAME : PDI_binop_rmi<opc, opc2, ImmForm, !strconcat("v", OpcodeStr),
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OpNode, OpNode2, VR128, DstVT128, SrcVT,
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loadv2i64, 0>, VEX_4V;
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let Predicates = [HasAVX2, prd] in
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defm V#NAME#Y : PDI_binop_rmi<opc, opc2, ImmForm, !strconcat("v", OpcodeStr),
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OpNode, OpNode2, VR256, DstVT256, SrcVT,
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loadv2i64, 0>, VEX_4V, VEX_L;
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let Constraints = "$src1 = $dst" in
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defm NAME : PDI_binop_rmi<opc, opc2, ImmForm, OpcodeStr, OpNode, OpNode2,
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VR128, DstVT128, SrcVT, memopv2i64>;
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}
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multiclass PDI_binop_ri<bits<8> opc, Format ImmForm, string OpcodeStr,
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SDNode OpNode, RegisterClass RC, ValueType VT,
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bit Is2Addr = 1> {
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def ri : PDIi8<opc, ImmForm, (outs RC:$dst), (ins RC:$src1, u8imm:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (VT (OpNode RC:$src1, (i8 imm:$src2))))],
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IIC_SSE_INTSHDQ_P_RI>, Sched<[WriteVecShift]>;
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}
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multiclass PDI_binop_ri_all<bits<8> opc, Format ImmForm, string OpcodeStr,
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SDNode OpNode> {
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let Predicates = [HasAVX, NoVLX_Or_NoBWI] in
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defm V#NAME : PDI_binop_ri<opc, ImmForm, !strconcat("v", OpcodeStr), OpNode,
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VR128, v16i8, 0>, VEX_4V;
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let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in
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defm V#NAME#Y : PDI_binop_ri<opc, ImmForm, !strconcat("v", OpcodeStr), OpNode,
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VR256, v32i8, 0>, VEX_4V, VEX_L;
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let Constraints = "$src1 = $dst" in
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defm NAME : PDI_binop_ri<opc, ImmForm, OpcodeStr, OpNode, VR128, v16i8>;
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}
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let ExeDomain = SSEPackedInt in {
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defm PSLLW : PDI_binop_rmi_all<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
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v8i16, v16i16, v8i16, NoVLX_Or_NoBWI>;
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defm PSLLD : PDI_binop_rmi_all<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
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v4i32, v8i32, v4i32, NoVLX>;
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defm PSLLQ : PDI_binop_rmi_all<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
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v2i64, v4i64, v2i64, NoVLX>;
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defm PSRLW : PDI_binop_rmi_all<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
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v8i16, v16i16, v8i16, NoVLX_Or_NoBWI>;
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defm PSRLD : PDI_binop_rmi_all<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
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v4i32, v8i32, v4i32, NoVLX>;
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defm PSRLQ : PDI_binop_rmi_all<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
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v2i64, v4i64, v2i64, NoVLX>;
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defm PSRAW : PDI_binop_rmi_all<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
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v8i16, v16i16, v8i16, NoVLX_Or_NoBWI>;
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defm PSRAD : PDI_binop_rmi_all<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
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v4i32, v8i32, v4i32, NoVLX>;
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defm PSLLDQ : PDI_binop_ri_all<0x73, MRM7r, "pslldq", X86vshldq>;
|
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defm PSRLDQ : PDI_binop_ri_all<0x73, MRM3r, "psrldq", X86vshrdq>;
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// PSRADQri doesn't exist in SSE[1-3].
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} // ExeDomain = SSEPackedInt
|
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|
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//===---------------------------------------------------------------------===//
|
||||
// SSE2 - Packed Integer Comparison Instructions
|
||||
|
|
|
|||
Loading…
Reference in New Issue