diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp index a804857cc201..f9724882272a 100644 --- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp +++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp @@ -106,7 +106,7 @@ static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, @@ -115,13 +115,13 @@ static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, @@ -481,10 +481,10 @@ static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable); } -static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t /*Address*/, - const void *Decoder) { - static const MCPhysReg VecRegDecoderTable[] = { +static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t /*Address*/, + const void *Decoder) { + static const MCPhysReg HvxVRDecoderTable[] = { Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9, Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, @@ -493,7 +493,7 @@ static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo, Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29, Hexagon::V30, Hexagon::V31}; - return DecodeRegisterClass(Inst, RegNo, VecRegDecoderTable); + return DecodeRegisterClass(Inst, RegNo, HvxVRDecoderTable); } static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, @@ -517,16 +517,16 @@ static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass( return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable); } -static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t /*Address*/, - const void *Decoder) { - static const MCPhysReg VecDblRegDecoderTable[] = { +static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t /*Address*/, + const void *Decoder) { + static const MCPhysReg HvxWRDecoderTable[] = { Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7, Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11, Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15}; - return (DecodeRegisterClass(Inst, RegNo >> 1, VecDblRegDecoderTable)); + return (DecodeRegisterClass(Inst, RegNo >> 1, HvxWRDecoderTable)); } static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, @@ -538,13 +538,13 @@ static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable); } -static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t /*Address*/, - const void *Decoder) { - static const MCPhysReg VecPredRegDecoderTable[] = {Hexagon::Q0, Hexagon::Q1, - Hexagon::Q2, Hexagon::Q3}; +static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t /*Address*/, + const void *Decoder) { + static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1, + Hexagon::Q2, Hexagon::Q3}; - return DecodeRegisterClass(Inst, RegNo, VecPredRegDecoderTable); + return DecodeRegisterClass(Inst, RegNo, HvxQRDecoderTable); } static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, diff --git a/llvm/lib/Target/Hexagon/Hexagon.td b/llvm/lib/Target/Hexagon/Hexagon.td index 4767165141a3..df6f3ea1f168 100644 --- a/llvm/lib/Target/Hexagon/Hexagon.td +++ b/llvm/lib/Target/Hexagon/Hexagon.td @@ -44,6 +44,9 @@ def UseHVXSgl : Predicate<"HST->useHVXSglOps()">; def UseHVX : Predicate<"HST->useHVXSglOps() ||HST->useHVXDblOps()">, AssemblerPredicate<"ExtensionHVX">; +def Hvx64 : HwMode<"+hvx,-hvx-double">; +def Hvx128 : HwMode<"+hvx,+hvx-double">; + //===----------------------------------------------------------------------===// // Classes used for relation maps. //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp index ba76492e7dd6..3f7963208739 100644 --- a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp +++ b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp @@ -281,10 +281,8 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, MCInst &MappedInst = static_cast (Inst); const MCRegisterInfo *RI = OutStreamer->getContext().getRegisterInfo(); const MachineFunction &MF = *MI.getParent()->getParent(); - const auto &HST = MF.getSubtarget(); - const auto &VecRC = HST.useHVXSglOps() ? Hexagon::VectorRegsRegClass - : Hexagon::VectorRegs128BRegClass; - unsigned VectorSize = HST.getRegisterInfo()->getSpillSize(VecRC); + auto &HRI = *MF.getSubtarget().getRegisterInfo(); + unsigned VectorSize = HRI.getRegSizeInBits(Hexagon::HvxVRRegClass) / 8; switch (Inst.getOpcode()) { default: return; @@ -605,8 +603,7 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, return; } - case Hexagon::V6_vd0: - case Hexagon::V6_vd0_128B: { + case Hexagon::V6_vd0: { MCInst TmpInst; assert(Inst.getOperand(0).isReg() && "Expected register and none was found"); @@ -626,13 +623,6 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, case Hexagon::V6_vL32b_nt_pi: case Hexagon::V6_vL32b_nt_tmp_pi: case Hexagon::V6_vL32b_tmp_pi: - case Hexagon::V6_vL32Ub_pi_128B: - case Hexagon::V6_vL32b_cur_pi_128B: - case Hexagon::V6_vL32b_nt_cur_pi_128B: - case Hexagon::V6_vL32b_pi_128B: - case Hexagon::V6_vL32b_nt_pi_128B: - case Hexagon::V6_vL32b_nt_tmp_pi_128B: - case Hexagon::V6_vL32b_tmp_pi_128B: MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext); return; @@ -643,13 +633,6 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, case Hexagon::V6_vL32b_nt_cur_ai: case Hexagon::V6_vL32b_nt_tmp_ai: case Hexagon::V6_vL32b_tmp_ai: - case Hexagon::V6_vL32Ub_ai_128B: - case Hexagon::V6_vL32b_ai_128B: - case Hexagon::V6_vL32b_cur_ai_128B: - case Hexagon::V6_vL32b_nt_ai_128B: - case Hexagon::V6_vL32b_nt_cur_ai_128B: - case Hexagon::V6_vL32b_nt_tmp_ai_128B: - case Hexagon::V6_vL32b_tmp_ai_128B: MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext); return; @@ -658,11 +641,6 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, case Hexagon::V6_vS32b_nt_new_pi: case Hexagon::V6_vS32b_nt_pi: case Hexagon::V6_vS32b_pi: - case Hexagon::V6_vS32Ub_pi_128B: - case Hexagon::V6_vS32b_new_pi_128B: - case Hexagon::V6_vS32b_nt_new_pi_128B: - case Hexagon::V6_vS32b_nt_pi_128B: - case Hexagon::V6_vS32b_pi_128B: MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext); return; @@ -671,11 +649,6 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, case Hexagon::V6_vS32b_new_ai: case Hexagon::V6_vS32b_nt_ai: case Hexagon::V6_vS32b_nt_new_ai: - case Hexagon::V6_vS32Ub_ai_128B: - case Hexagon::V6_vS32b_ai_128B: - case Hexagon::V6_vS32b_new_ai_128B: - case Hexagon::V6_vS32b_nt_ai_128B: - case Hexagon::V6_vS32b_nt_new_ai_128B: MappedInst = ScaleVectorOffset(Inst, 1, VectorSize, OutContext); return; @@ -691,18 +664,6 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, case Hexagon::V6_vL32b_pred_pi: case Hexagon::V6_vL32b_tmp_npred_pi: case Hexagon::V6_vL32b_tmp_pred_pi: - case Hexagon::V6_vL32b_cur_npred_pi_128B: - case Hexagon::V6_vL32b_cur_pred_pi_128B: - case Hexagon::V6_vL32b_npred_pi_128B: - case Hexagon::V6_vL32b_nt_cur_npred_pi_128B: - case Hexagon::V6_vL32b_nt_cur_pred_pi_128B: - case Hexagon::V6_vL32b_nt_npred_pi_128B: - case Hexagon::V6_vL32b_nt_pred_pi_128B: - case Hexagon::V6_vL32b_nt_tmp_npred_pi_128B: - case Hexagon::V6_vL32b_nt_tmp_pred_pi_128B: - case Hexagon::V6_vL32b_pred_pi_128B: - case Hexagon::V6_vL32b_tmp_npred_pi_128B: - case Hexagon::V6_vL32b_tmp_pred_pi_128B: MappedInst = ScaleVectorOffset(Inst, 4, VectorSize, OutContext); return; @@ -718,18 +679,6 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, case Hexagon::V6_vL32b_pred_ai: case Hexagon::V6_vL32b_tmp_npred_ai: case Hexagon::V6_vL32b_tmp_pred_ai: - case Hexagon::V6_vL32b_cur_npred_ai_128B: - case Hexagon::V6_vL32b_cur_pred_ai_128B: - case Hexagon::V6_vL32b_npred_ai_128B: - case Hexagon::V6_vL32b_nt_cur_npred_ai_128B: - case Hexagon::V6_vL32b_nt_cur_pred_ai_128B: - case Hexagon::V6_vL32b_nt_npred_ai_128B: - case Hexagon::V6_vL32b_nt_pred_ai_128B: - case Hexagon::V6_vL32b_nt_tmp_npred_ai_128B: - case Hexagon::V6_vL32b_nt_tmp_pred_ai_128B: - case Hexagon::V6_vL32b_pred_ai_128B: - case Hexagon::V6_vL32b_tmp_npred_ai_128B: - case Hexagon::V6_vL32b_tmp_pred_ai_128B: MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext); return; @@ -747,20 +696,6 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, case Hexagon::V6_vS32b_nt_qpred_pi: case Hexagon::V6_vS32b_pred_pi: case Hexagon::V6_vS32b_qpred_pi: - case Hexagon::V6_vS32Ub_npred_pi_128B: - case Hexagon::V6_vS32Ub_pred_pi_128B: - case Hexagon::V6_vS32b_new_npred_pi_128B: - case Hexagon::V6_vS32b_new_pred_pi_128B: - case Hexagon::V6_vS32b_npred_pi_128B: - case Hexagon::V6_vS32b_nqpred_pi_128B: - case Hexagon::V6_vS32b_nt_new_npred_pi_128B: - case Hexagon::V6_vS32b_nt_new_pred_pi_128B: - case Hexagon::V6_vS32b_nt_npred_pi_128B: - case Hexagon::V6_vS32b_nt_nqpred_pi_128B: - case Hexagon::V6_vS32b_nt_pred_pi_128B: - case Hexagon::V6_vS32b_nt_qpred_pi_128B: - case Hexagon::V6_vS32b_pred_pi_128B: - case Hexagon::V6_vS32b_qpred_pi_128B: MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext); return; @@ -778,20 +713,6 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, case Hexagon::V6_vS32b_nt_qpred_ai: case Hexagon::V6_vS32b_pred_ai: case Hexagon::V6_vS32b_qpred_ai: - case Hexagon::V6_vS32Ub_npred_ai_128B: - case Hexagon::V6_vS32Ub_pred_ai_128B: - case Hexagon::V6_vS32b_new_npred_ai_128B: - case Hexagon::V6_vS32b_new_pred_ai_128B: - case Hexagon::V6_vS32b_npred_ai_128B: - case Hexagon::V6_vS32b_nqpred_ai_128B: - case Hexagon::V6_vS32b_nt_new_npred_ai_128B: - case Hexagon::V6_vS32b_nt_new_pred_ai_128B: - case Hexagon::V6_vS32b_nt_npred_ai_128B: - case Hexagon::V6_vS32b_nt_nqpred_ai_128B: - case Hexagon::V6_vS32b_nt_pred_ai_128B: - case Hexagon::V6_vS32b_nt_qpred_ai_128B: - case Hexagon::V6_vS32b_pred_ai_128B: - case Hexagon::V6_vS32b_qpred_ai_128B: MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext); return; } diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp index c360f09517eb..09aa3938c446 100644 --- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp @@ -420,8 +420,7 @@ bool HexagonBitSimplify::getSubregMask(const BitTracker::RegisterRef &RR, switch (RC->getID()) { case Hexagon::DoubleRegsRegClassID: - case Hexagon::VecDblRegsRegClassID: - case Hexagon::VecDblRegs128BRegClassID: + case Hexagon::HvxWRRegClassID: Width = MRI.getTargetRegisterInfo()->getRegSizeInBits(*RC) / 2; if (RR.Sub == Hexagon::isub_hi || RR.Sub == Hexagon::vsub_hi) Begin = Width; @@ -918,12 +917,9 @@ const TargetRegisterClass *HexagonBitSimplify::getFinalVRegClass( case Hexagon::DoubleRegsRegClassID: VerifySR(RC, RR.Sub); return &Hexagon::IntRegsRegClass; - case Hexagon::VecDblRegsRegClassID: + case Hexagon::HvxWRRegClassID: VerifySR(RC, RR.Sub); - return &Hexagon::VectorRegsRegClass; - case Hexagon::VecDblRegs128BRegClassID: - VerifySR(RC, RR.Sub); - return &Hexagon::VectorRegs128BRegClass; + return &Hexagon::HvxVRRegClass; } return nullptr; } @@ -1627,8 +1623,7 @@ bool CopyGeneration::processBlock(MachineBasicBlock &B, } if (FRC == &Hexagon::DoubleRegsRegClass || - FRC == &Hexagon::VecDblRegsRegClass || - FRC == &Hexagon::VecDblRegs128BRegClass) { + FRC == &Hexagon::HvxWRRegClass) { // Try to generate REG_SEQUENCE. unsigned SubLo = HRI.getHexagonSubRegIndex(FRC, Hexagon::ps_sub_lo); unsigned SubHi = HRI.getHexagonSubRegIndex(FRC, Hexagon::ps_sub_hi); @@ -1665,7 +1660,6 @@ bool CopyPropagation::isCopyReg(unsigned Opc, bool NoConv) { case Hexagon::A2_tfrp: case Hexagon::A2_combinew: case Hexagon::V6_vcombine: - case Hexagon::V6_vcombine_128B: return NoConv; default: break; @@ -1704,8 +1698,7 @@ bool CopyPropagation::propagateRegCopy(MachineInstr &MI) { break; } case Hexagon::A2_combinew: - case Hexagon::V6_vcombine: - case Hexagon::V6_vcombine_128B: { + case Hexagon::V6_vcombine: { const TargetRegisterClass *RC = MRI.getRegClass(RD.Reg); unsigned SubLo = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo); unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); diff --git a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp index d88df8035bc6..610fc2598f81 100644 --- a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp @@ -102,8 +102,7 @@ BT::BitMask HexagonEvaluator::mask(unsigned Reg, unsigned Sub) const { bool IsSubLo = (Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo)); switch (ID) { case DoubleRegsRegClassID: - case VecDblRegsRegClassID: - case VecDblRegs128BRegClassID: + case HvxWRRegClassID: return IsSubLo ? BT::BitMask(0, RW-1) : BT::BitMask(RW, 2*RW-1); default: @@ -703,7 +702,6 @@ bool HexagonEvaluator::evaluate(const MachineInstr &MI, case A4_combineri: case A2_combinew: case V6_vcombine: - case V6_vcombine_128B: assert(W0 % 2 == 0); return rr0(cop(2, W0/2).cat(cop(1, W0/2)), Outputs); case A2_combine_ll: diff --git a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp index 86c877efb781..d7cc6f5ea28e 100644 --- a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp @@ -161,7 +161,6 @@ static bool isCombinableInstType(MachineInstr &MI, const HexagonInstrInfo *TII, } case Hexagon::V6_vassign: - case Hexagon::V6_vassign_128B: return true; default: @@ -231,8 +230,7 @@ static bool isEvenReg(unsigned Reg) { assert(TargetRegisterInfo::isPhysicalRegister(Reg)); if (Hexagon::IntRegsRegClass.contains(Reg)) return (Reg - Hexagon::R0) % 2 == 0; - if (Hexagon::VectorRegsRegClass.contains(Reg) || - Hexagon::VectorRegs128BRegClass.contains(Reg)) + if (Hexagon::HvxVRRegClass.contains(Reg)) return (Reg - Hexagon::V0) % 2 == 0; llvm_unreachable("Invalid register"); } @@ -593,12 +591,9 @@ void HexagonCopyToCombine::combine(MachineInstr &I1, MachineInstr &I2, if (Hexagon::IntRegsRegClass.contains(LoRegDef)) { SuperRC = &Hexagon::DoubleRegsRegClass; SubLo = Hexagon::isub_lo; - } else if (Hexagon::VectorRegsRegClass.contains(LoRegDef)) { + } else if (Hexagon::HvxVRRegClass.contains(LoRegDef)) { assert(ST->useHVXOps()); - if (ST->useHVXSglOps()) - SuperRC = &Hexagon::VecDblRegsRegClass; - else - SuperRC = &Hexagon::VecDblRegs128BRegClass; + SuperRC = &Hexagon::HvxWRRegClass; SubLo = Hexagon::vsub_lo; } else llvm_unreachable("Unexpected register class"); @@ -875,12 +870,9 @@ void HexagonCopyToCombine::emitCombineRR(MachineBasicBlock::iterator &InsertPt, unsigned NewOpc; if (Hexagon::DoubleRegsRegClass.contains(DoubleDestReg)) { NewOpc = Hexagon::A2_combinew; - } else if (Hexagon::VecDblRegsRegClass.contains(DoubleDestReg)) { + } else if (Hexagon::HvxWRRegClass.contains(DoubleDestReg)) { assert(ST->useHVXOps()); - if (ST->useHVXSglOps()) - NewOpc = Hexagon::V6_vcombine; - else - NewOpc = Hexagon::V6_vcombine_128B; + NewOpc = Hexagon::V6_vcombine; } else llvm_unreachable("Unexpected register"); diff --git a/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td index 30ebf89c9808..9d36b2d263b0 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td @@ -25541,8 +25541,8 @@ let mayStore = 1; let DecoderNamespace = "SUBINSN_S2"; } def V6_MAP_equb : HInst< -(outs VecPredRegs:$Qd4), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qd4), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.eq($Vu32.ub,$Vv32.ub)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -25551,21 +25551,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_MAP_equb_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qd4 = vcmp.eq($Vu32.ub,$Vv32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_MAP_equb_and : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.eq($Vu32.ub,$Vv32.ub)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -25575,22 +25563,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_MAP_equb_and_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 &= vcmp.eq($Vu32.ub,$Vv32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_MAP_equb_ior : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.eq($Vu32.ub,$Vv32.ub)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -25601,23 +25576,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_MAP_equb_ior_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 |= vcmp.eq($Vu32.ub,$Vv32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_MAP_equb_xor : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.eq($Vu32.ub,$Vv32.ub)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -25627,22 +25588,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_MAP_equb_xor_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 ^= vcmp.eq($Vu32.ub,$Vv32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_MAP_equh : HInst< -(outs VecPredRegs:$Qd4), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qd4), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.eq($Vu32.uh,$Vv32.uh)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -25651,21 +25599,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_MAP_equh_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qd4 = vcmp.eq($Vu32.uh,$Vv32.uh)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_MAP_equh_and : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.eq($Vu32.uh,$Vv32.uh)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -25675,22 +25611,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_MAP_equh_and_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 &= vcmp.eq($Vu32.uh,$Vv32.uh)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_MAP_equh_ior : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.eq($Vu32.uh,$Vv32.uh)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -25701,23 +25624,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_MAP_equh_ior_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 |= vcmp.eq($Vu32.uh,$Vv32.uh)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_MAP_equh_xor : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.eq($Vu32.uh,$Vv32.uh)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -25727,22 +25636,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_MAP_equh_xor_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 ^= vcmp.eq($Vu32.uh,$Vv32.uh)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_MAP_equw : HInst< -(outs VecPredRegs:$Qd4), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qd4), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.eq($Vu32.uw,$Vv32.uw)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -25751,21 +25647,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_MAP_equw_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qd4 = vcmp.eq($Vu32.uw,$Vv32.uw)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_MAP_equw_and : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.eq($Vu32.uw,$Vv32.uw)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -25775,22 +25659,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_MAP_equw_and_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 &= vcmp.eq($Vu32.uw,$Vv32.uw)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_MAP_equw_ior : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.eq($Vu32.uw,$Vv32.uw)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -25801,23 +25672,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_MAP_equw_ior_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 |= vcmp.eq($Vu32.uw,$Vv32.uw)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_MAP_equw_xor : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.eq($Vu32.uw,$Vv32.uw)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -25827,22 +25684,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_MAP_equw_xor_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 ^= vcmp.eq($Vu32.uw,$Vv32.uw)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_extractw : HInst< (outs IntRegs:$Rd32), -(ins VectorRegs:$Vu32, IntRegs:$Rs32), +(ins HvxVR:$Vu32, IntRegs:$Rs32), "$Rd32 = vextract($Vu32,$Rs32)", tc_9777e6bf, TypeLD>, Enc_50e578, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -25854,24 +25698,9 @@ let isSolo = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_extractw_128B : HInst< -(outs IntRegs:$Rd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rs32), -"$Rd32 = vextract($Vu32,$Rs32)", -tc_9777e6bf, TypeLD>, Enc_50e578, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b10010010000; -let hasNewValue = 1; -let opNewValue = 0; -let isSolo = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_extractw_alt : HInst< (outs IntRegs:$Rd32), -(ins VectorRegs:$Vu32, IntRegs:$Rs32), +(ins HvxVR:$Vu32, IntRegs:$Rs32), "$Rd32.w = vextract($Vu32,$Rs32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -25880,21 +25709,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_extractw_alt_128B : HInst< -(outs IntRegs:$Rd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rs32), -"$Rd32.w = vextract($Vu32,$Rs32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_hi : HInst< -(outs VectorRegs:$Vd32), -(ins VecDblRegs:$Vss32), +(outs HvxVR:$Vd32), +(ins HvxWR:$Vss32), "$Vd32 = hi($Vss32)", CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -25902,19 +25719,8 @@ let opNewValue = 0; let isPseudo = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_hi_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VecDblRegs128B:$Vss32), -"$Vd32 = hi($Vss32)", -CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_ld0 : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins IntRegs:$Rt32), "$Vd32 = vmem($Rt32)", PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> { @@ -25924,20 +25730,8 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_ld0_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins IntRegs:$Rt32), -"$Vd32 = vmem($Rt32)", -PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_ldcnp0 : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32), "if (!$Pv4) $Vd32.cur = vmem($Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { @@ -25947,20 +25741,8 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_ldcnp0_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32), -"if (!$Pv4) $Vd32.cur = vmem($Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_ldcnpnt0 : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32), "if (!$Pv4) $Vd32.cur = vmem($Rt32):nt", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { @@ -25970,20 +25752,8 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_ldcnpnt0_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32), -"if (!$Pv4) $Vd32.cur = vmem($Rt32):nt", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_ldcp0 : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32), "if ($Pv4) $Vd32.cur = vmem($Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { @@ -25993,20 +25763,8 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_ldcp0_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32), -"if ($Pv4) $Vd32.cur = vmem($Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_ldcpnt0 : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32), "if ($Pv4) $Vd32.cur = vmem($Rt32):nt", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { @@ -26016,20 +25774,8 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_ldcpnt0_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32), -"if ($Pv4) $Vd32.cur = vmem($Rt32):nt", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_ldnp0 : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32), "if (!$Pv4) $Vd32 = vmem($Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { @@ -26039,20 +25785,8 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_ldnp0_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32), -"if (!$Pv4) $Vd32 = vmem($Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_ldnpnt0 : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32), "if (!$Pv4) $Vd32 = vmem($Rt32):nt", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { @@ -26062,20 +25796,8 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_ldnpnt0_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32), -"if (!$Pv4) $Vd32 = vmem($Rt32):nt", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_ldnt0 : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins IntRegs:$Rt32), "$Vd32 = vmem($Rt32):nt", PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> { @@ -26085,20 +25807,8 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_ldnt0_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins IntRegs:$Rt32), -"$Vd32 = vmem($Rt32):nt", -PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_ldp0 : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32), "if ($Pv4) $Vd32 = vmem($Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { @@ -26108,20 +25818,8 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_ldp0_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32), -"if ($Pv4) $Vd32 = vmem($Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_ldpnt0 : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32), "if ($Pv4) $Vd32 = vmem($Rt32):nt", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { @@ -26131,20 +25829,8 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_ldpnt0_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32), -"if ($Pv4) $Vd32 = vmem($Rt32):nt", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_ldtnp0 : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32), "if (!$Pv4) $Vd32.tmp = vmem($Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { @@ -26154,20 +25840,8 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_ldtnp0_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32), -"if (!$Pv4) $Vd32.tmp = vmem($Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_ldtnpnt0 : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32), "if (!$Pv4) $Vd32.tmp = vmem($Rt32):nt", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { @@ -26177,20 +25851,8 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_ldtnpnt0_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32), -"if (!$Pv4) $Vd32.tmp = vmem($Rt32):nt", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_ldtp0 : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32), "if ($Pv4) $Vd32.tmp = vmem($Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { @@ -26200,20 +25862,8 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_ldtp0_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32), -"if ($Pv4) $Vd32.tmp = vmem($Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_ldtpnt0 : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32), "if ($Pv4) $Vd32.tmp = vmem($Rt32):nt", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { @@ -26223,20 +25873,8 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_ldtpnt0_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32), -"if ($Pv4) $Vd32.tmp = vmem($Rt32):nt", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_ldu0 : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins IntRegs:$Rt32), "$Vd32 = vmemu($Rt32)", PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> { @@ -26246,21 +25884,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_ldu0_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins IntRegs:$Rt32), -"$Vd32 = vmemu($Rt32)", -PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_lo : HInst< -(outs VectorRegs:$Vd32), -(ins VecDblRegs:$Vss32), +(outs HvxVR:$Vd32), +(ins HvxWR:$Vss32), "$Vd32 = lo($Vss32)", CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -26268,19 +25894,8 @@ let opNewValue = 0; let isPseudo = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_lo_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VecDblRegs128B:$Vss32), -"$Vd32 = lo($Vss32)", -CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_lvsplatb : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins IntRegs:$Rt32), "$Vd32.b = vsplat($Rt32)", tc_6b78cf13, TypeCVI_VX>, Enc_a5ed8a, Requires<[HasV62T,UseHVX]> { @@ -26290,20 +25905,8 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_lvsplatb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins IntRegs:$Rt32), -"$Vd32.b = vsplat($Rt32)", -tc_6b78cf13, TypeCVI_VX>, Enc_a5ed8a, Requires<[HasV62T,UseHVX]> { -let Inst{13-5} = 0b000000010; -let Inst{31-21} = 0b00011001110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_lvsplath : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins IntRegs:$Rt32), "$Vd32.h = vsplat($Rt32)", tc_6b78cf13, TypeCVI_VX>, Enc_a5ed8a, Requires<[HasV62T,UseHVX]> { @@ -26313,20 +25916,8 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_lvsplath_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins IntRegs:$Rt32), -"$Vd32.h = vsplat($Rt32)", -tc_6b78cf13, TypeCVI_VX>, Enc_a5ed8a, Requires<[HasV62T,UseHVX]> { -let Inst{13-5} = 0b000000001; -let Inst{31-21} = 0b00011001110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_lvsplatw : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins IntRegs:$Rt32), "$Vd32 = vsplat($Rt32)", tc_6b78cf13, TypeCVI_VX_LATE>, Enc_a5ed8a, Requires<[HasV60T,UseHVX]> { @@ -26336,21 +25927,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_lvsplatw_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins IntRegs:$Rt32), -"$Vd32 = vsplat($Rt32)", -tc_6b78cf13, TypeCVI_VX_LATE>, Enc_a5ed8a, Requires<[HasV60T,UseHVX]> { -let Inst{13-5} = 0b000000001; -let Inst{31-21} = 0b00011001101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_pred_and : HInst< -(outs VecPredRegs:$Qd4), -(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4), +(outs HvxQR:$Qd4), +(ins HvxQR:$Qs4, HvxQR:$Qt4), "$Qd4 = and($Qs4,$Qt4)", tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000000; @@ -26361,23 +25940,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_pred_and_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4), -"$Qd4 = and($Qs4,$Qt4)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000000; -let Inst{13-10} = 0b0000; -let Inst{21-16} = 0b000011; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_pred_and_n : HInst< -(outs VecPredRegs:$Qd4), -(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4), +(outs HvxQR:$Qd4), +(ins HvxQR:$Qs4, HvxQR:$Qt4), "$Qd4 = and($Qs4,!$Qt4)", tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000101; @@ -26388,23 +25953,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_pred_and_n_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4), -"$Qd4 = and($Qs4,!$Qt4)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000101; -let Inst{13-10} = 0b0000; -let Inst{21-16} = 0b000011; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_pred_not : HInst< -(outs VecPredRegs:$Qd4), -(ins VecPredRegs:$Qs4), +(outs HvxQR:$Qd4), +(ins HvxQR:$Qs4), "$Qd4 = not($Qs4)", tc_71337255, TypeCVI_VA>, Enc_bfbf03, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000010; @@ -26414,22 +25965,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_pred_not_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VecPredRegs128B:$Qs4), -"$Qd4 = not($Qs4)", -tc_71337255, TypeCVI_VA>, Enc_bfbf03, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000010; -let Inst{13-10} = 0b0000; -let Inst{31-16} = 0b0001111000000011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_pred_or : HInst< -(outs VecPredRegs:$Qd4), -(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4), +(outs HvxQR:$Qd4), +(ins HvxQR:$Qs4, HvxQR:$Qt4), "$Qd4 = or($Qs4,$Qt4)", tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000001; @@ -26440,23 +25978,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_pred_or_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4), -"$Qd4 = or($Qs4,$Qt4)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000001; -let Inst{13-10} = 0b0000; -let Inst{21-16} = 0b000011; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_pred_or_n : HInst< -(outs VecPredRegs:$Qd4), -(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4), +(outs HvxQR:$Qd4), +(ins HvxQR:$Qs4, HvxQR:$Qt4), "$Qd4 = or($Qs4,!$Qt4)", tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000100; @@ -26467,22 +25991,8 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_pred_or_n_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4), -"$Qd4 = or($Qs4,!$Qt4)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000100; -let Inst{13-10} = 0b0000; -let Inst{21-16} = 0b000011; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_pred_scalar2 : HInst< -(outs VecPredRegs:$Qd4), +(outs HvxQR:$Qd4), (ins IntRegs:$Rt32), "$Qd4 = vsetq($Rt32)", tc_4105d6b5, TypeCVI_VP>, Enc_7222b7, Requires<[HasV60T,UseHVX]> { @@ -26492,20 +26002,8 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_pred_scalar2_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins IntRegs:$Rt32), -"$Qd4 = vsetq($Rt32)", -tc_4105d6b5, TypeCVI_VP>, Enc_7222b7, Requires<[HasV60T,UseHVX]> { -let Inst{13-2} = 0b000000010001; -let Inst{31-21} = 0b00011001101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_pred_scalar2v2 : HInst< -(outs VecPredRegs:$Qd4), +(outs HvxQR:$Qd4), (ins IntRegs:$Rt32), "$Qd4 = vsetq2($Rt32)", tc_4105d6b5, TypeCVI_VP>, Enc_7222b7, Requires<[HasV62T,UseHVX]> { @@ -26515,21 +26013,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_pred_scalar2v2_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins IntRegs:$Rt32), -"$Qd4 = vsetq2($Rt32)", -tc_4105d6b5, TypeCVI_VP>, Enc_7222b7, Requires<[HasV62T,UseHVX]> { -let Inst{13-2} = 0b000000010011; -let Inst{31-21} = 0b00011001101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_pred_xor : HInst< -(outs VecPredRegs:$Qd4), -(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4), +(outs HvxQR:$Qd4), +(ins HvxQR:$Qs4, HvxQR:$Qt4), "$Qd4 = xor($Qs4,$Qt4)", tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000011; @@ -26540,23 +26026,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_pred_xor_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4), -"$Qd4 = xor($Qs4,$Qt4)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000011; -let Inst{13-10} = 0b0000; -let Inst{21-16} = 0b000011; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_shuffeqh : HInst< -(outs VecPredRegs:$Qd4), -(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4), +(outs HvxQR:$Qd4), +(ins HvxQR:$Qs4, HvxQR:$Qt4), "$Qd4.b = vshuffe($Qs4.h,$Qt4.h)", tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV62T,UseHVX]> { let Inst{7-2} = 0b000110; @@ -26567,23 +26039,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_shuffeqh_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4), -"$Qd4.b = vshuffe($Qs4.h,$Qt4.h)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV62T,UseHVX]> { -let Inst{7-2} = 0b000110; -let Inst{13-10} = 0b0000; -let Inst{21-16} = 0b000011; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_shuffeqw : HInst< -(outs VecPredRegs:$Qd4), -(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4), +(outs HvxQR:$Qd4), +(ins HvxQR:$Qs4, HvxQR:$Qt4), "$Qd4.h = vshuffe($Qs4.w,$Qt4.w)", tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV62T,UseHVX]> { let Inst{7-2} = 0b000111; @@ -26594,42 +26052,18 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_shuffeqw_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4), -"$Qd4.h = vshuffe($Qs4.w,$Qt4.w)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV62T,UseHVX]> { -let Inst{7-2} = 0b000111; -let Inst{13-10} = 0b0000; -let Inst{21-16} = 0b000011; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_st0 : HInst< (outs), -(ins IntRegs:$Rt32, VectorRegs:$Vs32), +(ins IntRegs:$Rt32, HvxVR:$Vs32), "vmem($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_st0_128B : HInst< -(outs), -(ins IntRegs:$Rt32, VectorRegs128B:$Vs32), -"vmem($Rt32) = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_stn0 : HInst< (outs), -(ins IntRegs:$Rt32, VectorRegs:$Os8), +(ins IntRegs:$Rt32, HvxVR:$Os8), "vmem($Rt32) = $Os8.new", PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { let isPseudo = 1; @@ -26637,20 +26071,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let opNewValue = 1; } -def V6_stn0_128B : HInst< -(outs), -(ins IntRegs:$Rt32, VectorRegs128B:$Os8), -"vmem($Rt32) = $Os8.new", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 1; -} def V6_stnnt0 : HInst< (outs), -(ins IntRegs:$Rt32, VectorRegs:$Os8), +(ins IntRegs:$Rt32, HvxVR:$Os8), "vmem($Rt32):nt = $Os8.new", PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { let isPseudo = 1; @@ -26658,247 +26081,116 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let opNewValue = 1; } -def V6_stnnt0_128B : HInst< -(outs), -(ins IntRegs:$Rt32, VectorRegs128B:$Os8), -"vmem($Rt32):nt = $Os8.new", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 1; -} def V6_stnp0 : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), "if (!$Pv4) vmem($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_stnp0_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), -"if (!$Pv4) vmem($Rt32) = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_stnpnt0 : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), "if (!$Pv4) vmem($Rt32):nt = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_stnpnt0_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), -"if (!$Pv4) vmem($Rt32):nt = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_stnq0 : HInst< (outs), -(ins VecPredRegs:$Qv4, IntRegs:$Rt32, VectorRegs:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32), "if (!$Qv4) vmem($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_stnq0_128B : HInst< -(outs), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), -"if (!$Qv4) vmem($Rt32) = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_stnqnt0 : HInst< (outs), -(ins VecPredRegs:$Qv4, IntRegs:$Rt32, VectorRegs:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32), "if (!$Qv4) vmem($Rt32):nt = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_stnqnt0_128B : HInst< -(outs), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), -"if (!$Qv4) vmem($Rt32):nt = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_stnt0 : HInst< (outs), -(ins IntRegs:$Rt32, VectorRegs:$Vs32), +(ins IntRegs:$Rt32, HvxVR:$Vs32), "vmem($Rt32):nt = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_stnt0_128B : HInst< -(outs), -(ins IntRegs:$Rt32, VectorRegs128B:$Vs32), -"vmem($Rt32):nt = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_stp0 : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), "if ($Pv4) vmem($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_stp0_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), -"if ($Pv4) vmem($Rt32) = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_stpnt0 : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), "if ($Pv4) vmem($Rt32):nt = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_stpnt0_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), -"if ($Pv4) vmem($Rt32):nt = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_stq0 : HInst< (outs), -(ins VecPredRegs:$Qv4, IntRegs:$Rt32, VectorRegs:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32), "if ($Qv4) vmem($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_stq0_128B : HInst< -(outs), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), -"if ($Qv4) vmem($Rt32) = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_stqnt0 : HInst< (outs), -(ins VecPredRegs:$Qv4, IntRegs:$Rt32, VectorRegs:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32), "if ($Qv4) vmem($Rt32):nt = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_stqnt0_128B : HInst< -(outs), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), -"if ($Qv4) vmem($Rt32):nt = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_stu0 : HInst< (outs), -(ins IntRegs:$Rt32, VectorRegs:$Vs32), +(ins IntRegs:$Rt32, HvxVR:$Vs32), "vmemu($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_stu0_128B : HInst< -(outs), -(ins IntRegs:$Rt32, VectorRegs128B:$Vs32), -"vmemu($Rt32) = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_stunp0 : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), "if (!$Pv4) vmemu($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_stunp0_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), -"if (!$Pv4) vmemu($Rt32) = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_stup0 : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), "if ($Pv4) vmemu($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_stup0_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), -"if ($Pv4) vmemu($Rt32) = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32Ub_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins IntRegs:$Rt32, s4_0Imm:$Ii), "$Vd32 = vmemu($Rt32+#$Ii)", tc_35e92f8e, TypeCVI_VM_VP_LDU>, Enc_f3f408, Requires<[HasV60T,UseHVX]> { @@ -26908,30 +26200,13 @@ let Inst{31-21} = 0b00101000000; let hasNewValue = 1; let opNewValue = 0; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32Ub_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins IntRegs:$Rt32, s4_0Imm:$Ii), -"$Vd32 = vmemu($Rt32+#$Ii)", -tc_35e92f8e, TypeCVI_VM_VP_LDU>, Enc_f3f408, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{12-11} = 0b00; -let Inst{31-21} = 0b00101000000; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32Ub_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s3_0Imm:$Ii), "$Vd32 = vmemu($Rx32++#$Ii)", tc_4fd8566e, TypeCVI_VM_VP_LDU>, Enc_a255dc, Requires<[HasV60T,UseHVX]> { @@ -26941,32 +26216,14 @@ let Inst{31-21} = 0b00101001000; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32Ub_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii), -"$Vd32 = vmemu($Rx32++#$Ii)", -tc_4fd8566e, TypeCVI_VM_VP_LDU>, Enc_a255dc, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-11} = 0b000; -let Inst{31-21} = 0b00101001000; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32Ub_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Vd32 = vmemu($Rx32++$Mu2)", tc_4fd8566e, TypeCVI_VM_VP_LDU>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]> { @@ -26975,31 +26232,14 @@ let Inst{31-21} = 0b00101011000; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32Ub_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2), -"$Vd32 = vmemu($Rx32++$Mu2)", -tc_4fd8566e, TypeCVI_VM_VP_LDU>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]> { -let Inst{12-5} = 0b00000111; -let Inst{31-21} = 0b00101011000; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins IntRegs:$Rt32, s4_0Imm:$Ii), "$Vd32 = vmem($Rt32+#$Ii)", tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[HasV60T,UseHVX]> { @@ -27009,32 +26249,14 @@ let Inst{31-21} = 0b00101000000; let hasNewValue = 1; let opNewValue = 0; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isCVLoadable = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins IntRegs:$Rt32, s4_0Imm:$Ii), -"$Vd32 = vmem($Rt32+#$Ii)", -tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{12-11} = 0b00; -let Inst{31-21} = 0b00101000000; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let isCVLoadable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_cur_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins IntRegs:$Rt32, s4_0Imm:$Ii), "$Vd32.cur = vmem($Rt32+#$Ii)", tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[HasV60T,UseHVX]> { @@ -27044,32 +26266,14 @@ let Inst{31-21} = 0b00101000000; let hasNewValue = 1; let opNewValue = 0; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_cur_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins IntRegs:$Rt32, s4_0Imm:$Ii), -"$Vd32.cur = vmem($Rt32+#$Ii)", -tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{12-11} = 0b00; -let Inst{31-21} = 0b00101000000; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let CVINew = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_cur_npred_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii)", tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> { @@ -27080,33 +26284,14 @@ let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_cur_npred_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), -"if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii)", -tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{31-21} = 0b00101000100; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let CVINew = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_cur_npred_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii)", tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> { @@ -27118,36 +26303,15 @@ let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_cur_npred_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), -"if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii)", -tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001100; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let CVINew = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_cur_npred_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2)", tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> { @@ -27158,35 +26322,15 @@ let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_cur_npred_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), -"if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2)", -tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> { -let Inst{10-5} = 0b000101; -let Inst{31-21} = 0b00101011100; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let CVINew = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_cur_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s3_0Imm:$Ii), "$Vd32.cur = vmem($Rx32++#$Ii)", tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[HasV60T,UseHVX]> { @@ -27196,34 +26340,15 @@ let Inst{31-21} = 0b00101001000; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_cur_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii), -"$Vd32.cur = vmem($Rx32++#$Ii)", -tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-11} = 0b000; -let Inst{31-21} = 0b00101001000; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let CVINew = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_cur_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Vd32.cur = vmem($Rx32++$Mu2)", tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]> { @@ -27232,33 +26357,15 @@ let Inst{31-21} = 0b00101011000; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_cur_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2), -"$Vd32.cur = vmem($Rx32++$Mu2)", -tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]> { -let Inst{12-5} = 0b00000001; -let Inst{31-21} = 0b00101011000; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let CVINew = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_cur_pred_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii)", tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> { @@ -27268,32 +26375,14 @@ let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_cur_pred_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), -"if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii)", -tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{31-21} = 0b00101000100; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let CVINew = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_cur_pred_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii)", tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> { @@ -27304,35 +26393,15 @@ let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_cur_pred_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), -"if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii)", -tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001100; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let CVINew = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_cur_pred_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2)", tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> { @@ -27342,34 +26411,15 @@ let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_cur_pred_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), -"if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2)", -tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> { -let Inst{10-5} = 0b000100; -let Inst{31-21} = 0b00101011100; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let CVINew = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_npred_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii)", tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> { @@ -27380,31 +26430,13 @@ let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_npred_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), -"if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii)", -tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{31-21} = 0b00101000100; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_npred_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii)", tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> { @@ -27416,34 +26448,14 @@ let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_npred_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), -"if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii)", -tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001100; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_npred_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2)", tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> { @@ -27454,33 +26466,14 @@ let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_npred_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), -"if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2)", -tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> { -let Inst{10-5} = 0b000011; -let Inst{31-21} = 0b00101011100; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins IntRegs:$Rt32, s4_0Imm:$Ii), "$Vd32 = vmem($Rt32+#$Ii):nt", tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[HasV60T,UseHVX]> { @@ -27490,34 +26483,15 @@ let Inst{31-21} = 0b00101000010; let hasNewValue = 1; let opNewValue = 0; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; let isCVLoadable = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_nt_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins IntRegs:$Rt32, s4_0Imm:$Ii), -"$Vd32 = vmem($Rt32+#$Ii):nt", -tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{12-11} = 0b00; -let Inst{31-21} = 0b00101000010; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let isNonTemporal = 1; -let isCVLoadable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_nt_cur_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins IntRegs:$Rt32, s4_0Imm:$Ii), "$Vd32.cur = vmem($Rt32+#$Ii):nt", tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[HasV60T,UseHVX]> { @@ -27527,34 +26501,15 @@ let Inst{31-21} = 0b00101000010; let hasNewValue = 1; let opNewValue = 0; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; let isNonTemporal = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_nt_cur_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins IntRegs:$Rt32, s4_0Imm:$Ii), -"$Vd32.cur = vmem($Rt32+#$Ii):nt", -tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{12-11} = 0b00; -let Inst{31-21} = 0b00101000010; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let CVINew = 1; -let mayLoad = 1; -let isNonTemporal = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_nt_cur_npred_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt", tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> { @@ -27565,35 +26520,15 @@ let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; let isNonTemporal = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_nt_cur_npred_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), -"if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt", -tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{31-21} = 0b00101000110; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let CVINew = 1; -let mayLoad = 1; -let isNonTemporal = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_nt_cur_npred_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt", tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> { @@ -27605,7 +26540,7 @@ let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; @@ -27613,30 +26548,8 @@ let isNonTemporal = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_cur_npred_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), -"if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt", -tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001110; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let CVINew = 1; -let mayLoad = 1; -let isNonTemporal = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_cur_npred_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt", tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> { @@ -27647,7 +26560,7 @@ let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; @@ -27655,29 +26568,8 @@ let isNonTemporal = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_cur_npred_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), -"if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt", -tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> { -let Inst{10-5} = 0b000101; -let Inst{31-21} = 0b00101011110; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let CVINew = 1; -let mayLoad = 1; -let isNonTemporal = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_cur_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s3_0Imm:$Ii), "$Vd32.cur = vmem($Rx32++#$Ii):nt", tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[HasV60T,UseHVX]> { @@ -27687,7 +26579,7 @@ let Inst{31-21} = 0b00101001010; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; @@ -27695,28 +26587,8 @@ let isNonTemporal = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_cur_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii), -"$Vd32.cur = vmem($Rx32++#$Ii):nt", -tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-11} = 0b000; -let Inst{31-21} = 0b00101001010; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let CVINew = 1; -let mayLoad = 1; -let isNonTemporal = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_cur_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Vd32.cur = vmem($Rx32++$Mu2):nt", tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]> { @@ -27725,7 +26597,7 @@ let Inst{31-21} = 0b00101011010; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; @@ -27733,27 +26605,8 @@ let isNonTemporal = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_cur_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2), -"$Vd32.cur = vmem($Rx32++$Mu2):nt", -tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]> { -let Inst{12-5} = 0b00000001; -let Inst{31-21} = 0b00101011010; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let CVINew = 1; -let mayLoad = 1; -let isNonTemporal = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_cur_pred_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt", tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> { @@ -27763,34 +26616,15 @@ let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; let isNonTemporal = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_nt_cur_pred_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), -"if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt", -tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{31-21} = 0b00101000110; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let CVINew = 1; -let mayLoad = 1; -let isNonTemporal = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_nt_cur_pred_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt", tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> { @@ -27801,7 +26635,7 @@ let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; @@ -27809,29 +26643,8 @@ let isNonTemporal = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_cur_pred_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), -"if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt", -tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001110; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let CVINew = 1; -let mayLoad = 1; -let isNonTemporal = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_cur_pred_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt", tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> { @@ -27841,7 +26654,7 @@ let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; @@ -27849,28 +26662,8 @@ let isNonTemporal = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_cur_pred_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), -"if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt", -tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> { -let Inst{10-5} = 0b000100; -let Inst{31-21} = 0b00101011110; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let CVINew = 1; -let mayLoad = 1; -let isNonTemporal = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_npred_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii):nt", tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> { @@ -27881,33 +26674,14 @@ let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_nt_npred_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), -"if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii):nt", -tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{31-21} = 0b00101000110; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let isNonTemporal = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_nt_npred_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii):nt", tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> { @@ -27919,36 +26693,15 @@ let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_npred_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), -"if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii):nt", -tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001110; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let isNonTemporal = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_npred_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2):nt", tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> { @@ -27959,35 +26712,15 @@ let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_npred_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), -"if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2):nt", -tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> { -let Inst{10-5} = 0b000011; -let Inst{31-21} = 0b00101011110; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let isNonTemporal = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s3_0Imm:$Ii), "$Vd32 = vmem($Rx32++#$Ii):nt", tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[HasV60T,UseHVX]> { @@ -27997,7 +26730,7 @@ let Inst{31-21} = 0b00101001010; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; @@ -28005,28 +26738,8 @@ let isCVLoadable = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii), -"$Vd32 = vmem($Rx32++#$Ii):nt", -tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-11} = 0b000; -let Inst{31-21} = 0b00101001010; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let isNonTemporal = 1; -let isCVLoadable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Vd32 = vmem($Rx32++$Mu2):nt", tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]> { @@ -28035,7 +26748,7 @@ let Inst{31-21} = 0b00101011010; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; @@ -28043,27 +26756,8 @@ let isCVLoadable = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2), -"$Vd32 = vmem($Rx32++$Mu2):nt", -tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]> { -let Inst{12-5} = 0b00000000; -let Inst{31-21} = 0b00101011010; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let isNonTemporal = 1; -let isCVLoadable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_pred_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if ($Pv4) $Vd32 = vmem($Rt32+#$Ii):nt", tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> { @@ -28073,32 +26767,14 @@ let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_nt_pred_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), -"if ($Pv4) $Vd32 = vmem($Rt32+#$Ii):nt", -tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{31-21} = 0b00101000110; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let isNonTemporal = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_nt_pred_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if ($Pv4) $Vd32 = vmem($Rx32++#$Ii):nt", tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> { @@ -28109,35 +26785,15 @@ let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_pred_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), -"if ($Pv4) $Vd32 = vmem($Rx32++#$Ii):nt", -tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001110; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let isNonTemporal = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_pred_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if ($Pv4) $Vd32 = vmem($Rx32++$Mu2):nt", tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> { @@ -28147,34 +26803,15 @@ let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_pred_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), -"if ($Pv4) $Vd32 = vmem($Rx32++$Mu2):nt", -tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> { -let Inst{10-5} = 0b000010; -let Inst{31-21} = 0b00101011110; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let isNonTemporal = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_tmp_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins IntRegs:$Rt32, s4_0Imm:$Ii), "$Vd32.tmp = vmem($Rt32+#$Ii):nt", tc_77a4c701, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[HasV60T,UseHVX]> { @@ -28184,32 +26821,14 @@ let Inst{31-21} = 0b00101000010; let hasNewValue = 1; let opNewValue = 0; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_nt_tmp_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins IntRegs:$Rt32, s4_0Imm:$Ii), -"$Vd32.tmp = vmem($Rt32+#$Ii):nt", -tc_77a4c701, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{12-11} = 0b00; -let Inst{31-21} = 0b00101000010; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let isNonTemporal = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_nt_tmp_npred_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt", tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> { @@ -28220,33 +26839,14 @@ let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_nt_tmp_npred_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), -"if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt", -tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{31-21} = 0b00101000110; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let isNonTemporal = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_nt_tmp_npred_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt", tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> { @@ -28258,36 +26858,15 @@ let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_tmp_npred_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), -"if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt", -tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001110; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let isNonTemporal = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_tmp_npred_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt", tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> { @@ -28298,35 +26877,15 @@ let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_tmp_npred_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), -"if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt", -tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> { -let Inst{10-5} = 0b000111; -let Inst{31-21} = 0b00101011110; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let isNonTemporal = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_tmp_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s3_0Imm:$Ii), "$Vd32.tmp = vmem($Rx32++#$Ii):nt", tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[HasV60T,UseHVX]> { @@ -28336,34 +26895,15 @@ let Inst{31-21} = 0b00101001010; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_tmp_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii), -"$Vd32.tmp = vmem($Rx32++#$Ii):nt", -tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-11} = 0b000; -let Inst{31-21} = 0b00101001010; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let isNonTemporal = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_tmp_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Vd32.tmp = vmem($Rx32++$Mu2):nt", tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]> { @@ -28372,33 +26912,15 @@ let Inst{31-21} = 0b00101011010; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_tmp_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2), -"$Vd32.tmp = vmem($Rx32++$Mu2):nt", -tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]> { -let Inst{12-5} = 0b00000010; -let Inst{31-21} = 0b00101011010; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let isNonTemporal = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_tmp_pred_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt", tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> { @@ -28408,32 +26930,14 @@ let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_nt_tmp_pred_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), -"if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt", -tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{31-21} = 0b00101000110; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let isNonTemporal = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_nt_tmp_pred_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt", tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> { @@ -28444,35 +26948,15 @@ let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_tmp_pred_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), -"if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt", -tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001110; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let isNonTemporal = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_tmp_pred_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt", tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> { @@ -28482,34 +26966,15 @@ let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_tmp_pred_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), -"if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt", -tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> { -let Inst{10-5} = 0b000110; -let Inst{31-21} = 0b00101011110; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let isNonTemporal = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s3_0Imm:$Ii), "$Vd32 = vmem($Rx32++#$Ii)", tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[HasV60T,UseHVX]> { @@ -28519,34 +26984,15 @@ let Inst{31-21} = 0b00101001000; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isCVLoadable = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii), -"$Vd32 = vmem($Rx32++#$Ii)", -tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-11} = 0b000; -let Inst{31-21} = 0b00101001000; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let isCVLoadable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Vd32 = vmem($Rx32++$Mu2)", tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]> { @@ -28555,33 +27001,15 @@ let Inst{31-21} = 0b00101011000; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isCVLoadable = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2), -"$Vd32 = vmem($Rx32++$Mu2)", -tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]> { -let Inst{12-5} = 0b00000000; -let Inst{31-21} = 0b00101011000; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let isCVLoadable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_pred_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if ($Pv4) $Vd32 = vmem($Rt32+#$Ii)", tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> { @@ -28591,30 +27019,13 @@ let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_pred_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), -"if ($Pv4) $Vd32 = vmem($Rt32+#$Ii)", -tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{31-21} = 0b00101000100; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_pred_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if ($Pv4) $Vd32 = vmem($Rx32++#$Ii)", tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> { @@ -28625,33 +27036,14 @@ let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_pred_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), -"if ($Pv4) $Vd32 = vmem($Rx32++#$Ii)", -tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001100; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_pred_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if ($Pv4) $Vd32 = vmem($Rx32++$Mu2)", tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> { @@ -28661,32 +27053,14 @@ let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_pred_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), -"if ($Pv4) $Vd32 = vmem($Rx32++$Mu2)", -tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> { -let Inst{10-5} = 0b000010; -let Inst{31-21} = 0b00101011100; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_tmp_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins IntRegs:$Rt32, s4_0Imm:$Ii), "$Vd32.tmp = vmem($Rt32+#$Ii)", tc_77a4c701, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[HasV60T,UseHVX]> { @@ -28696,30 +27070,13 @@ let Inst{31-21} = 0b00101000000; let hasNewValue = 1; let opNewValue = 0; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_tmp_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins IntRegs:$Rt32, s4_0Imm:$Ii), -"$Vd32.tmp = vmem($Rt32+#$Ii)", -tc_77a4c701, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{12-11} = 0b00; -let Inst{31-21} = 0b00101000000; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_tmp_npred_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)", tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> { @@ -28730,31 +27087,13 @@ let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_tmp_npred_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), -"if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)", -tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{31-21} = 0b00101000100; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_tmp_npred_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)", tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> { @@ -28766,34 +27105,14 @@ let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_tmp_npred_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), -"if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)", -tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001100; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_tmp_npred_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)", tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> { @@ -28804,33 +27123,14 @@ let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_tmp_npred_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), -"if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)", -tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> { -let Inst{10-5} = 0b000111; -let Inst{31-21} = 0b00101011100; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_tmp_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s3_0Imm:$Ii), "$Vd32.tmp = vmem($Rx32++#$Ii)", tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[HasV60T,UseHVX]> { @@ -28840,32 +27140,14 @@ let Inst{31-21} = 0b00101001000; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_tmp_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii), -"$Vd32.tmp = vmem($Rx32++#$Ii)", -tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-11} = 0b000; -let Inst{31-21} = 0b00101001000; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_tmp_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Vd32.tmp = vmem($Rx32++$Mu2)", tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]> { @@ -28874,31 +27156,14 @@ let Inst{31-21} = 0b00101011000; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_tmp_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2), -"$Vd32.tmp = vmem($Rx32++$Mu2)", -tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]> { -let Inst{12-5} = 0b00000010; -let Inst{31-21} = 0b00101011000; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_tmp_pred_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)", tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> { @@ -28908,30 +27173,13 @@ let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_tmp_pred_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), -"if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)", -tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{31-21} = 0b00101000100; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_tmp_pred_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)", tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> { @@ -28942,33 +27190,14 @@ let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_tmp_pred_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), -"if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)", -tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001100; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_tmp_pred_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)", tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> { @@ -28978,64 +27207,30 @@ let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_tmp_pred_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), -"if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)", -tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]> { -let Inst{10-5} = 0b000110; -let Inst{31-21} = 0b00101011100; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32Ub_ai : HInst< (outs), -(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "vmemu($Rt32+#$Ii) = $Vs32", tc_354299ad, TypeCVI_VM_STU>, Enc_c9e3bc, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b111; let Inst{12-11} = 0b00; let Inst{31-21} = 0b00101000001; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let mayStore = 1; let BaseOpcode = "V6_vS32Ub_ai"; let isPredicable = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vS32Ub_ai_128B : HInst< -(outs), -(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), -"vmemu($Rt32+#$Ii) = $Vs32", -tc_354299ad, TypeCVI_VM_STU>, Enc_c9e3bc, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b111; -let Inst{12-11} = 0b00; -let Inst{31-21} = 0b00101000001; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32Ub_ai_128B"; -let isPredicable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vS32Ub_npred_ai : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "if (!$Pv4) vmemu($Rt32+#$Ii) = $Vs32", tc_d642eff3, TypeCVI_VM_STU>, Enc_27b757, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b111; @@ -29043,30 +27238,14 @@ let Inst{31-21} = 0b00101000101; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let mayStore = 1; let BaseOpcode = "V6_vS32Ub_ai"; let DecoderNamespace = "EXT_mmvec"; } -def V6_vS32Ub_npred_ai_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), -"if (!$Pv4) vmemu($Rt32+#$Ii) = $Vs32", -tc_d642eff3, TypeCVI_VM_STU>, Enc_27b757, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b111; -let Inst{31-21} = 0b00101000101; -let isPredicated = 1; -let isPredicatedFalse = 1; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32Ub_ai_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vS32Ub_npred_pi : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "if (!$Pv4) vmemu($Rx32++#$Ii) = $Vs32", tc_6fd9ad30, TypeCVI_VM_STU>, Enc_865390, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b111; @@ -29075,33 +27254,15 @@ let Inst{31-21} = 0b00101001101; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let mayStore = 1; let BaseOpcode = "V6_vS32Ub_pi"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32Ub_npred_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), -"if (!$Pv4) vmemu($Rx32++#$Ii) = $Vs32", -tc_6fd9ad30, TypeCVI_VM_STU>, Enc_865390, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001101; -let isPredicated = 1; -let isPredicatedFalse = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32Ub_pi_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32Ub_npred_ppu : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "if (!$Pv4) vmemu($Rx32++$Mu2) = $Vs32", tc_6fd9ad30, TypeCVI_VM_STU>, Enc_1ef990, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{10-5} = 0b000111; @@ -29109,125 +27270,60 @@ let Inst{31-21} = 0b00101011101; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let mayStore = 1; let BaseOpcode = "V6_vS32Ub_ppu"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32Ub_npred_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), -"if (!$Pv4) vmemu($Rx32++$Mu2) = $Vs32", -tc_6fd9ad30, TypeCVI_VM_STU>, Enc_1ef990, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{10-5} = 0b000111; -let Inst{31-21} = 0b00101011101; -let isPredicated = 1; -let isPredicatedFalse = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32Ub_ppu_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32Ub_pi : HInst< (outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "vmemu($Rx32++#$Ii) = $Vs32", tc_7fa82b08, TypeCVI_VM_STU>, Enc_b62ef7, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b111; let Inst{13-11} = 0b000; let Inst{31-21} = 0b00101001001; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let mayStore = 1; let BaseOpcode = "V6_vS32Ub_pi"; let isPredicable = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32Ub_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), -"vmemu($Rx32++#$Ii) = $Vs32", -tc_7fa82b08, TypeCVI_VM_STU>, Enc_b62ef7, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b111; -let Inst{13-11} = 0b000; -let Inst{31-21} = 0b00101001001; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32Ub_pi_128B"; -let isPredicable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32Ub_ppu : HInst< (outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "vmemu($Rx32++$Mu2) = $Vs32", tc_7fa82b08, TypeCVI_VM_STU>, Enc_d15d19, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{12-5} = 0b00000111; let Inst{31-21} = 0b00101011001; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let mayStore = 1; let BaseOpcode = "V6_vS32Ub_ppu"; let isPredicable = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32Ub_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), -"vmemu($Rx32++$Mu2) = $Vs32", -tc_7fa82b08, TypeCVI_VM_STU>, Enc_d15d19, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{12-5} = 0b00000111; -let Inst{31-21} = 0b00101011001; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32Ub_ppu_128B"; -let isPredicable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32Ub_pred_ai : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "if ($Pv4) vmemu($Rt32+#$Ii) = $Vs32", tc_d642eff3, TypeCVI_VM_STU>, Enc_27b757, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b110; let Inst{31-21} = 0b00101000101; let isPredicated = 1; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let mayStore = 1; let BaseOpcode = "V6_vS32Ub_ai"; let DecoderNamespace = "EXT_mmvec"; } -def V6_vS32Ub_pred_ai_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), -"if ($Pv4) vmemu($Rt32+#$Ii) = $Vs32", -tc_d642eff3, TypeCVI_VM_STU>, Enc_27b757, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b110; -let Inst{31-21} = 0b00101000101; -let isPredicated = 1; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32Ub_ai_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vS32Ub_pred_pi : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "if ($Pv4) vmemu($Rx32++#$Ii) = $Vs32", tc_6fd9ad30, TypeCVI_VM_STU>, Enc_865390, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b110; @@ -29235,103 +27331,53 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001101; let isPredicated = 1; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let mayStore = 1; let BaseOpcode = "V6_vS32Ub_pi"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32Ub_pred_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), -"if ($Pv4) vmemu($Rx32++#$Ii) = $Vs32", -tc_6fd9ad30, TypeCVI_VM_STU>, Enc_865390, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001101; -let isPredicated = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32Ub_pi_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32Ub_pred_ppu : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "if ($Pv4) vmemu($Rx32++$Mu2) = $Vs32", tc_6fd9ad30, TypeCVI_VM_STU>, Enc_1ef990, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{10-5} = 0b000110; let Inst{31-21} = 0b00101011101; let isPredicated = 1; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let mayStore = 1; let BaseOpcode = "V6_vS32Ub_ppu"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32Ub_pred_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), -"if ($Pv4) vmemu($Rx32++$Mu2) = $Vs32", -tc_6fd9ad30, TypeCVI_VM_STU>, Enc_1ef990, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{10-5} = 0b000110; -let Inst{31-21} = 0b00101011101; -let isPredicated = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32Ub_ppu_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_ai : HInst< (outs), -(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "vmem($Rt32+#$Ii) = $Vs32", tc_e3748cdf, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b000; let Inst{12-11} = 0b00; let Inst{31-21} = 0b00101000001; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let mayStore = 1; let BaseOpcode = "V6_vS32b_ai"; let isNVStorable = 1; let isPredicable = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vS32b_ai_128B : HInst< -(outs), -(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), -"vmem($Rt32+#$Ii) = $Vs32", -tc_e3748cdf, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b000; -let Inst{12-11} = 0b00; -let Inst{31-21} = 0b00101000001; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_ai_128B"; -let isNVStorable = 1; -let isPredicable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vS32b_new_ai : HInst< (outs), -(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Os8), +(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8), "vmem($Rt32+#$Ii) = $Os8.new", tc_1b93bdc6, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-3} = 0b00100; let Inst{12-11} = 0b00; let Inst{31-21} = 0b00101000001; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNVStore = 1; let CVINew = 1; let isNewValue = 1; @@ -29341,29 +27387,9 @@ let isPredicable = 1; let DecoderNamespace = "EXT_mmvec"; let opNewValue = 2; } -def V6_vS32b_new_ai_128B : HInst< -(outs), -(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Os8), -"vmem($Rt32+#$Ii) = $Os8.new", -tc_1b93bdc6, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-3} = 0b00100; -let Inst{12-11} = 0b00; -let Inst{31-21} = 0b00101000001; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isNVStore = 1; -let CVINew = 1; -let isNewValue = 1; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_ai_128B"; -let isPredicable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 2; -} def V6_vS32b_new_npred_ai : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Os8), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8), "if (!$Pv4) vmem($Rt32+#$Ii) = $Os8.new", tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-3} = 0b01101; @@ -29371,7 +27397,7 @@ let Inst{31-21} = 0b00101000101; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNVStore = 1; let CVINew = 1; let isNewValue = 1; @@ -29380,29 +27406,9 @@ let BaseOpcode = "V6_vS32b_ai"; let DecoderNamespace = "EXT_mmvec"; let opNewValue = 3; } -def V6_vS32b_new_npred_ai_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Os8), -"if (!$Pv4) vmem($Rt32+#$Ii) = $Os8.new", -tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-3} = 0b01101; -let Inst{31-21} = 0b00101000101; -let isPredicated = 1; -let isPredicatedFalse = 1; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isNVStore = 1; -let CVINew = 1; -let isNewValue = 1; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_ai_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 3; -} def V6_vS32b_new_npred_pi : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Os8), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8), "if (!$Pv4) vmem($Rx32++#$Ii) = $Os8.new", tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-3} = 0b01101; @@ -29411,7 +27417,7 @@ let Inst{31-21} = 0b00101001101; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNVStore = 1; let CVINew = 1; let isNewValue = 1; @@ -29421,31 +27427,9 @@ let DecoderNamespace = "EXT_mmvec"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_new_npred_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Os8), -"if (!$Pv4) vmem($Rx32++#$Ii) = $Os8.new", -tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-3} = 0b01101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001101; -let isPredicated = 1; -let isPredicatedFalse = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNVStore = 1; -let CVINew = 1; -let isNewValue = 1; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_pi_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 4; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_new_npred_ppu : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Os8), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8), "if (!$Pv4) vmem($Rx32++$Mu2) = $Os8.new", tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{10-3} = 0b00001101; @@ -29453,7 +27437,7 @@ let Inst{31-21} = 0b00101011101; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNVStore = 1; let CVINew = 1; let isNewValue = 1; @@ -29463,37 +27447,16 @@ let DecoderNamespace = "EXT_mmvec"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_new_npred_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Os8), -"if (!$Pv4) vmem($Rx32++$Mu2) = $Os8.new", -tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{10-3} = 0b00001101; -let Inst{31-21} = 0b00101011101; -let isPredicated = 1; -let isPredicatedFalse = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNVStore = 1; -let CVINew = 1; -let isNewValue = 1; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_ppu_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 4; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_new_pi : HInst< (outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Os8), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8), "vmem($Rx32++#$Ii) = $Os8.new", tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-3} = 0b00100; let Inst{13-11} = 0b000; let Inst{31-21} = 0b00101001001; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNVStore = 1; let CVINew = 1; let isNewValue = 1; @@ -29504,36 +27467,15 @@ let DecoderNamespace = "EXT_mmvec"; let opNewValue = 3; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_new_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Os8), -"vmem($Rx32++#$Ii) = $Os8.new", -tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-3} = 0b00100; -let Inst{13-11} = 0b000; -let Inst{31-21} = 0b00101001001; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNVStore = 1; -let CVINew = 1; -let isNewValue = 1; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_pi_128B"; -let isPredicable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 3; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_new_ppu : HInst< (outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Os8), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8), "vmem($Rx32++$Mu2) = $Os8.new", tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{12-3} = 0b0000000100; let Inst{31-21} = 0b00101011001; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNVStore = 1; let CVINew = 1; let isNewValue = 1; @@ -29544,36 +27486,16 @@ let DecoderNamespace = "EXT_mmvec"; let opNewValue = 3; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_new_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Os8), -"vmem($Rx32++$Mu2) = $Os8.new", -tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{12-3} = 0b0000000100; -let Inst{31-21} = 0b00101011001; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNVStore = 1; -let CVINew = 1; -let isNewValue = 1; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_ppu_128B"; -let isPredicable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 3; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_new_pred_ai : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Os8), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8), "if ($Pv4) vmem($Rt32+#$Ii) = $Os8.new", tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-3} = 0b01000; let Inst{31-21} = 0b00101000101; let isPredicated = 1; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNVStore = 1; let CVINew = 1; let isNewValue = 1; @@ -29582,28 +27504,9 @@ let BaseOpcode = "V6_vS32b_ai"; let DecoderNamespace = "EXT_mmvec"; let opNewValue = 3; } -def V6_vS32b_new_pred_ai_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Os8), -"if ($Pv4) vmem($Rt32+#$Ii) = $Os8.new", -tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-3} = 0b01000; -let Inst{31-21} = 0b00101000101; -let isPredicated = 1; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isNVStore = 1; -let CVINew = 1; -let isNewValue = 1; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_ai_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 3; -} def V6_vS32b_new_pred_pi : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Os8), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8), "if ($Pv4) vmem($Rx32++#$Ii) = $Os8.new", tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-3} = 0b01000; @@ -29611,7 +27514,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001101; let isPredicated = 1; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNVStore = 1; let CVINew = 1; let isNewValue = 1; @@ -29621,37 +27524,16 @@ let DecoderNamespace = "EXT_mmvec"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_new_pred_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Os8), -"if ($Pv4) vmem($Rx32++#$Ii) = $Os8.new", -tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-3} = 0b01000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001101; -let isPredicated = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNVStore = 1; -let CVINew = 1; -let isNewValue = 1; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_pi_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 4; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_new_pred_ppu : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Os8), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8), "if ($Pv4) vmem($Rx32++$Mu2) = $Os8.new", tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{10-3} = 0b00001000; let Inst{31-21} = 0b00101011101; let isPredicated = 1; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNVStore = 1; let CVINew = 1; let isNewValue = 1; @@ -29661,29 +27543,9 @@ let DecoderNamespace = "EXT_mmvec"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_new_pred_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Os8), -"if ($Pv4) vmem($Rx32++$Mu2) = $Os8.new", -tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{10-3} = 0b00001000; -let Inst{31-21} = 0b00101011101; -let isPredicated = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNVStore = 1; -let CVINew = 1; -let isNewValue = 1; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_ppu_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 4; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_npred_ai : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "if (!$Pv4) vmem($Rt32+#$Ii) = $Vs32", tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b001; @@ -29691,32 +27553,15 @@ let Inst{31-21} = 0b00101000101; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let mayStore = 1; let BaseOpcode = "V6_vS32b_ai"; let isNVStorable = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vS32b_npred_ai_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), -"if (!$Pv4) vmem($Rt32+#$Ii) = $Vs32", -tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b001; -let Inst{31-21} = 0b00101000101; -let isPredicated = 1; -let isPredicatedFalse = 1; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_ai_128B"; -let isNVStorable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vS32b_npred_pi : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "if (!$Pv4) vmem($Rx32++#$Ii) = $Vs32", tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b001; @@ -29725,35 +27570,16 @@ let Inst{31-21} = 0b00101001101; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let mayStore = 1; let BaseOpcode = "V6_vS32b_pi"; let isNVStorable = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_npred_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), -"if (!$Pv4) vmem($Rx32++#$Ii) = $Vs32", -tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001101; -let isPredicated = 1; -let isPredicatedFalse = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_pi_128B"; -let isNVStorable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_npred_ppu : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "if (!$Pv4) vmem($Rx32++$Mu2) = $Vs32", tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{10-5} = 0b000001; @@ -29761,122 +27587,62 @@ let Inst{31-21} = 0b00101011101; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let mayStore = 1; let BaseOpcode = "V6_vS32b_ppu"; let isNVStorable = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_npred_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), -"if (!$Pv4) vmem($Rx32++$Mu2) = $Vs32", -tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{10-5} = 0b000001; -let Inst{31-21} = 0b00101011101; -let isPredicated = 1; -let isPredicatedFalse = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_ppu_128B"; -let isNVStorable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nqpred_ai : HInst< (outs), -(ins VecPredRegs:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "if (!$Qv4) vmem($Rt32+#$Ii) = $Vs32", tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; let Inst{31-21} = 0b00101000100; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vS32b_nqpred_ai_128B : HInst< -(outs), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), -"if (!$Qv4) vmem($Rt32+#$Ii) = $Vs32", -tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{31-21} = 0b00101000100; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let mayStore = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vS32b_nqpred_pi : HInst< (outs IntRegs:$Rx32), -(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "if (!$Qv4) vmem($Rx32++#$Ii) = $Vs32", tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001100; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nqpred_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), -"if (!$Qv4) vmem($Rx32++#$Ii) = $Vs32", -tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001100; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nqpred_ppu : HInst< (outs IntRegs:$Rx32), -(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "if (!$Qv4) vmem($Rx32++$Mu2) = $Vs32", tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[HasV60T,UseHVX]> { let Inst{10-5} = 0b000001; let Inst{31-21} = 0b00101011100; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nqpred_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), -"if (!$Qv4) vmem($Rx32++$Mu2) = $Vs32", -tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[HasV60T,UseHVX]> { -let Inst{10-5} = 0b000001; -let Inst{31-21} = 0b00101011100; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nt_ai : HInst< (outs), -(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "vmem($Rt32+#$Ii):nt = $Vs32", tc_e3748cdf, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b000; let Inst{12-11} = 0b00; let Inst{31-21} = 0b00101000011; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNonTemporal = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_ai"; @@ -29884,34 +27650,16 @@ let isNVStorable = 1; let isPredicable = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vS32b_nt_ai_128B : HInst< -(outs), -(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), -"vmem($Rt32+#$Ii):nt = $Vs32", -tc_e3748cdf, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b000; -let Inst{12-11} = 0b00; -let Inst{31-21} = 0b00101000011; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isNonTemporal = 1; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_ai_128B"; -let isNVStorable = 1; -let isPredicable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vS32b_nt_new_ai : HInst< (outs), -(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Os8), +(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8), "vmem($Rt32+#$Ii):nt = $Os8.new", tc_1b93bdc6, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-3} = 0b00100; let Inst{12-11} = 0b00; let Inst{31-21} = 0b00101000011; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNVStore = 1; let CVINew = 1; let isNewValue = 1; @@ -29922,30 +27670,9 @@ let isPredicable = 1; let DecoderNamespace = "EXT_mmvec"; let opNewValue = 2; } -def V6_vS32b_nt_new_ai_128B : HInst< -(outs), -(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Os8), -"vmem($Rt32+#$Ii):nt = $Os8.new", -tc_1b93bdc6, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-3} = 0b00100; -let Inst{12-11} = 0b00; -let Inst{31-21} = 0b00101000011; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isNVStore = 1; -let CVINew = 1; -let isNewValue = 1; -let isNonTemporal = 1; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_ai_128B"; -let isPredicable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 2; -} def V6_vS32b_nt_new_npred_ai : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Os8), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8), "if (!$Pv4) vmem($Rt32+#$Ii):nt = $Os8.new", tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-3} = 0b01111; @@ -29953,7 +27680,7 @@ let Inst{31-21} = 0b00101000111; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNVStore = 1; let CVINew = 1; let isNewValue = 1; @@ -29963,30 +27690,9 @@ let BaseOpcode = "V6_vS32b_ai"; let DecoderNamespace = "EXT_mmvec"; let opNewValue = 3; } -def V6_vS32b_nt_new_npred_ai_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Os8), -"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Os8.new", -tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-3} = 0b01111; -let Inst{31-21} = 0b00101000111; -let isPredicated = 1; -let isPredicatedFalse = 1; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isNVStore = 1; -let CVINew = 1; -let isNewValue = 1; -let isNonTemporal = 1; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_ai_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 3; -} def V6_vS32b_nt_new_npred_pi : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Os8), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8), "if (!$Pv4) vmem($Rx32++#$Ii):nt = $Os8.new", tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-3} = 0b01111; @@ -29995,7 +27701,7 @@ let Inst{31-21} = 0b00101001111; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNVStore = 1; let CVINew = 1; let isNewValue = 1; @@ -30006,32 +27712,9 @@ let DecoderNamespace = "EXT_mmvec"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_new_npred_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Os8), -"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Os8.new", -tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-3} = 0b01111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001111; -let isPredicated = 1; -let isPredicatedFalse = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNVStore = 1; -let CVINew = 1; -let isNewValue = 1; -let isNonTemporal = 1; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_pi_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 4; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nt_new_npred_ppu : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Os8), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8), "if (!$Pv4) vmem($Rx32++$Mu2):nt = $Os8.new", tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{10-3} = 0b00001111; @@ -30039,7 +27722,7 @@ let Inst{31-21} = 0b00101011111; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNVStore = 1; let CVINew = 1; let isNewValue = 1; @@ -30050,38 +27733,16 @@ let DecoderNamespace = "EXT_mmvec"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_new_npred_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Os8), -"if (!$Pv4) vmem($Rx32++$Mu2):nt = $Os8.new", -tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{10-3} = 0b00001111; -let Inst{31-21} = 0b00101011111; -let isPredicated = 1; -let isPredicatedFalse = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNVStore = 1; -let CVINew = 1; -let isNewValue = 1; -let isNonTemporal = 1; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_ppu_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 4; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nt_new_pi : HInst< (outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Os8), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8), "vmem($Rx32++#$Ii):nt = $Os8.new", tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-3} = 0b00100; let Inst{13-11} = 0b000; let Inst{31-21} = 0b00101001011; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNVStore = 1; let CVINew = 1; let isNewValue = 1; @@ -30093,37 +27754,15 @@ let DecoderNamespace = "EXT_mmvec"; let opNewValue = 3; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_new_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Os8), -"vmem($Rx32++#$Ii):nt = $Os8.new", -tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-3} = 0b00100; -let Inst{13-11} = 0b000; -let Inst{31-21} = 0b00101001011; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNVStore = 1; -let CVINew = 1; -let isNewValue = 1; -let isNonTemporal = 1; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_pi_128B"; -let isPredicable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 3; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nt_new_ppu : HInst< (outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Os8), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8), "vmem($Rx32++$Mu2):nt = $Os8.new", tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{12-3} = 0b0000000100; let Inst{31-21} = 0b00101011011; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNVStore = 1; let CVINew = 1; let isNewValue = 1; @@ -30135,37 +27774,16 @@ let DecoderNamespace = "EXT_mmvec"; let opNewValue = 3; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_new_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Os8), -"vmem($Rx32++$Mu2):nt = $Os8.new", -tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{12-3} = 0b0000000100; -let Inst{31-21} = 0b00101011011; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNVStore = 1; -let CVINew = 1; -let isNewValue = 1; -let isNonTemporal = 1; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_ppu_128B"; -let isPredicable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 3; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nt_new_pred_ai : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Os8), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8), "if ($Pv4) vmem($Rt32+#$Ii):nt = $Os8.new", tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-3} = 0b01010; let Inst{31-21} = 0b00101000111; let isPredicated = 1; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNVStore = 1; let CVINew = 1; let isNewValue = 1; @@ -30175,29 +27793,9 @@ let BaseOpcode = "V6_vS32b_ai"; let DecoderNamespace = "EXT_mmvec"; let opNewValue = 3; } -def V6_vS32b_nt_new_pred_ai_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Os8), -"if ($Pv4) vmem($Rt32+#$Ii):nt = $Os8.new", -tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-3} = 0b01010; -let Inst{31-21} = 0b00101000111; -let isPredicated = 1; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isNVStore = 1; -let CVINew = 1; -let isNewValue = 1; -let isNonTemporal = 1; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_ai_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 3; -} def V6_vS32b_nt_new_pred_pi : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Os8), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8), "if ($Pv4) vmem($Rx32++#$Ii):nt = $Os8.new", tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-3} = 0b01010; @@ -30205,7 +27803,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001111; let isPredicated = 1; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNVStore = 1; let CVINew = 1; let isNewValue = 1; @@ -30216,38 +27814,16 @@ let DecoderNamespace = "EXT_mmvec"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_new_pred_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Os8), -"if ($Pv4) vmem($Rx32++#$Ii):nt = $Os8.new", -tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-3} = 0b01010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001111; -let isPredicated = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNVStore = 1; -let CVINew = 1; -let isNewValue = 1; -let isNonTemporal = 1; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_pi_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 4; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nt_new_pred_ppu : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Os8), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8), "if ($Pv4) vmem($Rx32++$Mu2):nt = $Os8.new", tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{10-3} = 0b00001010; let Inst{31-21} = 0b00101011111; let isPredicated = 1; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNVStore = 1; let CVINew = 1; let isNewValue = 1; @@ -30258,30 +27834,9 @@ let DecoderNamespace = "EXT_mmvec"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_new_pred_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Os8), -"if ($Pv4) vmem($Rx32++$Mu2):nt = $Os8.new", -tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{10-3} = 0b00001010; -let Inst{31-21} = 0b00101011111; -let isPredicated = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNVStore = 1; -let CVINew = 1; -let isNewValue = 1; -let isNonTemporal = 1; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_ppu_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 4; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nt_npred_ai : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "if (!$Pv4) vmem($Rt32+#$Ii):nt = $Vs32", tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b001; @@ -30289,34 +27844,16 @@ let Inst{31-21} = 0b00101000111; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNonTemporal = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_ai"; let isNVStorable = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vS32b_nt_npred_ai_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), -"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Vs32", -tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b001; -let Inst{31-21} = 0b00101000111; -let isPredicated = 1; -let isPredicatedFalse = 1; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isNonTemporal = 1; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_ai_128B"; -let isNVStorable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vS32b_nt_npred_pi : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "if (!$Pv4) vmem($Rx32++#$Ii):nt = $Vs32", tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b001; @@ -30325,7 +27862,7 @@ let Inst{31-21} = 0b00101001111; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNonTemporal = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_pi"; @@ -30333,29 +27870,9 @@ let isNVStorable = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_npred_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), -"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Vs32", -tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001111; -let isPredicated = 1; -let isPredicatedFalse = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNonTemporal = 1; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_pi_128B"; -let isNVStorable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nt_npred_ppu : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "if (!$Pv4) vmem($Rx32++$Mu2):nt = $Vs32", tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{10-5} = 0b000001; @@ -30363,7 +27880,7 @@ let Inst{31-21} = 0b00101011111; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNonTemporal = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_ppu"; @@ -30371,122 +27888,58 @@ let isNVStorable = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_npred_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), -"if (!$Pv4) vmem($Rx32++$Mu2):nt = $Vs32", -tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{10-5} = 0b000001; -let Inst{31-21} = 0b00101011111; -let isPredicated = 1; -let isPredicatedFalse = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNonTemporal = 1; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_ppu_128B"; -let isNVStorable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nt_nqpred_ai : HInst< (outs), -(ins VecPredRegs:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "if (!$Qv4) vmem($Rt32+#$Ii):nt = $Vs32", tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; let Inst{31-21} = 0b00101000110; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNonTemporal = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vS32b_nt_nqpred_ai_128B : HInst< -(outs), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), -"if (!$Qv4) vmem($Rt32+#$Ii):nt = $Vs32", -tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{31-21} = 0b00101000110; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isNonTemporal = 1; -let mayStore = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vS32b_nt_nqpred_pi : HInst< (outs IntRegs:$Rx32), -(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "if (!$Qv4) vmem($Rx32++#$Ii):nt = $Vs32", tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001110; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNonTemporal = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_nqpred_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), -"if (!$Qv4) vmem($Rx32++#$Ii):nt = $Vs32", -tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001110; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNonTemporal = 1; -let mayStore = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nt_nqpred_ppu : HInst< (outs IntRegs:$Rx32), -(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "if (!$Qv4) vmem($Rx32++$Mu2):nt = $Vs32", tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[HasV60T,UseHVX]> { let Inst{10-5} = 0b000001; let Inst{31-21} = 0b00101011110; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNonTemporal = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_nqpred_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), -"if (!$Qv4) vmem($Rx32++$Mu2):nt = $Vs32", -tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[HasV60T,UseHVX]> { -let Inst{10-5} = 0b000001; -let Inst{31-21} = 0b00101011110; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNonTemporal = 1; -let mayStore = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nt_pi : HInst< (outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "vmem($Rx32++#$Ii):nt = $Vs32", tc_a4c9df3b, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b000; let Inst{13-11} = 0b000; let Inst{31-21} = 0b00101001011; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNonTemporal = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_pi"; @@ -30495,34 +27948,15 @@ let isPredicable = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), -"vmem($Rx32++#$Ii):nt = $Vs32", -tc_a4c9df3b, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b000; -let Inst{13-11} = 0b000; -let Inst{31-21} = 0b00101001011; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNonTemporal = 1; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_pi_128B"; -let isNVStorable = 1; -let isPredicable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nt_ppu : HInst< (outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "vmem($Rx32++$Mu2):nt = $Vs32", tc_a4c9df3b, TypeCVI_VM_ST>, Enc_d15d19, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b00101011011; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNonTemporal = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_ppu"; @@ -30531,60 +27965,25 @@ let isPredicable = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), -"vmem($Rx32++$Mu2):nt = $Vs32", -tc_a4c9df3b, TypeCVI_VM_ST>, Enc_d15d19, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{12-5} = 0b00000000; -let Inst{31-21} = 0b00101011011; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNonTemporal = 1; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_ppu_128B"; -let isNVStorable = 1; -let isPredicable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nt_pred_ai : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "if ($Pv4) vmem($Rt32+#$Ii):nt = $Vs32", tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b000; let Inst{31-21} = 0b00101000111; let isPredicated = 1; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNonTemporal = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_ai"; let isNVStorable = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vS32b_nt_pred_ai_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), -"if ($Pv4) vmem($Rt32+#$Ii):nt = $Vs32", -tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b000; -let Inst{31-21} = 0b00101000111; -let isPredicated = 1; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isNonTemporal = 1; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_ai_128B"; -let isNVStorable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vS32b_nt_pred_pi : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "if ($Pv4) vmem($Rx32++#$Ii):nt = $Vs32", tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b000; @@ -30592,7 +27991,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001111; let isPredicated = 1; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNonTemporal = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_pi"; @@ -30600,35 +27999,16 @@ let isNVStorable = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_pred_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), -"if ($Pv4) vmem($Rx32++#$Ii):nt = $Vs32", -tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001111; -let isPredicated = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNonTemporal = 1; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_pi_128B"; -let isNVStorable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nt_pred_ppu : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "if ($Pv4) vmem($Rx32++$Mu2):nt = $Vs32", tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{10-5} = 0b000000; let Inst{31-21} = 0b00101011111; let isPredicated = 1; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNonTemporal = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_ppu"; @@ -30636,121 +28016,58 @@ let isNVStorable = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_pred_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), -"if ($Pv4) vmem($Rx32++$Mu2):nt = $Vs32", -tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{10-5} = 0b000000; -let Inst{31-21} = 0b00101011111; -let isPredicated = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNonTemporal = 1; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_ppu_128B"; -let isNVStorable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nt_qpred_ai : HInst< (outs), -(ins VecPredRegs:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "if ($Qv4) vmem($Rt32+#$Ii):nt = $Vs32", tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; let Inst{31-21} = 0b00101000110; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNonTemporal = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vS32b_nt_qpred_ai_128B : HInst< -(outs), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), -"if ($Qv4) vmem($Rt32+#$Ii):nt = $Vs32", -tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{31-21} = 0b00101000110; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isNonTemporal = 1; -let mayStore = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vS32b_nt_qpred_pi : HInst< (outs IntRegs:$Rx32), -(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "if ($Qv4) vmem($Rx32++#$Ii):nt = $Vs32", tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001110; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNonTemporal = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_qpred_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), -"if ($Qv4) vmem($Rx32++#$Ii):nt = $Vs32", -tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001110; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNonTemporal = 1; -let mayStore = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nt_qpred_ppu : HInst< (outs IntRegs:$Rx32), -(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "if ($Qv4) vmem($Rx32++$Mu2):nt = $Vs32", tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[HasV60T,UseHVX]> { let Inst{10-5} = 0b000000; let Inst{31-21} = 0b00101011110; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let isNonTemporal = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_qpred_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), -"if ($Qv4) vmem($Rx32++$Mu2):nt = $Vs32", -tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[HasV60T,UseHVX]> { -let Inst{10-5} = 0b000000; -let Inst{31-21} = 0b00101011110; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNonTemporal = 1; -let mayStore = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_pi : HInst< (outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "vmem($Rx32++#$Ii) = $Vs32", tc_a4c9df3b, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b000; let Inst{13-11} = 0b000; let Inst{31-21} = 0b00101001001; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let mayStore = 1; let BaseOpcode = "V6_vS32b_pi"; let isNVStorable = 1; @@ -30758,89 +28075,39 @@ let isPredicable = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), -"vmem($Rx32++#$Ii) = $Vs32", -tc_a4c9df3b, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b000; -let Inst{13-11} = 0b000; -let Inst{31-21} = 0b00101001001; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_pi_128B"; -let isNVStorable = 1; -let isPredicable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_ppu : HInst< (outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "vmem($Rx32++$Mu2) = $Vs32", tc_a4c9df3b, TypeCVI_VM_ST>, Enc_d15d19, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b00101011001; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let mayStore = 1; let isNVStorable = 1; let isPredicable = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), -"vmem($Rx32++$Mu2) = $Vs32", -tc_a4c9df3b, TypeCVI_VM_ST>, Enc_d15d19, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{12-5} = 0b00000000; -let Inst{31-21} = 0b00101011001; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let isNVStorable = 1; -let isPredicable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_pred_ai : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "if ($Pv4) vmem($Rt32+#$Ii) = $Vs32", tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b000; let Inst{31-21} = 0b00101000101; let isPredicated = 1; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let mayStore = 1; let BaseOpcode = "V6_vS32b_ai"; let isNVStorable = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vS32b_pred_ai_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), -"if ($Pv4) vmem($Rt32+#$Ii) = $Vs32", -tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b000; -let Inst{31-21} = 0b00101000101; -let isPredicated = 1; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_ai_128B"; -let isNVStorable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vS32b_pred_pi : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "if ($Pv4) vmem($Rx32++#$Ii) = $Vs32", tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -30848,146 +28115,70 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001101; let isPredicated = 1; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let mayStore = 1; let BaseOpcode = "V6_vS32b_pi"; let isNVStorable = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_pred_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), -"if ($Pv4) vmem($Rx32++#$Ii) = $Vs32", -tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001101; -let isPredicated = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_pi_128B"; -let isNVStorable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_pred_ppu : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "if ($Pv4) vmem($Rx32++$Mu2) = $Vs32", tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[HasV60T,UseHVX]> { let Inst{10-5} = 0b000000; let Inst{31-21} = 0b00101011101; let isPredicated = 1; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let mayStore = 1; let isNVStorable = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_pred_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), -"if ($Pv4) vmem($Rx32++$Mu2) = $Vs32", -tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[HasV60T,UseHVX]> { -let Inst{10-5} = 0b000000; -let Inst{31-21} = 0b00101011101; -let isPredicated = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let isNVStorable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_qpred_ai : HInst< (outs), -(ins VecPredRegs:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "if ($Qv4) vmem($Rt32+#$Ii) = $Vs32", tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; let Inst{31-21} = 0b00101000100; let addrMode = BaseImmOffset; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vS32b_qpred_ai_128B : HInst< -(outs), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), -"if ($Qv4) vmem($Rt32+#$Ii) = $Vs32", -tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{31-21} = 0b00101000100; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let mayStore = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vS32b_qpred_pi : HInst< (outs IntRegs:$Rx32), -(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "if ($Qv4) vmem($Rx32++#$Ii) = $Vs32", tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001100; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_qpred_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), -"if ($Qv4) vmem($Rx32++#$Ii) = $Vs32", -tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001100; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_qpred_ppu : HInst< (outs IntRegs:$Rx32), -(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "if ($Qv4) vmem($Rx32++$Mu2) = $Vs32", tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[HasV60T,UseHVX]> { let Inst{10-5} = 0b000000; let Inst{31-21} = 0b00101011100; let addrMode = PostInc; -let accessSize = Vector64Access; +let accessSize = HVXVectorAccess; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_qpred_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), -"if ($Qv4) vmem($Rx32++$Mu2) = $Vs32", -tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[HasV60T,UseHVX]> { -let Inst{10-5} = 0b000000; -let Inst{31-21} = 0b00101011100; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vabsdiffh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vabsdiff($Vu32.h,$Vv32.h)", tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -30997,22 +28188,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vabsdiffh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.uh = vabsdiff($Vu32.h,$Vv32.h)", -tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vabsdiffh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vabsdiffh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -31021,21 +28199,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vabsdiffh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vabsdiffh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vabsdiffub : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vabsdiff($Vu32.ub,$Vv32.ub)", tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -31045,22 +28211,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vabsdiffub_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.ub = vabsdiff($Vu32.ub,$Vv32.ub)", -tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vabsdiffub_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vabsdiffub($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -31069,21 +28222,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vabsdiffub_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vabsdiffub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vabsdiffuh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vabsdiff($Vu32.uh,$Vv32.uh)", tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -31093,22 +28234,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vabsdiffuh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.uh = vabsdiff($Vu32.uh,$Vv32.uh)", -tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vabsdiffuh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vabsdiffuh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -31117,21 +28245,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vabsdiffuh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vabsdiffuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vabsdiffw : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uw = vabsdiff($Vu32.w,$Vv32.w)", tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -31141,22 +28257,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vabsdiffw_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.uw = vabsdiff($Vu32.w,$Vv32.w)", -tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vabsdiffw_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vabsdiffw($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -31165,21 +28268,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vabsdiffw_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vabsdiffw($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vabsh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32.h = vabs($Vu32.h)", tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -31189,22 +28280,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vabsh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32.h = vabs($Vu32.h)", -tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vabsh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32 = vabsh($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -31213,21 +28291,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vabsh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32 = vabsh($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vabsh_sat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32.h = vabs($Vu32.h):sat", tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -31237,22 +28303,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vabsh_sat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32.h = vabs($Vu32.h):sat", -tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vabsh_sat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32 = vabsh($Vu32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -31261,21 +28314,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vabsh_sat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32 = vabsh($Vu32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vabsw : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32.w = vabs($Vu32.w)", tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -31285,22 +28326,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vabsw_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32.w = vabs($Vu32.w)", -tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vabsw_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32 = vabsw($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -31309,21 +28337,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vabsw_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32 = vabsw($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vabsw_sat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32.w = vabs($Vu32.w):sat", tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -31333,22 +28349,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vabsw_sat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32.w = vabs($Vu32.w):sat", -tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vabsw_sat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32 = vabsw($Vu32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -31357,21 +28360,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vabsw_sat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32 = vabsw($Vu32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vadd($Vu32.b,$Vv32.b)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -31381,22 +28372,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.b = vadd($Vu32.b,$Vv32.b)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddb_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vaddb($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -31405,21 +28383,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddb_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vaddb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddb_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.b = vadd($Vuu32.b,$Vvv32.b)", tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -31429,22 +28395,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddb_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32.b = vadd($Vuu32.b,$Vvv32.b)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddb_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vaddb($Vuu32,$Vvv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -31453,21 +28406,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddb_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32 = vaddb($Vuu32,$Vvv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddbnq : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4) $Vx32.b += $Vu32.b", tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -31480,25 +28421,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vaddbnq_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), -"if (!$Qv4) $Vx32.b += $Vu32.b", -tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b1; -let Inst{21-16} = 0b000001; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vaddbnq_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4.b) $Vx32.b += $Vu32.b", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -31509,23 +28434,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vaddbnq_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), -"if (!$Qv4.b) $Vx32.b += $Vu32.b", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vaddbq : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4) $Vx32.b += $Vu32.b", tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -31538,25 +28449,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vaddbq_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), -"if ($Qv4) $Vx32.b += $Vu32.b", -tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b1; -let Inst{21-16} = 0b000001; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vaddbq_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4.b) $Vx32.b += $Vu32.b", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -31567,23 +28462,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vaddbq_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), -"if ($Qv4.b) $Vx32.b += $Vu32.b", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vaddbsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vadd($Vu32.b,$Vv32.b):sat", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b000; @@ -31593,22 +28474,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddbsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.b = vadd($Vu32.b,$Vv32.b):sat", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddbsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vaddb($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -31617,21 +28485,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddbsat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vaddb($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddbsat_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.b = vadd($Vuu32.b,$Vvv32.b):sat", tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b000; @@ -31641,22 +28497,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddbsat_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32.b = vadd($Vuu32.b,$Vvv32.b):sat", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011110101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddbsat_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vaddb($Vuu32,$Vvv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -31665,21 +28508,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddbsat_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32 = vaddb($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddcarry : HInst< -(outs VectorRegs:$Vd32, VecPredRegs:$Qx4), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, VecPredRegs:$Qx4in), +(outs HvxVR:$Vd32, HvxQR:$Qx4), +(ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qx4in), "$Vd32.w = vadd($Vu32.w,$Vv32.w,$Qx4):carry", tc_5a9fc4ec, TypeCVI_VA>, Enc_b43b67, Requires<[HasV62T,UseHVX]> { let Inst{7-7} = 0b0; @@ -31692,25 +28523,9 @@ let opNewValue2 = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vaddcarry_128B : HInst< -(outs VectorRegs128B:$Vd32, VecPredRegs128B:$Qx4), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, VecPredRegs128B:$Qx4in), -"$Vd32.w = vadd($Vu32.w,$Vv32.w,$Qx4):carry", -tc_5a9fc4ec, TypeCVI_VA>, Enc_b43b67, Requires<[HasV62T,UseHVX]> { -let Inst{7-7} = 0b0; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100101; -let hasNewValue = 1; -let opNewValue = 0; -let hasNewValue2 = 1; -let opNewValue2 = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_vaddclbh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vadd(vclb($Vu32.h),$Vv32.h)", tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b000; @@ -31720,22 +28535,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddclbh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.h = vadd(vclb($Vu32.h),$Vv32.h)", -tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011111000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddclbw : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vadd(vclb($Vu32.w),$Vv32.w)", tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b001; @@ -31745,22 +28547,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddclbw_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.w = vadd(vclb($Vu32.w),$Vv32.w)", -tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011111000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vadd($Vu32.h,$Vv32.h)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -31770,22 +28559,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.h = vadd($Vu32.h,$Vv32.h)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vaddh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -31794,21 +28570,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vaddh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddh_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.h = vadd($Vuu32.h,$Vvv32.h)", tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -31818,22 +28582,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddh_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32.h = vadd($Vuu32.h,$Vvv32.h)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddh_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vaddh($Vuu32,$Vvv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -31842,21 +28593,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddh_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32 = vaddh($Vuu32,$Vvv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddhnq : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4) $Vx32.h += $Vu32.h", tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -31869,25 +28608,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vaddhnq_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), -"if (!$Qv4) $Vx32.h += $Vu32.h", -tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b1; -let Inst{21-16} = 0b000001; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vaddhnq_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4.h) $Vx32.h += $Vu32.h", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -31898,23 +28621,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vaddhnq_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), -"if (!$Qv4.h) $Vx32.h += $Vu32.h", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vaddhq : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4) $Vx32.h += $Vu32.h", tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -31927,25 +28636,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vaddhq_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), -"if ($Qv4) $Vx32.h += $Vu32.h", -tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b1; -let Inst{21-16} = 0b000001; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vaddhq_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4.h) $Vx32.h += $Vu32.h", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -31956,23 +28649,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vaddhq_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), -"if ($Qv4.h) $Vx32.h += $Vu32.h", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vaddhsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vadd($Vu32.h,$Vv32.h):sat", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -31982,22 +28661,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddhsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.h = vadd($Vu32.h,$Vv32.h):sat", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddhsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vaddh($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -32006,21 +28672,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddhsat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vaddh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddhsat_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.h = vadd($Vuu32.h,$Vvv32.h):sat", tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -32030,22 +28684,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddhsat_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32.h = vadd($Vuu32.h,$Vvv32.h):sat", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddhsat_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vaddh($Vuu32,$Vvv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -32054,21 +28695,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddhsat_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32 = vaddh($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddhw : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.w = vadd($Vu32.h,$Vv32.h)", tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -32078,22 +28707,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddhw_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32.w = vadd($Vu32.h,$Vv32.h)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddhw_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32.w += vadd($Vu32.h,$Vv32.h)", tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b010; @@ -32105,24 +28721,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vaddhw_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vxx32.w += vadd($Vu32.h,$Vv32.h)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vaddhw_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32 += vaddh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -32133,23 +28734,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vaddhw_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vxx32 += vaddh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vaddhw_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vaddh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -32158,21 +28745,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddhw_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32 = vaddh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddubh : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.h = vadd($Vu32.ub,$Vv32.ub)", tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -32182,22 +28757,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddubh_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32.h = vadd($Vu32.ub,$Vv32.ub)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddubh_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32.h += vadd($Vu32.ub,$Vv32.ub)", tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b101; @@ -32209,24 +28771,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vaddubh_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vxx32.h += vadd($Vu32.ub,$Vv32.ub)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100010; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vaddubh_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32 += vaddub($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -32237,23 +28784,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vaddubh_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vxx32 += vaddub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vaddubh_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vaddub($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -32262,21 +28795,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddubh_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32 = vaddub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddubsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vadd($Vu32.ub,$Vv32.ub):sat", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -32286,22 +28807,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddubsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.ub = vadd($Vu32.ub,$Vv32.ub):sat", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddubsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vaddub($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -32310,21 +28818,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddubsat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vaddub($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddubsat_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.ub = vadd($Vuu32.ub,$Vvv32.ub):sat", tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -32334,22 +28830,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddubsat_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32.ub = vadd($Vuu32.ub,$Vvv32.ub):sat", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddubsat_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vaddub($Vuu32,$Vvv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -32358,21 +28841,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddubsat_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32 = vaddub($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddububb_sat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vadd($Vu32.ub,$Vv32.b):sat", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b100; @@ -32382,22 +28853,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddububb_sat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.ub = vadd($Vu32.ub,$Vv32.b):sat", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011110101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vadduhsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vadd($Vu32.uh,$Vv32.uh):sat", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -32407,22 +28865,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vadduhsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.uh = vadd($Vu32.uh,$Vv32.uh):sat", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vadduhsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vadduh($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -32431,21 +28876,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vadduhsat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vadduh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vadduhsat_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.uh = vadd($Vuu32.uh,$Vvv32.uh):sat", tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -32455,22 +28888,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vadduhsat_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32.uh = vadd($Vuu32.uh,$Vvv32.uh):sat", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vadduhsat_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vadduh($Vuu32,$Vvv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -32479,21 +28899,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vadduhsat_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32 = vadduh($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vadduhw : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.w = vadd($Vu32.uh,$Vv32.uh)", tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -32503,22 +28911,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vadduhw_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32.w = vadd($Vu32.uh,$Vv32.uh)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vadduhw_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32.w += vadd($Vu32.uh,$Vv32.uh)", tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b100; @@ -32530,24 +28925,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vadduhw_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vxx32.w += vadd($Vu32.uh,$Vv32.uh)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100010; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vadduhw_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32 += vadduh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -32558,23 +28938,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vadduhw_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vxx32 += vadduh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vadduhw_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vadduh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -32583,21 +28949,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vadduhw_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32 = vadduh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vadduwsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uw = vadd($Vu32.uw,$Vv32.uw):sat", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b001; @@ -32607,22 +28961,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vadduwsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.uw = vadd($Vu32.uw,$Vv32.uw):sat", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vadduwsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vadduw($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -32631,21 +28972,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vadduwsat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vadduw($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vadduwsat_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.uw = vadd($Vuu32.uw,$Vvv32.uw):sat", tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b010; @@ -32655,22 +28984,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vadduwsat_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32.uw = vadd($Vuu32.uw,$Vvv32.uw):sat", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011110101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vadduwsat_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vadduw($Vuu32,$Vvv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -32679,21 +28995,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vadduwsat_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32 = vadduw($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddw : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vadd($Vu32.w,$Vv32.w)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -32703,22 +29007,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddw_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.w = vadd($Vu32.w,$Vv32.w)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddw_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vaddw($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -32727,21 +29018,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddw_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vaddw($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddw_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.w = vadd($Vuu32.w,$Vvv32.w)", tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -32751,22 +29030,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddw_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32.w = vadd($Vuu32.w,$Vvv32.w)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddw_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vaddw($Vuu32,$Vvv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -32775,21 +29041,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddw_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32 = vaddw($Vuu32,$Vvv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddwnq : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4) $Vx32.w += $Vu32.w", tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -32802,25 +29056,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vaddwnq_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), -"if (!$Qv4) $Vx32.w += $Vu32.w", -tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b1; -let Inst{21-16} = 0b000001; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vaddwnq_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4.w) $Vx32.w += $Vu32.w", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -32831,23 +29069,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vaddwnq_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), -"if (!$Qv4.w) $Vx32.w += $Vu32.w", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vaddwq : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4) $Vx32.w += $Vu32.w", tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -32860,25 +29084,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vaddwq_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), -"if ($Qv4) $Vx32.w += $Vu32.w", -tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b1; -let Inst{21-16} = 0b000001; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vaddwq_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4.w) $Vx32.w += $Vu32.w", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -32889,23 +29097,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vaddwq_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), -"if ($Qv4.w) $Vx32.w += $Vu32.w", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vaddwsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vadd($Vu32.w,$Vv32.w):sat", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -32915,22 +29109,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddwsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.w = vadd($Vu32.w,$Vv32.w):sat", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddwsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vaddw($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -32939,21 +29120,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddwsat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vaddw($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddwsat_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.w = vadd($Vuu32.w,$Vvv32.w):sat", tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -32963,22 +29132,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddwsat_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32.w = vadd($Vuu32.w,$Vvv32.w):sat", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddwsat_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vaddw($Vuu32,$Vvv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -32987,21 +29143,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddwsat_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32 = vaddw($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_valignb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32 = valign($Vu32,$Vv32,$Rt8)", tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -33011,22 +29155,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_valignb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), -"$Vd32 = valign($Vu32,$Vv32,$Rt8)", -tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_valignbi : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, u3_0Imm:$Ii), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii), "$Vd32 = valign($Vu32,$Vv32,#$Ii)", tc_c4b515c5, TypeCVI_VP>, Enc_0b2e5b, Requires<[HasV60T,UseHVX]> { let Inst{13-13} = 0b1; @@ -33035,21 +29166,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_valignbi_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, u3_0Imm:$Ii), -"$Vd32 = valign($Vu32,$Vv32,#$Ii)", -tc_c4b515c5, TypeCVI_VP>, Enc_0b2e5b, Requires<[HasV60T,UseHVX]> { -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011110001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vand : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vand($Vu32,$Vv32)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -33059,22 +29178,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vand_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vand($Vu32,$Vv32)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vandnqrt : HInst< -(outs VectorRegs:$Vd32), -(ins VecPredRegs:$Qu4, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxQR:$Qu4, IntRegs:$Rt32), "$Vd32 = vand(!$Qu4,$Rt32)", tc_e231aa4f, TypeCVI_VX>, Enc_7b7ba8, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b101; @@ -33084,22 +29190,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vandnqrt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VecPredRegs128B:$Qu4, IntRegs:$Rt32), -"$Vd32 = vand(!$Qu4,$Rt32)", -tc_e231aa4f, TypeCVI_VX>, Enc_7b7ba8, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-10} = 0b0001; -let Inst{31-21} = 0b00011001101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vandnqrt_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VecPredRegs:$Qu4, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32), "$Vx32 |= vand(!$Qu4,$Rt32)", tc_9311da3f, TypeCVI_VX>, Enc_895bd9, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b011; @@ -33111,24 +29204,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vandnqrt_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VecPredRegs128B:$Qu4, IntRegs:$Rt32), -"$Vx32 |= vand(!$Qu4,$Rt32)", -tc_9311da3f, TypeCVI_VX>, Enc_895bd9, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-10} = 0b1001; -let Inst{31-21} = 0b00011001011; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vandnqrt_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VecPredRegs:$Qu4, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32), "$Vx32.ub |= vand(!$Qu4.ub,$Rt32.ub)", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -33139,23 +29217,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vandnqrt_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VecPredRegs128B:$Qu4, IntRegs:$Rt32), -"$Vx32.ub |= vand(!$Qu4.ub,$Rt32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vandnqrt_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VecPredRegs:$Qu4, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxQR:$Qu4, IntRegs:$Rt32), "$Vd32.ub = vand(!$Qu4.ub,$Rt32.ub)", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -33164,21 +29228,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vandnqrt_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VecPredRegs128B:$Qu4, IntRegs:$Rt32), -"$Vd32.ub = vand(!$Qu4.ub,$Rt32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vandqrt : HInst< -(outs VectorRegs:$Vd32), -(ins VecPredRegs:$Qu4, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxQR:$Qu4, IntRegs:$Rt32), "$Vd32 = vand($Qu4,$Rt32)", tc_e231aa4f, TypeCVI_VX_LATE>, Enc_7b7ba8, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -33188,22 +29240,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vandqrt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VecPredRegs128B:$Qu4, IntRegs:$Rt32), -"$Vd32 = vand($Qu4,$Rt32)", -tc_e231aa4f, TypeCVI_VX_LATE>, Enc_7b7ba8, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-10} = 0b0000; -let Inst{31-21} = 0b00011001101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vandqrt_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VecPredRegs:$Qu4, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32), "$Vx32 |= vand($Qu4,$Rt32)", tc_9311da3f, TypeCVI_VX_LATE>, Enc_895bd9, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -33215,24 +29254,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vandqrt_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VecPredRegs128B:$Qu4, IntRegs:$Rt32), -"$Vx32 |= vand($Qu4,$Rt32)", -tc_9311da3f, TypeCVI_VX_LATE>, Enc_895bd9, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-10} = 0b1000; -let Inst{31-21} = 0b00011001011; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vandqrt_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VecPredRegs:$Qu4, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32), "$Vx32.ub |= vand($Qu4.ub,$Rt32.ub)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -33243,23 +29267,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vandqrt_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VecPredRegs128B:$Qu4, IntRegs:$Rt32), -"$Vx32.ub |= vand($Qu4.ub,$Rt32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vandqrt_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VecPredRegs:$Qu4, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxQR:$Qu4, IntRegs:$Rt32), "$Vd32.ub = vand($Qu4.ub,$Rt32.ub)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -33268,21 +29278,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vandqrt_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VecPredRegs128B:$Qu4, IntRegs:$Rt32), -"$Vd32.ub = vand($Qu4.ub,$Rt32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vandvnqv : HInst< -(outs VectorRegs:$Vd32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxQR:$Qv4, HvxVR:$Vu32), "$Vd32 = vand(!$Qv4,$Vu32)", tc_bbaf280e, TypeCVI_VA>, Enc_c4dc92, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b001; @@ -33293,23 +29291,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vandvnqv_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vu32), -"$Vd32 = vand(!$Qv4,$Vu32)", -tc_bbaf280e, TypeCVI_VA>, Enc_c4dc92, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b1; -let Inst{21-16} = 0b000011; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vandvqv : HInst< -(outs VectorRegs:$Vd32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxQR:$Qv4, HvxVR:$Vu32), "$Vd32 = vand($Qv4,$Vu32)", tc_bbaf280e, TypeCVI_VA>, Enc_c4dc92, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b000; @@ -33320,23 +29304,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vandvqv_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vu32), -"$Vd32 = vand($Qv4,$Vu32)", -tc_bbaf280e, TypeCVI_VA>, Enc_c4dc92, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b1; -let Inst{21-16} = 0b000011; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vandvrt : HInst< -(outs VecPredRegs:$Qd4), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxQR:$Qd4), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Qd4 = vand($Vu32,$Rt32)", tc_e231aa4f, TypeCVI_VX_LATE>, Enc_0f8bab, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b010010; @@ -33346,22 +29316,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vandvrt_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Qd4 = vand($Vu32,$Rt32)", -tc_e231aa4f, TypeCVI_VX_LATE>, Enc_0f8bab, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b010010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vandvrt_acc : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, IntRegs:$Rt32), "$Qx4 |= vand($Vu32,$Rt32)", tc_9311da3f, TypeCVI_VX_LATE>, Enc_adf111, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b100000; @@ -33373,24 +29330,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vandvrt_acc_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Qx4 |= vand($Vu32,$Rt32)", -tc_9311da3f, TypeCVI_VX_LATE>, Enc_adf111, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b100000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001011; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_vandvrt_acc_alt : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, IntRegs:$Rt32), "$Qx4.ub |= vand($Vu32.ub,$Rt32.ub)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -33401,23 +29343,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vandvrt_acc_alt_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Qx4.ub |= vand($Vu32.ub,$Rt32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_vandvrt_alt : HInst< -(outs VecPredRegs:$Qd4), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxQR:$Qd4), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Qd4.ub = vand($Vu32.ub,$Rt32.ub)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -33426,21 +29354,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vandvrt_alt_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Qd4.ub = vand($Vu32.ub,$Rt32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaslh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.h = vasl($Vu32.h,$Rt32)", tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -33450,22 +29366,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaslh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32.h = vasl($Vu32.h,$Rt32)", -tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaslh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vaslh($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -33474,21 +29377,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaslh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32 = vaslh($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaslhv : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vasl($Vu32.h,$Vv32.h)", tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -33498,22 +29389,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaslhv_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.h = vasl($Vu32.h,$Vv32.h)", -tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaslhv_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vaslh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -33522,21 +29400,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaslhv_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vaslh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaslw : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.w = vasl($Vu32.w,$Rt32)", tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -33546,22 +29412,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaslw_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32.w = vasl($Vu32.w,$Rt32)", -tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaslw_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.w += vasl($Vu32.w,$Rt32)", tc_c00bf9c9, TypeCVI_VS>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -33573,24 +29426,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vaslw_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vx32.w += vasl($Vu32.w,$Rt32)", -tc_c00bf9c9, TypeCVI_VS>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001011; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vaslw_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vaslw($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -33601,23 +29439,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vaslw_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vx32 += vaslw($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vaslw_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vaslw($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -33626,21 +29450,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaslw_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32 = vaslw($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaslwv : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vasl($Vu32.w,$Vv32.w)", tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -33650,22 +29462,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaslwv_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.w = vasl($Vu32.w,$Vv32.w)", -tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaslwv_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vaslw($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -33674,21 +29473,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaslwv_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vaslw($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vasrh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.h = vasr($Vu32.h,$Rt32)", tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -33698,22 +29485,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32.h = vasr($Vu32.h,$Rt32)", -tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vasrh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vasrh($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -33722,21 +29496,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32 = vasrh($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vasrhbrndsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat", tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -33746,22 +29508,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrhbrndsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), -"$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat", -tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b1; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vasrhbrndsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32 = vasrhb($Vu32,$Vv32,$Rt8):rnd:sat", tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60T]> { let hasNewValue = 1; @@ -33770,8 +29519,8 @@ let isPseudo = 1; let isCodeGenOnly = 1; } def V6_vasrhbsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):sat", tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b000; @@ -33781,22 +29530,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrhbsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), -"$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):sat", -tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-24} = 0b00011000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vasrhubrndsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat", tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -33806,22 +29542,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrhubrndsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), -"$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat", -tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vasrhubrndsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):rnd:sat", tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60T]> { let hasNewValue = 1; @@ -33830,8 +29553,8 @@ let isPseudo = 1; let isCodeGenOnly = 1; } def V6_vasrhubsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):sat", tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -33841,22 +29564,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrhubsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), -"$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):sat", -tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vasrhubsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):sat", tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60T]> { let hasNewValue = 1; @@ -33865,8 +29575,8 @@ let isPseudo = 1; let isCodeGenOnly = 1; } def V6_vasrhv : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vasr($Vu32.h,$Vv32.h)", tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -33876,22 +29586,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrhv_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.h = vasr($Vu32.h,$Vv32.h)", -tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vasrhv_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vasrh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -33900,21 +29597,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrhv_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vasrh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vasruwuhrndsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.uh = vasr($Vu32.uw,$Vv32.uw,$Rt8):rnd:sat", tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b001; @@ -33924,22 +29609,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasruwuhrndsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), -"$Vd32.uh = vasr($Vu32.uw,$Vv32.uw,$Rt8):rnd:sat", -tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-24} = 0b00011000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vasrw : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.w = vasr($Vu32.w,$Rt32)", tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -33949,22 +29621,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrw_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32.w = vasr($Vu32.w,$Rt32)", -tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vasrw_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.w += vasr($Vu32.w,$Rt32)", tc_c00bf9c9, TypeCVI_VS>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -33976,24 +29635,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vasrw_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vx32.w += vasr($Vu32.w,$Rt32)", -tc_c00bf9c9, TypeCVI_VS>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001011; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vasrw_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vasrw($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34004,23 +29648,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vasrw_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vx32 += vasrw($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vasrw_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vasrw($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34029,21 +29659,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrw_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32 = vasrw($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vasrwh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8)", tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -34053,22 +29671,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrwh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), -"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8)", -tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vasrwh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32 = vasrwh($Vu32,$Vv32,$Rt8)", tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60T]> { let hasNewValue = 1; @@ -34077,8 +29682,8 @@ let isPseudo = 1; let isCodeGenOnly = 1; } def V6_vasrwhrndsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat", tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -34088,22 +29693,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrwhrndsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), -"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat", -tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vasrwhrndsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):rnd:sat", tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60T]> { let hasNewValue = 1; @@ -34112,8 +29704,8 @@ let isPseudo = 1; let isCodeGenOnly = 1; } def V6_vasrwhsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):sat", tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -34123,22 +29715,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrwhsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), -"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):sat", -tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vasrwhsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):sat", tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60T]> { let hasNewValue = 1; @@ -34147,8 +29726,8 @@ let isPseudo = 1; let isCodeGenOnly = 1; } def V6_vasrwuhrndsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat", tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b010; @@ -34158,22 +29737,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrwuhrndsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), -"$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat", -tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-24} = 0b00011000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vasrwuhsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):sat", tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -34183,22 +29749,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrwuhsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), -"$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):sat", -tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vasrwuhsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32 = vasrwuh($Vu32,$Vv32,$Rt8):sat", tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60T]> { let hasNewValue = 1; @@ -34207,8 +29760,8 @@ let isPseudo = 1; let isCodeGenOnly = 1; } def V6_vasrwv : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vasr($Vu32.w,$Vv32.w)", tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -34218,22 +29771,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrwv_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.w = vasr($Vu32.w,$Vv32.w)", -tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vasrwv_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vasrw($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34242,21 +29782,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrwv_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vasrw($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vassign : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32 = $Vu32", tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -34266,22 +29794,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vassign_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32 = $Vu32", -tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b1; -let Inst{31-16} = 0b0001111000000011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vassignp : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32), "$Vdd32 = $Vuu32", CVI_VA, TypeCVI_VA_DV>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34289,20 +29804,9 @@ let opNewValue = 0; let isPseudo = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vassignp_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32), -"$Vdd32 = $Vuu32", -CVI_VA, TypeCVI_VA_DV>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vavgh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vavg($Vu32.h,$Vv32.h)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -34312,22 +29816,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vavgh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.h = vavg($Vu32.h,$Vv32.h)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vavgh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vavgh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34336,21 +29827,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vavgh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vavgh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vavghrnd : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vavg($Vu32.h,$Vv32.h):rnd", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -34360,22 +29839,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vavghrnd_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.h = vavg($Vu32.h,$Vv32.h):rnd", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vavghrnd_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vavgh($Vu32,$Vv32):rnd", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34384,21 +29850,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vavghrnd_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vavgh($Vu32,$Vv32):rnd", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vavgub : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vavg($Vu32.ub,$Vv32.ub)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -34408,22 +29862,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vavgub_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.ub = vavg($Vu32.ub,$Vv32.ub)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vavgub_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vavgub($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34432,21 +29873,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vavgub_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vavgub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vavgubrnd : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vavg($Vu32.ub,$Vv32.ub):rnd", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -34456,22 +29885,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vavgubrnd_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.ub = vavg($Vu32.ub,$Vv32.ub):rnd", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vavgubrnd_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vavgub($Vu32,$Vv32):rnd", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34480,21 +29896,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vavgubrnd_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vavgub($Vu32,$Vv32):rnd", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vavguh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vavg($Vu32.uh,$Vv32.uh)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -34504,22 +29908,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vavguh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.uh = vavg($Vu32.uh,$Vv32.uh)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vavguh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vavguh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34528,21 +29919,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vavguh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vavguh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vavguhrnd : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vavg($Vu32.uh,$Vv32.uh):rnd", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -34552,22 +29931,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vavguhrnd_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.uh = vavg($Vu32.uh,$Vv32.uh):rnd", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vavguhrnd_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vavguh($Vu32,$Vv32):rnd", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34576,21 +29942,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vavguhrnd_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vavguh($Vu32,$Vv32):rnd", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vavgw : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vavg($Vu32.w,$Vv32.w)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -34600,22 +29954,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vavgw_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.w = vavg($Vu32.w,$Vv32.w)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vavgw_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vavgw($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34624,21 +29965,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vavgw_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vavgw($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vavgwrnd : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vavg($Vu32.w,$Vv32.w):rnd", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -34648,22 +29977,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vavgwrnd_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.w = vavg($Vu32.w,$Vv32.w):rnd", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vavgwrnd_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vavgw($Vu32,$Vv32):rnd", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34672,21 +29988,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vavgwrnd_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vavgw($Vu32,$Vv32):rnd", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vccombine : HInst< -(outs VecDblRegs:$Vdd32), -(ins PredRegs:$Ps4, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins PredRegs:$Ps4, HvxVR:$Vu32, HvxVR:$Vv32), "if ($Ps4) $Vdd32 = vcombine($Vu32,$Vv32)", tc_2171ebae, TypeCVI_VA_DV>, Enc_8c2412, Requires<[HasV60T,UseHVX]> { let Inst{7-7} = 0b0; @@ -34697,23 +30001,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vccombine_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins PredRegs:$Ps4, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"if ($Ps4) $Vdd32 = vcombine($Vu32,$Vv32)", -tc_2171ebae, TypeCVI_VA_DV>, Enc_8c2412, Requires<[HasV60T,UseHVX]> { -let Inst{7-7} = 0b0; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011010011; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vcl0h : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32.uh = vcl0($Vu32.uh)", tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -34723,22 +30013,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vcl0h_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32.uh = vcl0($Vu32.uh)", -tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vcl0h_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32 = vcl0h($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34747,21 +30024,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vcl0h_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32 = vcl0h($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vcl0w : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32.uw = vcl0($Vu32.uw)", tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -34771,22 +30036,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vcl0w_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32.uw = vcl0($Vu32.uw)", -tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vcl0w_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32 = vcl0w($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34795,21 +30047,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vcl0w_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32 = vcl0w($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vcmov : HInst< -(outs VectorRegs:$Vd32), -(ins PredRegs:$Ps4, VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins PredRegs:$Ps4, HvxVR:$Vu32), "if ($Ps4) $Vd32 = $Vu32", tc_b06ab583, TypeCVI_VA>, Enc_770858, Requires<[HasV60T,UseHVX]> { let Inst{7-7} = 0b0; @@ -34820,23 +30060,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vcmov_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Ps4, VectorRegs128B:$Vu32), -"if ($Ps4) $Vd32 = $Vu32", -tc_b06ab583, TypeCVI_VA>, Enc_770858, Requires<[HasV60T,UseHVX]> { -let Inst{7-7} = 0b0; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001101000000000; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vcombine : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vcombine($Vu32,$Vv32)", tc_97c165b9, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -34847,22 +30073,8 @@ let opNewValue = 0; let isRegSequence = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vcombine_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32 = vcombine($Vu32,$Vv32)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111010; -let hasNewValue = 1; -let opNewValue = 0; -let isRegSequence = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vd0 : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins), "$Vd32 = #0", CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { @@ -34872,21 +30084,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vd0_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins), -"$Vd32 = #0", -CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vdeal : HInst< -(outs VectorRegs:$Vy32, VectorRegs:$Vx32), -(ins VectorRegs:$Vy32in, VectorRegs:$Vx32in, IntRegs:$Rt32), +(outs HvxVR:$Vy32, HvxVR:$Vx32), +(ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32), "vdeal($Vy32,$Vx32,$Rt32)", tc_5c120602, TypeCVI_VP_VS>, Enc_989021, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -34899,25 +30099,9 @@ let opNewValue2 = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; } -def V6_vdeal_128B : HInst< -(outs VectorRegs128B:$Vy32, VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vy32in, VectorRegs128B:$Vx32in, IntRegs:$Rt32), -"vdeal($Vy32,$Vx32,$Rt32)", -tc_5c120602, TypeCVI_VP_VS>, Enc_989021, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001111; -let hasNewValue = 1; -let opNewValue = 0; -let hasNewValue2 = 1; -let opNewValue2 = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; -} def V6_vdealb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32.b = vdeal($Vu32.b)", tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -34928,8 +30112,8 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } def V6_vdealb4w : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vdeale($Vu32.b,$Vv32.b)", tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -34939,22 +30123,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdealb4w_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.b = vdeale($Vu32.b,$Vv32.b)", -tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vdealb4w_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vdealb4w($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34963,34 +30134,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdealb4w_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vdealb4w($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} -def V6_vdealb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32.b = vdeal($Vu32.b)", -tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vdealb_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32 = vdealb($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34999,21 +30145,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdealb_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32 = vdealb($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vdealh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32.h = vdeal($Vu32.h)", tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -35023,22 +30157,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdealh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32.h = vdeal($Vu32.h)", -tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vdealh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32 = vdealh($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35047,21 +30168,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdealh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32 = vdealh($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vdealvdd : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vdd32 = vdeal($Vu32,$Vv32,$Rt8)", tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -35071,22 +30180,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdealvdd_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), -"$Vdd32 = vdeal($Vu32,$Vv32,$Rt8)", -tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b1; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vdelta : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vdelta($Vu32,$Vv32)", tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -35096,22 +30192,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdelta_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vdelta($Vu32,$Vv32)", -tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vdmpybus : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.h = vdmpy($Vu32.ub,$Rt32.b)", tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -35121,22 +30204,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdmpybus_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32.h = vdmpy($Vu32.ub,$Rt32.b)", -tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vdmpybus_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.h += vdmpy($Vu32.ub,$Rt32.b)", tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -35148,24 +30218,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vdmpybus_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vx32.h += vdmpy($Vu32.ub,$Rt32.b)", -tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vdmpybus_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vdmpybus($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35176,23 +30231,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vdmpybus_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vx32 += vdmpybus($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vdmpybus_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vdmpybus($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35201,21 +30242,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdmpybus_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32 = vdmpybus($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vdmpybus_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32.h = vdmpy($Vuu32.ub,$Rt32.b)", tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -35225,22 +30254,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdmpybus_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vdd32.h = vdmpy($Vuu32.ub,$Rt32.b)", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vdmpybus_dv_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32.h += vdmpy($Vuu32.ub,$Rt32.b)", tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -35252,24 +30268,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vdmpybus_dv_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vxx32.h += vdmpy($Vuu32.ub,$Rt32.b)", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vdmpybus_dv_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32 += vdmpybus($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35280,23 +30281,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vdmpybus_dv_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vxx32 += vdmpybus($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vdmpybus_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32 = vdmpybus($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35305,21 +30292,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdmpybus_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vdd32 = vdmpybus($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vdmpyhb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.w = vdmpy($Vu32.h,$Rt32.b)", tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -35329,22 +30304,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdmpyhb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32.w = vdmpy($Vu32.h,$Rt32.b)", -tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vdmpyhb_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.w += vdmpy($Vu32.h,$Rt32.b)", tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -35356,24 +30318,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vdmpyhb_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vx32.w += vdmpy($Vu32.h,$Rt32.b)", -tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vdmpyhb_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vdmpyhb($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35384,23 +30331,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vdmpyhb_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vx32 += vdmpyhb($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vdmpyhb_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vdmpyhb($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35409,21 +30342,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdmpyhb_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32 = vdmpyhb($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vdmpyhb_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32.w = vdmpy($Vuu32.h,$Rt32.b)", tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -35433,22 +30354,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdmpyhb_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vdd32.w = vdmpy($Vuu32.h,$Rt32.b)", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vdmpyhb_dv_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32.w += vdmpy($Vuu32.h,$Rt32.b)", tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -35460,24 +30368,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vdmpyhb_dv_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vxx32.w += vdmpy($Vuu32.h,$Rt32.b)", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vdmpyhb_dv_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32 += vdmpyhb($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35488,23 +30381,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vdmpyhb_dv_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vxx32 += vdmpyhb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vdmpyhb_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32 = vdmpyhb($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35513,21 +30392,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdmpyhb_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vdd32 = vdmpyhb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vdmpyhisat : HInst< -(outs VectorRegs:$Vd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vd32.w = vdmpy($Vuu32.h,$Rt32.h):sat", tc_7c3f55c4, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -35537,22 +30404,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdmpyhisat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vd32.w = vdmpy($Vuu32.h,$Rt32.h):sat", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vdmpyhisat_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vx32.w += vdmpy($Vuu32.h,$Rt32.h):sat", tc_d98f4d63, TypeCVI_VX_DV>, Enc_cc857d, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -35564,24 +30418,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vdmpyhisat_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vx32.w += vdmpy($Vuu32.h,$Rt32.h):sat", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_cc857d, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vdmpyhisat_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vx32 += vdmpyh($Vuu32,$Rt32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35592,23 +30431,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vdmpyhisat_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vx32 += vdmpyh($Vuu32,$Rt32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vdmpyhisat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vd32 = vdmpyh($Vuu32,$Rt32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35617,21 +30442,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdmpyhisat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vd32 = vdmpyh($Vuu32,$Rt32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vdmpyhsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.w = vdmpy($Vu32.h,$Rt32.h):sat", tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -35641,22 +30454,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdmpyhsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32.w = vdmpy($Vu32.h,$Rt32.h):sat", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vdmpyhsat_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.w += vdmpy($Vu32.h,$Rt32.h):sat", tc_d98f4d63, TypeCVI_VX_DV>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -35668,24 +30468,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vdmpyhsat_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vx32.w += vdmpy($Vu32.h,$Rt32.h):sat", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vdmpyhsat_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vdmpyh($Vu32,$Rt32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35696,23 +30481,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vdmpyhsat_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vx32 += vdmpyh($Vu32,$Rt32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vdmpyhsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vdmpyh($Vu32,$Rt32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35721,21 +30492,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdmpyhsat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32 = vdmpyh($Vu32,$Rt32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vdmpyhsuisat : HInst< -(outs VectorRegs:$Vd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vd32.w = vdmpy($Vuu32.h,$Rt32.uh,#1):sat", tc_7c3f55c4, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -35745,22 +30504,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdmpyhsuisat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vd32.w = vdmpy($Vuu32.h,$Rt32.uh,#1):sat", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vdmpyhsuisat_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vx32.w += vdmpy($Vuu32.h,$Rt32.uh,#1):sat", tc_d98f4d63, TypeCVI_VX_DV>, Enc_cc857d, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -35772,24 +30518,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vdmpyhsuisat_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vx32.w += vdmpy($Vuu32.h,$Rt32.uh,#1):sat", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_cc857d, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vdmpyhsuisat_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vx32 += vdmpyhsu($Vuu32,$Rt32,#1):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35800,23 +30531,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vdmpyhsuisat_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vx32 += vdmpyhsu($Vuu32,$Rt32,#1):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vdmpyhsuisat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vd32 = vdmpyhsu($Vuu32,$Rt32,#1):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35825,21 +30542,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdmpyhsuisat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vd32 = vdmpyhsu($Vuu32,$Rt32,#1):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vdmpyhsusat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.w = vdmpy($Vu32.h,$Rt32.uh):sat", tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -35849,22 +30554,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdmpyhsusat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32.w = vdmpy($Vu32.h,$Rt32.uh):sat", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vdmpyhsusat_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.w += vdmpy($Vu32.h,$Rt32.uh):sat", tc_d98f4d63, TypeCVI_VX_DV>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -35876,24 +30568,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vdmpyhsusat_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vx32.w += vdmpy($Vu32.h,$Rt32.uh):sat", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vdmpyhsusat_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vdmpyhsu($Vu32,$Rt32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35904,23 +30581,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vdmpyhsusat_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vx32 += vdmpyhsu($Vu32,$Rt32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vdmpyhsusat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vdmpyhsu($Vu32,$Rt32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35929,21 +30592,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdmpyhsusat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32 = vdmpyhsu($Vu32,$Rt32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vdmpyhvsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vdmpy($Vu32.h,$Vv32.h):sat", tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -35953,22 +30604,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdmpyhvsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.w = vdmpy($Vu32.h,$Vv32.h):sat", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vdmpyhvsat_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32.w += vdmpy($Vu32.h,$Vv32.h):sat", tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -35980,24 +30618,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vdmpyhvsat_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vx32.w += vdmpy($Vu32.h,$Vv32.h):sat", -tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vdmpyhvsat_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32 += vdmpyh($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -36008,23 +30631,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vdmpyhvsat_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vx32 += vdmpyh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vdmpyhvsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vdmpyh($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -36033,21 +30642,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdmpyhvsat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vdmpyh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vdsaduh : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32.uw = vdsad($Vuu32.uh,$Rt32.uh)", tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -36057,22 +30654,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdsaduh_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vdd32.uw = vdsad($Vuu32.uh,$Rt32.uh)", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vdsaduh_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32.uw += vdsad($Vuu32.uh,$Rt32.uh)", tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -36084,24 +30668,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vdsaduh_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vxx32.uw += vdsad($Vuu32.uh,$Rt32.uh)", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001011; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vdsaduh_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32 += vdsaduh($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -36112,23 +30681,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vdsaduh_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vxx32 += vdsaduh($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vdsaduh_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32 = vdsaduh($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -36137,21 +30692,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdsaduh_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vdd32 = vdsaduh($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_veqb : HInst< -(outs VecPredRegs:$Qd4), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qd4), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.eq($Vu32.b,$Vv32.b)", tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000000; @@ -36161,22 +30704,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_veqb_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qd4 = vcmp.eq($Vu32.b,$Vv32.b)", -tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_veqb_and : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.eq($Vu32.b,$Vv32.b)", tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000000; @@ -36187,23 +30717,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_veqb_and_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 &= vcmp.eq($Vu32.b,$Vv32.b)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_veqb_or : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.eq($Vu32.b,$Vv32.b)", tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b010000; @@ -36215,24 +30731,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_veqb_or_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 |= vcmp.eq($Vu32.b,$Vv32.b)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b010000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_veqb_xor : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.eq($Vu32.b,$Vv32.b)", tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b100000; @@ -36243,23 +30744,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_veqb_xor_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 ^= vcmp.eq($Vu32.b,$Vv32.b)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b100000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_veqh : HInst< -(outs VecPredRegs:$Qd4), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qd4), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.eq($Vu32.h,$Vv32.h)", tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000001; @@ -36269,22 +30756,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_veqh_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qd4 = vcmp.eq($Vu32.h,$Vv32.h)", -tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_veqh_and : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.eq($Vu32.h,$Vv32.h)", tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000001; @@ -36295,23 +30769,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_veqh_and_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 &= vcmp.eq($Vu32.h,$Vv32.h)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000001; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_veqh_or : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.eq($Vu32.h,$Vv32.h)", tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b010001; @@ -36323,24 +30783,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_veqh_or_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 |= vcmp.eq($Vu32.h,$Vv32.h)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b010001; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_veqh_xor : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.eq($Vu32.h,$Vv32.h)", tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b100001; @@ -36351,23 +30796,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_veqh_xor_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 ^= vcmp.eq($Vu32.h,$Vv32.h)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b100001; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_veqw : HInst< -(outs VecPredRegs:$Qd4), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qd4), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.eq($Vu32.w,$Vv32.w)", tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000010; @@ -36377,22 +30808,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_veqw_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qd4 = vcmp.eq($Vu32.w,$Vv32.w)", -tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_veqw_and : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.eq($Vu32.w,$Vv32.w)", tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000010; @@ -36403,23 +30821,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_veqw_and_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 &= vcmp.eq($Vu32.w,$Vv32.w)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000010; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_veqw_or : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.eq($Vu32.w,$Vv32.w)", tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b010010; @@ -36431,24 +30835,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_veqw_or_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 |= vcmp.eq($Vu32.w,$Vv32.w)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b010010; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_veqw_xor : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.eq($Vu32.w,$Vv32.w)", tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b100010; @@ -36459,23 +30848,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_veqw_xor_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 ^= vcmp.eq($Vu32.w,$Vv32.w)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b100010; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_vgtb : HInst< -(outs VecPredRegs:$Qd4), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qd4), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.gt($Vu32.b,$Vv32.b)", tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000100; @@ -36485,22 +30860,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vgtb_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qd4 = vcmp.gt($Vu32.b,$Vv32.b)", -tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vgtb_and : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.gt($Vu32.b,$Vv32.b)", tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000100; @@ -36511,23 +30873,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vgtb_and_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 &= vcmp.gt($Vu32.b,$Vv32.b)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000100; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_vgtb_or : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.gt($Vu32.b,$Vv32.b)", tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b010100; @@ -36539,24 +30887,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vgtb_or_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 |= vcmp.gt($Vu32.b,$Vv32.b)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b010100; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_vgtb_xor : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.gt($Vu32.b,$Vv32.b)", tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b100100; @@ -36567,23 +30900,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vgtb_xor_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 ^= vcmp.gt($Vu32.b,$Vv32.b)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b100100; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_vgth : HInst< -(outs VecPredRegs:$Qd4), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qd4), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.gt($Vu32.h,$Vv32.h)", tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000101; @@ -36593,22 +30912,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vgth_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qd4 = vcmp.gt($Vu32.h,$Vv32.h)", -tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vgth_and : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.gt($Vu32.h,$Vv32.h)", tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000101; @@ -36619,23 +30925,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vgth_and_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 &= vcmp.gt($Vu32.h,$Vv32.h)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000101; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_vgth_or : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.gt($Vu32.h,$Vv32.h)", tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b010101; @@ -36647,24 +30939,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vgth_or_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 |= vcmp.gt($Vu32.h,$Vv32.h)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b010101; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_vgth_xor : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.gt($Vu32.h,$Vv32.h)", tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b100101; @@ -36675,23 +30952,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vgth_xor_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 ^= vcmp.gt($Vu32.h,$Vv32.h)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b100101; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_vgtub : HInst< -(outs VecPredRegs:$Qd4), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qd4), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.gt($Vu32.ub,$Vv32.ub)", tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b001000; @@ -36701,22 +30964,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vgtub_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qd4 = vcmp.gt($Vu32.ub,$Vv32.ub)", -tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b001000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vgtub_and : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.gt($Vu32.ub,$Vv32.ub)", tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b001000; @@ -36727,23 +30977,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vgtub_and_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 &= vcmp.gt($Vu32.ub,$Vv32.ub)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b001000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_vgtub_or : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.gt($Vu32.ub,$Vv32.ub)", tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b011000; @@ -36755,24 +30991,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vgtub_or_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 |= vcmp.gt($Vu32.ub,$Vv32.ub)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b011000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_vgtub_xor : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.gt($Vu32.ub,$Vv32.ub)", tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b101000; @@ -36783,23 +31004,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vgtub_xor_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 ^= vcmp.gt($Vu32.ub,$Vv32.ub)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b101000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_vgtuh : HInst< -(outs VecPredRegs:$Qd4), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qd4), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.gt($Vu32.uh,$Vv32.uh)", tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b001001; @@ -36809,22 +31016,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vgtuh_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qd4 = vcmp.gt($Vu32.uh,$Vv32.uh)", -tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b001001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vgtuh_and : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.gt($Vu32.uh,$Vv32.uh)", tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b001001; @@ -36835,23 +31029,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vgtuh_and_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 &= vcmp.gt($Vu32.uh,$Vv32.uh)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b001001; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_vgtuh_or : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.gt($Vu32.uh,$Vv32.uh)", tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b011001; @@ -36863,24 +31043,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vgtuh_or_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 |= vcmp.gt($Vu32.uh,$Vv32.uh)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b011001; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_vgtuh_xor : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.gt($Vu32.uh,$Vv32.uh)", tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b101001; @@ -36891,23 +31056,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vgtuh_xor_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 ^= vcmp.gt($Vu32.uh,$Vv32.uh)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b101001; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_vgtuw : HInst< -(outs VecPredRegs:$Qd4), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qd4), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.gt($Vu32.uw,$Vv32.uw)", tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b001010; @@ -36917,22 +31068,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vgtuw_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qd4 = vcmp.gt($Vu32.uw,$Vv32.uw)", -tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b001010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vgtuw_and : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.gt($Vu32.uw,$Vv32.uw)", tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b001010; @@ -36943,23 +31081,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vgtuw_and_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 &= vcmp.gt($Vu32.uw,$Vv32.uw)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b001010; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_vgtuw_or : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.gt($Vu32.uw,$Vv32.uw)", tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b011010; @@ -36971,24 +31095,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vgtuw_or_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 |= vcmp.gt($Vu32.uw,$Vv32.uw)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b011010; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_vgtuw_xor : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.gt($Vu32.uw,$Vv32.uw)", tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b101010; @@ -36999,23 +31108,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vgtuw_xor_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 ^= vcmp.gt($Vu32.uw,$Vv32.uw)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b101010; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_vgtw : HInst< -(outs VecPredRegs:$Qd4), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qd4), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.gt($Vu32.w,$Vv32.w)", tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000110; @@ -37025,22 +31120,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vgtw_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qd4 = vcmp.gt($Vu32.w,$Vv32.w)", -tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vgtw_and : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.gt($Vu32.w,$Vv32.w)", tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000110; @@ -37051,23 +31133,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vgtw_and_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 &= vcmp.gt($Vu32.w,$Vv32.w)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000110; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_vgtw_or : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.gt($Vu32.w,$Vv32.w)", tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b010110; @@ -37079,24 +31147,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vgtw_or_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 |= vcmp.gt($Vu32.w,$Vv32.w)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b010110; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_vgtw_xor : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.gt($Vu32.w,$Vv32.w)", tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b100110; @@ -37107,20 +31160,6 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vgtw_xor_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 ^= vcmp.gt($Vu32.w,$Vv32.w)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b100110; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_vhist : HInst< (outs), (ins), @@ -37130,19 +31169,9 @@ let Inst{13-0} = 0b10000010000000; let Inst{31-16} = 0b0001111000000000; let DecoderNamespace = "EXT_mmvec"; } -def V6_vhist_128B : HInst< -(outs), -(ins), -"vhist", -tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[HasV60T,UseHVX]> { -let Inst{13-0} = 0b10000010000000; -let Inst{31-16} = 0b0001111000000000; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vhistq : HInst< (outs), -(ins VecPredRegs:$Qv4), +(ins HvxQR:$Qv4), "vhist($Qv4)", tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[HasV60T,UseHVX]> { let Inst{13-0} = 0b10000010000000; @@ -37150,20 +31179,9 @@ let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; let DecoderNamespace = "EXT_mmvec"; } -def V6_vhistq_128B : HInst< -(outs), -(ins VecPredRegs128B:$Qv4), -"vhist($Qv4)", -tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[HasV60T,UseHVX]> { -let Inst{13-0} = 0b10000010000000; -let Inst{21-16} = 0b000010; -let Inst{31-24} = 0b00011110; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vinsertwr : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, IntRegs:$Rt32), "$Vx32.w = vinsert($Rt32)", tc_e231aa4f, TypeCVI_VX_LATE>, Enc_569cfe, Requires<[HasV60T,UseHVX]> { let Inst{13-5} = 0b100000001; @@ -37173,22 +31191,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vinsertwr_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, IntRegs:$Rt32), -"$Vx32.w = vinsert($Rt32)", -tc_e231aa4f, TypeCVI_VX_LATE>, Enc_569cfe, Requires<[HasV60T,UseHVX]> { -let Inst{13-5} = 0b100000001; -let Inst{31-21} = 0b00011001101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vlalignb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32 = vlalign($Vu32,$Vv32,$Rt8)", tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -37198,22 +31203,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vlalignb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), -"$Vd32 = vlalign($Vu32,$Vv32,$Rt8)", -tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vlalignbi : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, u3_0Imm:$Ii), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii), "$Vd32 = vlalign($Vu32,$Vv32,#$Ii)", tc_c4b515c5, TypeCVI_VP>, Enc_0b2e5b, Requires<[HasV60T,UseHVX]> { let Inst{13-13} = 0b1; @@ -37222,21 +31214,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vlalignbi_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, u3_0Imm:$Ii), -"$Vd32 = vlalign($Vu32,$Vv32,#$Ii)", -tc_c4b515c5, TypeCVI_VP>, Enc_0b2e5b, Requires<[HasV60T,UseHVX]> { -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011110011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vlsrb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.ub = vlsr($Vu32.ub,$Rt32)", tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b011; @@ -37246,22 +31226,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vlsrb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32.ub = vlsr($Vu32.ub,$Rt32)", -tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vlsrh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.uh = vlsr($Vu32.uh,$Rt32)", tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -37271,22 +31238,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vlsrh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32.uh = vlsr($Vu32.uh,$Rt32)", -tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vlsrh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vlsrh($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -37295,21 +31249,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vlsrh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32 = vlsrh($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vlsrhv : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vlsr($Vu32.h,$Vv32.h)", tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -37319,22 +31261,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vlsrhv_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.h = vlsr($Vu32.h,$Vv32.h)", -tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vlsrhv_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vlsrh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -37343,21 +31272,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vlsrhv_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vlsrh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vlsrw : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.uw = vlsr($Vu32.uw,$Rt32)", tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -37367,22 +31284,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vlsrw_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32.uw = vlsr($Vu32.uw,$Rt32)", -tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vlsrw_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vlsrw($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -37391,21 +31295,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vlsrw_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32 = vlsrw($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vlsrwv : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vlsr($Vu32.w,$Vv32.w)", tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -37415,22 +31307,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vlsrwv_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.w = vlsr($Vu32.w,$Vv32.w)", -tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vlsrwv_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vlsrw($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -37439,21 +31318,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vlsrwv_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vlsrw($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vlutvvb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8)", tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -37463,22 +31330,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vlutvvb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), -"$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8)", -tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b1; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vlutvvb_nm : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8):nomatch", tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b011; @@ -37488,22 +31342,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vlutvvb_nm_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), -"$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8):nomatch", -tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-24} = 0b00011000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vlutvvb_oracc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vx32.b |= vlut32($Vu32.b,$Vv32.b,$Rt8)", tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_245865, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -37515,24 +31356,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vlutvvb_oracc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), -"$Vx32.b |= vlut32($Vu32.b,$Vv32.b,$Rt8)", -tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_245865, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b1; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vlutvvb_oracci : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32, u3_0Imm:$Ii), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii), "$Vx32.b |= vlut32($Vu32.b,$Vv32.b,#$Ii)", tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_cd4705, Requires<[HasV62T,UseHVX]> { let Inst{13-13} = 0b1; @@ -37543,23 +31369,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vlutvvb_oracci_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, u3_0Imm:$Ii), -"$Vx32.b |= vlut32($Vu32.b,$Vv32.b,#$Ii)", -tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_cd4705, Requires<[HasV62T,UseHVX]> { -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100110; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vlutvvbi : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, u3_0Imm:$Ii), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii), "$Vd32.b = vlut32($Vu32.b,$Vv32.b,#$Ii)", tc_c4b515c5, TypeCVI_VP>, Enc_0b2e5b, Requires<[HasV62T,UseHVX]> { let Inst{13-13} = 0b0; @@ -37568,21 +31380,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vlutvvbi_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, u3_0Imm:$Ii), -"$Vd32.b = vlut32($Vu32.b,$Vv32.b,#$Ii)", -tc_c4b515c5, TypeCVI_VP>, Enc_0b2e5b, Requires<[HasV62T,UseHVX]> { -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011110001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vlutvwh : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8)", tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -37592,22 +31392,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vlutvwh_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), -"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8)", -tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b1; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vlutvwh_nm : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8):nomatch", tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b100; @@ -37617,22 +31404,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vlutvwh_nm_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), -"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8):nomatch", -tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-24} = 0b00011000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vlutvwh_oracc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,$Rt8)", tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_7b523d, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -37644,24 +31418,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vlutvwh_oracc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), -"$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,$Rt8)", -tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_7b523d, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b1; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vlutvwh_oracci : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32, u3_0Imm:$Ii), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii), "$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,#$Ii)", tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_1178da, Requires<[HasV62T,UseHVX]> { let Inst{13-13} = 0b1; @@ -37672,23 +31431,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vlutvwh_oracci_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, u3_0Imm:$Ii), -"$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,#$Ii)", -tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_1178da, Requires<[HasV62T,UseHVX]> { -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100111; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vlutvwhi : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, u3_0Imm:$Ii), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii), "$Vdd32.h = vlut16($Vu32.b,$Vv32.h,#$Ii)", tc_4e2a5159, TypeCVI_VP_VS>, Enc_4b39e4, Requires<[HasV62T,UseHVX]> { let Inst{13-13} = 0b0; @@ -37697,21 +31442,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vlutvwhi_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, u3_0Imm:$Ii), -"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,#$Ii)", -tc_4e2a5159, TypeCVI_VP_VS>, Enc_4b39e4, Requires<[HasV62T,UseHVX]> { -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011110011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmaxb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vmax($Vu32.b,$Vv32.b)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b101; @@ -37721,22 +31454,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmaxb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.b = vmax($Vu32.b,$Vv32.b)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmaxb_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmaxb($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -37745,21 +31465,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmaxb_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vmaxb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmaxh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vmax($Vu32.h,$Vv32.h)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -37769,22 +31477,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmaxh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.h = vmax($Vu32.h,$Vv32.h)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmaxh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmaxh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -37793,21 +31488,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmaxh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vmaxh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmaxub : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vmax($Vu32.ub,$Vv32.ub)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -37817,22 +31500,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmaxub_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.ub = vmax($Vu32.ub,$Vv32.ub)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmaxub_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmaxub($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -37841,21 +31511,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmaxub_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vmaxub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmaxuh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vmax($Vu32.uh,$Vv32.uh)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -37865,22 +31523,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmaxuh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.uh = vmax($Vu32.uh,$Vv32.uh)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmaxuh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmaxuh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -37889,21 +31534,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmaxuh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vmaxuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmaxw : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vmax($Vu32.w,$Vv32.w)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -37913,22 +31546,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmaxw_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.w = vmax($Vu32.w,$Vv32.w)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmaxw_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmaxw($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -37937,21 +31557,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmaxw_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vmaxw($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vminb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vmin($Vu32.b,$Vv32.b)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b100; @@ -37961,22 +31569,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vminb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.b = vmin($Vu32.b,$Vv32.b)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vminb_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vminb($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -37985,21 +31580,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vminb_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vminb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vminh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vmin($Vu32.h,$Vv32.h)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -38009,22 +31592,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vminh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.h = vmin($Vu32.h,$Vv32.h)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vminh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vminh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38033,21 +31603,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vminh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vminh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vminub : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vmin($Vu32.ub,$Vv32.ub)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -38057,22 +31615,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vminub_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.ub = vmin($Vu32.ub,$Vv32.ub)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vminub_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vminub($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38081,21 +31626,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vminub_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vminub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vminuh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vmin($Vu32.uh,$Vv32.uh)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -38105,22 +31638,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vminuh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.uh = vmin($Vu32.uh,$Vv32.uh)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vminuh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vminuh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38129,21 +31649,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vminuh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vminuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vminw : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vmin($Vu32.w,$Vv32.w)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -38153,22 +31661,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vminw_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.w = vmin($Vu32.w,$Vv32.w)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vminw_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vminw($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38177,21 +31672,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vminw_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vminw($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpabus : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32.h = vmpa($Vuu32.ub,$Rt32.b)", tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -38201,22 +31684,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpabus_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vdd32.h = vmpa($Vuu32.ub,$Rt32.b)", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpabus_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32.h += vmpa($Vuu32.ub,$Rt32.b)", tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -38228,24 +31698,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vmpabus_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vxx32.h += vmpa($Vuu32.ub,$Rt32.b)", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vmpabus_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32 += vmpabus($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38256,23 +31711,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vmpabus_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vxx32 += vmpabus($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vmpabus_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32 = vmpabus($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38281,21 +31722,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpabus_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vdd32 = vmpabus($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpabusv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.b)", tc_eda67dcd, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -38305,22 +31734,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpabusv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.b)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpabusv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vmpabus($Vuu32,$Vvv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38329,21 +31745,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpabusv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32 = vmpabus($Vuu32,$Vvv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpabuuv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.ub)", tc_eda67dcd, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -38353,22 +31757,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpabuuv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.ub)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpabuuv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vmpabuu($Vuu32,$Vvv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38377,21 +31768,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpabuuv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32 = vmpabuu($Vuu32,$Vvv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpahb : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32.w = vmpa($Vuu32.h,$Rt32.b)", tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -38401,22 +31780,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpahb_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vdd32.w = vmpa($Vuu32.h,$Rt32.b)", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpahb_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32.w += vmpa($Vuu32.h,$Rt32.b)", tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -38428,24 +31794,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vmpahb_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vxx32.w += vmpa($Vuu32.h,$Rt32.b)", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vmpahb_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32 += vmpahb($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38456,23 +31807,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vmpahb_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vxx32 += vmpahb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vmpahb_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32 = vmpahb($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38481,21 +31818,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpahb_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vdd32 = vmpahb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpauhb : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32.w = vmpa($Vuu32.uh,$Rt32.b)", tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b101; @@ -38505,22 +31830,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpauhb_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vdd32.w = vmpa($Vuu32.uh,$Rt32.b)", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpauhb_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32.w += vmpa($Vuu32.uh,$Rt32.b)", tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b010; @@ -38532,24 +31844,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vmpauhb_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vxx32.w += vmpa($Vuu32.uh,$Rt32.b)", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001100; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vmpauhb_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32 += vmpauhb($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -38560,23 +31857,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vmpauhb_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vxx32 += vmpauhb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vmpauhb_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32 = vmpauhb($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -38585,21 +31868,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpauhb_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vdd32 = vmpauhb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpybus : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vdd32.h = vmpy($Vu32.ub,$Rt32.b)", tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -38609,22 +31880,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpybus_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vdd32.h = vmpy($Vu32.ub,$Rt32.b)", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpybus_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vxx32.h += vmpy($Vu32.ub,$Rt32.b)", tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -38636,24 +31894,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vmpybus_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vxx32.h += vmpy($Vu32.ub,$Rt32.b)", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vmpybus_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vxx32 += vmpybus($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38664,23 +31907,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vmpybus_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vxx32 += vmpybus($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vmpybus_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vdd32 = vmpybus($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38689,21 +31918,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpybus_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vdd32 = vmpybus($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpybusv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.h = vmpy($Vu32.ub,$Vv32.b)", tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -38713,22 +31930,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpybusv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32.h = vmpy($Vu32.ub,$Vv32.b)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpybusv_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32.h += vmpy($Vu32.ub,$Vv32.b)", tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -38740,24 +31944,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vmpybusv_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vxx32.h += vmpy($Vu32.ub,$Vv32.b)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vmpybusv_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32 += vmpybus($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38768,23 +31957,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vmpybusv_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vxx32 += vmpybus($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vmpybusv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vmpybus($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38793,21 +31968,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpybusv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32 = vmpybus($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpybv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.h = vmpy($Vu32.b,$Vv32.b)", tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -38817,22 +31980,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpybv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32.h = vmpy($Vu32.b,$Vv32.b)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpybv_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32.h += vmpy($Vu32.b,$Vv32.b)", tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -38844,24 +31994,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vmpybv_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vxx32.h += vmpy($Vu32.b,$Vv32.b)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vmpybv_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32 += vmpyb($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38872,23 +32007,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vmpybv_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vxx32 += vmpyb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vmpybv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vmpyb($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38897,21 +32018,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpybv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32 = vmpyb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyewuh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vmpye($Vu32.w,$Vv32.uh)", tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -38921,22 +32030,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyewuh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.w = vmpye($Vu32.w,$Vv32.uh)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyewuh_64 : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vmpye($Vu32.w,$Vv32.uh)", tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b110; @@ -38946,22 +32042,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyewuh_64_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32 = vmpye($Vu32.w,$Vv32.uh)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011110101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyewuh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmpyewuh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38970,21 +32053,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyewuh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vmpyewuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyh : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vdd32.w = vmpy($Vu32.h,$Rt32.h)", tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -38994,22 +32065,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyh_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vdd32.w = vmpy($Vu32.h,$Rt32.h)", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyh_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vdd32 = vmpyh($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39018,21 +32076,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyh_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vdd32 = vmpyh($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyhsat_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vxx32.w += vmpy($Vu32.h,$Rt32.h):sat", tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -39044,24 +32090,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vmpyhsat_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vxx32.w += vmpy($Vu32.h,$Rt32.h):sat", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001010; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vmpyhsat_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vxx32 += vmpyh($Vu32,$Rt32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39072,23 +32103,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vmpyhsat_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vxx32 += vmpyh($Vu32,$Rt32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vmpyhsrs : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:rnd:sat", tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -39098,22 +32115,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyhsrs_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:rnd:sat", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyhsrs_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vmpyh($Vu32,$Rt32):<<1:rnd:sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39122,21 +32126,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyhsrs_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32 = vmpyh($Vu32,$Rt32):<<1:rnd:sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyhss : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:sat", tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -39146,22 +32138,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyhss_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:sat", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyhss_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vmpyh($Vu32,$Rt32):<<1:sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39170,21 +32149,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyhss_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32 = vmpyh($Vu32,$Rt32):<<1:sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyhus : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.w = vmpy($Vu32.h,$Vv32.uh)", tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -39194,22 +32161,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyhus_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32.w = vmpy($Vu32.h,$Vv32.uh)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyhus_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32.w += vmpy($Vu32.h,$Vv32.uh)", tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -39221,24 +32175,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vmpyhus_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vxx32.w += vmpy($Vu32.h,$Vv32.uh)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vmpyhus_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32 += vmpyhus($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39249,23 +32188,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vmpyhus_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vxx32 += vmpyhus($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vmpyhus_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vmpyhus($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39274,21 +32199,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyhus_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32 = vmpyhus($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyhv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.w = vmpy($Vu32.h,$Vv32.h)", tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -39298,22 +32211,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyhv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32.w = vmpy($Vu32.h,$Vv32.h)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyhv_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32.w += vmpy($Vu32.h,$Vv32.h)", tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -39325,24 +32225,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vmpyhv_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vxx32.w += vmpy($Vu32.h,$Vv32.h)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vmpyhv_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32 += vmpyh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39353,23 +32238,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vmpyhv_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vxx32 += vmpyh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vmpyhv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vmpyh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39378,21 +32249,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyhv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32 = vmpyh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyhvsrs : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vmpy($Vu32.h,$Vv32.h):<<1:rnd:sat", tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -39402,22 +32261,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyhvsrs_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.h = vmpy($Vu32.h,$Vv32.h):<<1:rnd:sat", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyhvsrs_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmpyh($Vu32,$Vv32):<<1:rnd:sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39426,21 +32272,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyhvsrs_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vmpyh($Vu32,$Vv32):<<1:rnd:sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyieoh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vmpyieo($Vu32.h,$Vv32.h)", tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -39450,22 +32284,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyieoh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.w = vmpyieo($Vu32.h,$Vv32.h)", -tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyiewh_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32.w += vmpyie($Vu32.w,$Vv32.h)", tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -39477,24 +32298,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vmpyiewh_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vx32.w += vmpyie($Vu32.w,$Vv32.h)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100010; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vmpyiewh_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32 += vmpyiewh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39505,23 +32311,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vmpyiewh_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vx32 += vmpyiewh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vmpyiewuh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vmpyie($Vu32.w,$Vv32.uh)", tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -39531,22 +32323,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyiewuh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.w = vmpyie($Vu32.w,$Vv32.uh)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyiewuh_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32.w += vmpyie($Vu32.w,$Vv32.uh)", tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -39558,24 +32337,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vmpyiewuh_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vx32.w += vmpyie($Vu32.w,$Vv32.uh)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vmpyiewuh_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32 += vmpyiewuh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39586,23 +32350,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vmpyiewuh_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vx32 += vmpyiewuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vmpyiewuh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmpyiewuh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39611,21 +32361,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyiewuh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vmpyiewuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyih : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vmpyi($Vu32.h,$Vv32.h)", tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -39635,22 +32373,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyih_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.h = vmpyi($Vu32.h,$Vv32.h)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyih_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32.h += vmpyi($Vu32.h,$Vv32.h)", tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -39662,24 +32387,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vmpyih_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vx32.h += vmpyi($Vu32.h,$Vv32.h)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vmpyih_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32 += vmpyih($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39690,23 +32400,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vmpyih_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vx32 += vmpyih($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vmpyih_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmpyih($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39715,21 +32411,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyih_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vmpyih($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyihb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.h = vmpyi($Vu32.h,$Rt32.b)", tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -39739,22 +32423,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyihb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32.h = vmpyi($Vu32.h,$Rt32.b)", -tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyihb_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.h += vmpyi($Vu32.h,$Rt32.b)", tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -39766,24 +32437,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vmpyihb_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vx32.h += vmpyi($Vu32.h,$Rt32.b)", -tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001011; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vmpyihb_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vmpyihb($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39794,23 +32450,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vmpyihb_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vx32 += vmpyihb($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vmpyihb_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vmpyihb($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39819,21 +32461,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyihb_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32 = vmpyihb($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyiowh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vmpyio($Vu32.w,$Vv32.h)", tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -39843,22 +32473,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyiowh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.w = vmpyio($Vu32.w,$Vv32.h)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyiowh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmpyiowh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39867,21 +32484,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyiowh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vmpyiowh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyiwb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.w = vmpyi($Vu32.w,$Rt32.b)", tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -39891,22 +32496,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyiwb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32.w = vmpyi($Vu32.w,$Rt32.b)", -tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyiwb_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.w += vmpyi($Vu32.w,$Rt32.b)", tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -39918,24 +32510,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vmpyiwb_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vx32.w += vmpyi($Vu32.w,$Rt32.b)", -tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001010; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vmpyiwb_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vmpyiwb($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39946,23 +32523,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vmpyiwb_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vx32 += vmpyiwb($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vmpyiwb_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vmpyiwb($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39971,21 +32534,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyiwb_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32 = vmpyiwb($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyiwh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.w = vmpyi($Vu32.w,$Rt32.h)", tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -39995,22 +32546,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyiwh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32.w = vmpyi($Vu32.w,$Rt32.h)", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyiwh_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.w += vmpyi($Vu32.w,$Rt32.h)", tc_d98f4d63, TypeCVI_VX_DV>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -40022,24 +32560,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vmpyiwh_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vx32.w += vmpyi($Vu32.w,$Rt32.h)", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001010; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vmpyiwh_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vmpyiwh($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40050,23 +32573,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vmpyiwh_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vx32 += vmpyiwh($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vmpyiwh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vmpyiwh($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40075,21 +32584,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyiwh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32 = vmpyiwh($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyiwub : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.w = vmpyi($Vu32.w,$Rt32.ub)", tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b110; @@ -40099,22 +32596,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyiwub_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32.w = vmpyi($Vu32.w,$Rt32.ub)", -tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyiwub_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.w += vmpyi($Vu32.w,$Rt32.ub)", tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b001; @@ -40126,24 +32610,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vmpyiwub_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vx32.w += vmpyi($Vu32.w,$Rt32.ub)", -tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001100; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vmpyiwub_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vmpyiwub($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -40154,23 +32623,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vmpyiwub_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vx32 += vmpyiwub($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vmpyiwub_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vmpyiwub($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -40179,21 +32634,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyiwub_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32 = vmpyiwub($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyowh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:sat", tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -40203,22 +32646,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyowh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:sat", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyowh_64_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32 += vmpyo($Vu32.w,$Vv32.h)", tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b011; @@ -40230,24 +32660,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vmpyowh_64_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vxx32 += vmpyo($Vu32.w,$Vv32.h)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vmpyowh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmpyowh($Vu32,$Vv32):<<1:sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40256,21 +32671,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyowh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyowh_rnd : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat", tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -40280,22 +32683,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyowh_rnd_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyowh_rnd_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmpyowh($Vu32,$Vv32):<<1:rnd:sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40304,21 +32694,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyowh_rnd_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:rnd:sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyowh_rnd_sacc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat:shift", tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -40330,24 +32708,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vmpyowh_rnd_sacc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat:shift", -tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vmpyowh_rnd_sacc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32 += vmpyowh($Vu32,$Vv32):<<1:rnd:sat:shift", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40357,22 +32720,9 @@ let isPseudo = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vmpyowh_rnd_sacc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vx32 += vmpyowh($Vu32,$Vv32):<<1:rnd:sat:shift", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vmpyowh_sacc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:sat:shift", tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -40384,24 +32734,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vmpyowh_sacc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:sat:shift", -tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vmpyowh_sacc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32 += vmpyowh($Vu32,$Vv32):<<1:sat:shift", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40411,22 +32746,9 @@ let isPseudo = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vmpyowh_sacc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vx32 += vmpyowh($Vu32,$Vv32):<<1:sat:shift", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vmpyub : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vdd32.uh = vmpy($Vu32.ub,$Rt32.ub)", tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -40436,22 +32758,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyub_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vdd32.uh = vmpy($Vu32.ub,$Rt32.ub)", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyub_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vxx32.uh += vmpy($Vu32.ub,$Rt32.ub)", tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -40463,24 +32772,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vmpyub_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vxx32.uh += vmpy($Vu32.ub,$Rt32.ub)", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001100; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vmpyub_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vxx32 += vmpyub($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40491,23 +32785,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vmpyub_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vxx32 += vmpyub($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vmpyub_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vdd32 = vmpyub($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40516,21 +32796,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyub_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vdd32 = vmpyub($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyubv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.uh = vmpy($Vu32.ub,$Vv32.ub)", tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -40540,22 +32808,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyubv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32.uh = vmpy($Vu32.ub,$Vv32.ub)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyubv_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32.uh += vmpy($Vu32.ub,$Vv32.ub)", tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -40567,24 +32822,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vmpyubv_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vxx32.uh += vmpy($Vu32.ub,$Vv32.ub)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vmpyubv_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32 += vmpyub($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40595,23 +32835,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vmpyubv_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vxx32 += vmpyub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vmpyubv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vmpyub($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40620,21 +32846,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyubv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32 = vmpyub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyuh : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vdd32.uw = vmpy($Vu32.uh,$Rt32.uh)", tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -40644,22 +32858,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyuh_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vdd32.uw = vmpy($Vu32.uh,$Rt32.uh)", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyuh_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vxx32.uw += vmpy($Vu32.uh,$Rt32.uh)", tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -40671,24 +32872,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vmpyuh_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vxx32.uw += vmpy($Vu32.uh,$Rt32.uh)", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001010; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vmpyuh_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vxx32 += vmpyuh($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40699,23 +32885,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vmpyuh_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vxx32 += vmpyuh($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vmpyuh_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vdd32 = vmpyuh($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40724,21 +32896,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyuh_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vdd32 = vmpyuh($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyuhv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.uw = vmpy($Vu32.uh,$Vv32.uh)", tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -40748,22 +32908,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyuhv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32.uw = vmpy($Vu32.uh,$Vv32.uh)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyuhv_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32.uw += vmpy($Vu32.uh,$Vv32.uh)", tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -40775,24 +32922,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vmpyuhv_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vxx32.uw += vmpy($Vu32.uh,$Vv32.uh)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vmpyuhv_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32 += vmpyuh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40803,23 +32935,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vmpyuhv_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vxx32 += vmpyuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vmpyuhv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vmpyuh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40828,21 +32946,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyuhv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32 = vmpyuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmux : HInst< -(outs VectorRegs:$Vd32), -(ins VecPredRegs:$Qt4, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxQR:$Qt4, HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmux($Qt4,$Vu32,$Vv32)", tc_a3127e12, TypeCVI_VA>, Enc_31db33, Requires<[HasV60T,UseHVX]> { let Inst{7-7} = 0b0; @@ -40852,22 +32958,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmux_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VecPredRegs128B:$Qt4, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vmux($Qt4,$Vu32,$Vv32)", -tc_a3127e12, TypeCVI_VA>, Enc_31db33, Requires<[HasV60T,UseHVX]> { -let Inst{7-7} = 0b0; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011110111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vnavgh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vnavg($Vu32.h,$Vv32.h)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -40877,22 +32970,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vnavgh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.h = vnavg($Vu32.h,$Vv32.h)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vnavgh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vnavgh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40901,21 +32981,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vnavgh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vnavgh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vnavgub : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vnavg($Vu32.ub,$Vv32.ub)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -40925,22 +32993,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vnavgub_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.b = vnavg($Vu32.ub,$Vv32.ub)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vnavgub_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vnavgub($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40949,21 +33004,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vnavgub_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vnavgub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vnavgw : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vnavg($Vu32.w,$Vv32.w)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -40973,22 +33016,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vnavgw_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.w = vnavg($Vu32.w,$Vv32.w)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vnavgw_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vnavgw($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40997,21 +33027,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vnavgw_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vnavgw($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vnccombine : HInst< -(outs VecDblRegs:$Vdd32), -(ins PredRegs:$Ps4, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins PredRegs:$Ps4, HvxVR:$Vu32, HvxVR:$Vv32), "if (!$Ps4) $Vdd32 = vcombine($Vu32,$Vv32)", tc_2171ebae, TypeCVI_VA_DV>, Enc_8c2412, Requires<[HasV60T,UseHVX]> { let Inst{7-7} = 0b0; @@ -41023,24 +33041,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vnccombine_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins PredRegs:$Ps4, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"if (!$Ps4) $Vdd32 = vcombine($Vu32,$Vv32)", -tc_2171ebae, TypeCVI_VA_DV>, Enc_8c2412, Requires<[HasV60T,UseHVX]> { -let Inst{7-7} = 0b0; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011010010; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vncmov : HInst< -(outs VectorRegs:$Vd32), -(ins PredRegs:$Ps4, VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins PredRegs:$Ps4, HvxVR:$Vu32), "if (!$Ps4) $Vd32 = $Vu32", tc_b06ab583, TypeCVI_VA>, Enc_770858, Requires<[HasV60T,UseHVX]> { let Inst{7-7} = 0b0; @@ -41052,24 +33055,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vncmov_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Ps4, VectorRegs128B:$Vu32), -"if (!$Ps4) $Vd32 = $Vu32", -tc_b06ab583, TypeCVI_VA>, Enc_770858, Requires<[HasV60T,UseHVX]> { -let Inst{7-7} = 0b0; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001101000100000; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vnormamth : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32.h = vnormamt($Vu32.h)", tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -41079,22 +33067,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vnormamth_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32.h = vnormamt($Vu32.h)", -tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vnormamth_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32 = vnormamth($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41103,21 +33078,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vnormamth_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32 = vnormamth($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vnormamtw : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32.w = vnormamt($Vu32.w)", tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -41127,22 +33090,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vnormamtw_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32.w = vnormamt($Vu32.w)", -tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vnormamtw_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32 = vnormamtw($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41151,21 +33101,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vnormamtw_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32 = vnormamtw($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vnot : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32 = vnot($Vu32)", tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -41175,22 +33113,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vnot_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32 = vnot($Vu32)", -tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vor : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vor($Vu32,$Vv32)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -41200,22 +33125,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vor_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vor($Vu32,$Vv32)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vpackeb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vpacke($Vu32.h,$Vv32.h)", tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -41225,22 +33137,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vpackeb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.b = vpacke($Vu32.h,$Vv32.h)", -tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vpackeb_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vpackeb($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41249,21 +33148,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vpackeb_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vpackeb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vpackeh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vpacke($Vu32.w,$Vv32.w)", tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -41273,22 +33160,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vpackeh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.h = vpacke($Vu32.w,$Vv32.w)", -tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vpackeh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vpackeh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41297,21 +33171,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vpackeh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vpackeh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vpackhb_sat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vpack($Vu32.h,$Vv32.h):sat", tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -41321,22 +33183,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vpackhb_sat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.b = vpack($Vu32.h,$Vv32.h):sat", -tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vpackhb_sat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vpackhb($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41345,21 +33194,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vpackhb_sat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vpackhb($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vpackhub_sat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vpack($Vu32.h,$Vv32.h):sat", tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -41369,22 +33206,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vpackhub_sat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.ub = vpack($Vu32.h,$Vv32.h):sat", -tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vpackhub_sat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vpackhub($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41393,21 +33217,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vpackhub_sat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vpackhub($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vpackob : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vpacko($Vu32.h,$Vv32.h)", tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -41417,22 +33229,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vpackob_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.b = vpacko($Vu32.h,$Vv32.h)", -tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vpackob_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vpackob($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41441,21 +33240,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vpackob_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vpackob($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vpackoh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vpacko($Vu32.w,$Vv32.w)", tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -41465,22 +33252,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vpackoh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.h = vpacko($Vu32.w,$Vv32.w)", -tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vpackoh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vpackoh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41489,21 +33263,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vpackoh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vpackoh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vpackwh_sat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vpack($Vu32.w,$Vv32.w):sat", tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -41513,22 +33275,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vpackwh_sat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.h = vpack($Vu32.w,$Vv32.w):sat", -tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vpackwh_sat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vpackwh($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41537,21 +33286,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vpackwh_sat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vpackwh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vpackwuh_sat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vpack($Vu32.w,$Vv32.w):sat", tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -41561,22 +33298,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vpackwuh_sat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.uh = vpack($Vu32.w,$Vv32.w):sat", -tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vpackwuh_sat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vpackwuh($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41585,21 +33309,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vpackwuh_sat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vpackwuh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vpopcounth : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32.h = vpopcount($Vu32.h)", tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -41609,22 +33321,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vpopcounth_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32.h = vpopcount($Vu32.h)", -tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vpopcounth_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32 = vpopcounth($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41633,21 +33332,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vpopcounth_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32 = vpopcounth($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vrdelta : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vrdelta($Vu32,$Vv32)", tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -41657,22 +33344,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vrdelta_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vrdelta($Vu32,$Vv32)", -tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vrmpybus : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.w = vrmpy($Vu32.ub,$Rt32.b)", tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -41682,22 +33356,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vrmpybus_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32.w = vrmpy($Vu32.ub,$Rt32.b)", -tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vrmpybus_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.w += vrmpy($Vu32.ub,$Rt32.b)", tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -41709,24 +33370,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vrmpybus_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vx32.w += vrmpy($Vu32.ub,$Rt32.b)", -tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vrmpybus_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vrmpybus($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41737,23 +33383,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vrmpybus_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vx32 += vrmpybus($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vrmpybus_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vrmpybus($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41762,21 +33394,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vrmpybus_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32 = vrmpybus($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vrmpybusi : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vdd32.w = vrmpy($Vuu32.ub,$Rt32.b,#$Ii)", tc_7e9f581b, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[HasV60T,UseHVX]> { let Inst{7-6} = 0b10; @@ -41786,22 +33406,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vrmpybusi_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), -"$Vdd32.w = vrmpy($Vuu32.ub,$Rt32.b,#$Ii)", -tc_7e9f581b, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[HasV60T,UseHVX]> { -let Inst{7-6} = 0b10; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vrmpybusi_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vxx32.w += vrmpy($Vuu32.ub,$Rt32.b,#$Ii)", tc_41f99e1c, TypeCVI_VX_DV>, Enc_d483b9, Requires<[HasV60T,UseHVX]> { let Inst{7-6} = 0b10; @@ -41813,24 +33420,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vrmpybusi_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), -"$Vxx32.w += vrmpy($Vuu32.ub,$Rt32.b,#$Ii)", -tc_41f99e1c, TypeCVI_VX_DV>, Enc_d483b9, Requires<[HasV60T,UseHVX]> { -let Inst{7-6} = 0b10; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001010; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vrmpybusi_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vxx32 += vrmpybus($Vuu32,$Rt32,#$Ii)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41841,23 +33433,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vrmpybusi_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), -"$Vxx32 += vrmpybus($Vuu32,$Rt32,#$Ii)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vrmpybusi_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vdd32 = vrmpybus($Vuu32,$Rt32,#$Ii)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41866,21 +33444,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vrmpybusi_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), -"$Vdd32 = vrmpybus($Vuu32,$Rt32,#$Ii)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vrmpybusv : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vrmpy($Vu32.ub,$Vv32.b)", tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -41890,22 +33456,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vrmpybusv_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.w = vrmpy($Vu32.ub,$Vv32.b)", -tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vrmpybusv_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32.w += vrmpy($Vu32.ub,$Vv32.b)", tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -41917,24 +33470,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vrmpybusv_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vx32.w += vrmpy($Vu32.ub,$Vv32.b)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vrmpybusv_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32 += vrmpybus($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41945,23 +33483,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vrmpybusv_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vx32 += vrmpybus($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vrmpybusv_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vrmpybus($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41970,21 +33494,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vrmpybusv_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vrmpybus($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vrmpybv : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vrmpy($Vu32.b,$Vv32.b)", tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -41994,22 +33506,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vrmpybv_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.w = vrmpy($Vu32.b,$Vv32.b)", -tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vrmpybv_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32.w += vrmpy($Vu32.b,$Vv32.b)", tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -42021,24 +33520,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vrmpybv_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vx32.w += vrmpy($Vu32.b,$Vv32.b)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vrmpybv_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32 += vrmpyb($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42049,23 +33533,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vrmpybv_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vx32 += vrmpyb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vrmpybv_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vrmpyb($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42074,21 +33544,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vrmpybv_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vrmpyb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vrmpyub : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.uw = vrmpy($Vu32.ub,$Rt32.ub)", tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -42098,22 +33556,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vrmpyub_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32.uw = vrmpy($Vu32.ub,$Rt32.ub)", -tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vrmpyub_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.uw += vrmpy($Vu32.ub,$Rt32.ub)", tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -42125,24 +33570,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vrmpyub_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vx32.uw += vrmpy($Vu32.ub,$Rt32.ub)", -tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vrmpyub_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vrmpyub($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42153,23 +33583,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vrmpyub_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vx32 += vrmpyub($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vrmpyub_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vrmpyub($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42178,21 +33594,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vrmpyub_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32 = vrmpyub($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vrmpyubi : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vdd32.uw = vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)", tc_7e9f581b, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[HasV60T,UseHVX]> { let Inst{7-6} = 0b11; @@ -42202,22 +33606,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vrmpyubi_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), -"$Vdd32.uw = vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)", -tc_7e9f581b, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[HasV60T,UseHVX]> { -let Inst{7-6} = 0b11; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vrmpyubi_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vxx32.uw += vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)", tc_41f99e1c, TypeCVI_VX_DV>, Enc_d483b9, Requires<[HasV60T,UseHVX]> { let Inst{7-6} = 0b11; @@ -42229,24 +33620,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vrmpyubi_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), -"$Vxx32.uw += vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)", -tc_41f99e1c, TypeCVI_VX_DV>, Enc_d483b9, Requires<[HasV60T,UseHVX]> { -let Inst{7-6} = 0b11; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001011; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vrmpyubi_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vxx32 += vrmpyub($Vuu32,$Rt32,#$Ii)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42257,23 +33633,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vrmpyubi_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), -"$Vxx32 += vrmpyub($Vuu32,$Rt32,#$Ii)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vrmpyubi_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vdd32 = vrmpyub($Vuu32,$Rt32,#$Ii)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42282,21 +33644,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vrmpyubi_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), -"$Vdd32 = vrmpyub($Vuu32,$Rt32,#$Ii)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vrmpyubv : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uw = vrmpy($Vu32.ub,$Vv32.ub)", tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -42306,22 +33656,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vrmpyubv_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.uw = vrmpy($Vu32.ub,$Vv32.ub)", -tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vrmpyubv_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32.uw += vrmpy($Vu32.ub,$Vv32.ub)", tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -42333,24 +33670,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vrmpyubv_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vx32.uw += vrmpy($Vu32.ub,$Vv32.ub)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vrmpyubv_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32 += vrmpyub($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42361,23 +33683,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vrmpyubv_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vx32 += vrmpyub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vrmpyubv_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vrmpyub($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42386,21 +33694,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vrmpyubv_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vrmpyub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vror : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vror($Vu32,$Rt32)", tc_bf142ae2, TypeCVI_VP>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -42410,22 +33706,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vror_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32 = vror($Vu32,$Rt32)", -tc_bf142ae2, TypeCVI_VP>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vroundhb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vround($Vu32.h,$Vv32.h):sat", tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -42435,22 +33718,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vroundhb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.b = vround($Vu32.h,$Vv32.h):sat", -tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vroundhb_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vroundhb($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42459,21 +33729,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vroundhb_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vroundhb($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vroundhub : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vround($Vu32.h,$Vv32.h):sat", tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -42483,22 +33741,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vroundhub_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.ub = vround($Vu32.h,$Vv32.h):sat", -tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vroundhub_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vroundhub($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42507,21 +33752,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vroundhub_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vroundhub($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vrounduhub : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vround($Vu32.uh,$Vv32.uh):sat", tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b011; @@ -42531,22 +33764,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vrounduhub_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.ub = vround($Vu32.uh,$Vv32.uh):sat", -tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vrounduhub_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vrounduhub($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -42555,21 +33775,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vrounduhub_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vrounduhub($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vrounduwuh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vround($Vu32.uw,$Vv32.uw):sat", tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b100; @@ -42579,22 +33787,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vrounduwuh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.uh = vround($Vu32.uw,$Vv32.uw):sat", -tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vrounduwuh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vrounduwuh($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -42603,21 +33798,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vrounduwuh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vrounduwuh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vroundwh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vround($Vu32.w,$Vv32.w):sat", tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -42627,22 +33810,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vroundwh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.h = vround($Vu32.w,$Vv32.w):sat", -tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vroundwh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vroundwh($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42651,21 +33821,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vroundwh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vroundwh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vroundwuh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vround($Vu32.w,$Vv32.w):sat", tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -42675,22 +33833,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vroundwuh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.uh = vround($Vu32.w,$Vv32.w):sat", -tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vroundwuh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vroundwuh($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42699,21 +33844,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vroundwuh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vroundwuh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vrsadubi : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vdd32.uw = vrsad($Vuu32.ub,$Rt32.ub,#$Ii)", tc_7e9f581b, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[HasV60T,UseHVX]> { let Inst{7-6} = 0b11; @@ -42723,22 +33856,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vrsadubi_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), -"$Vdd32.uw = vrsad($Vuu32.ub,$Rt32.ub,#$Ii)", -tc_7e9f581b, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[HasV60T,UseHVX]> { -let Inst{7-6} = 0b11; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vrsadubi_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vxx32.uw += vrsad($Vuu32.ub,$Rt32.ub,#$Ii)", tc_41f99e1c, TypeCVI_VX_DV>, Enc_d483b9, Requires<[HasV60T,UseHVX]> { let Inst{7-6} = 0b11; @@ -42750,24 +33870,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vrsadubi_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), -"$Vxx32.uw += vrsad($Vuu32.ub,$Rt32.ub,#$Ii)", -tc_41f99e1c, TypeCVI_VX_DV>, Enc_d483b9, Requires<[HasV60T,UseHVX]> { -let Inst{7-6} = 0b11; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001010; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vrsadubi_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vxx32 += vrsadub($Vuu32,$Rt32,#$Ii)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42778,23 +33883,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vrsadubi_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), -"$Vxx32 += vrsadub($Vuu32,$Rt32,#$Ii)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vrsadubi_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vdd32 = vrsadub($Vuu32,$Rt32,#$Ii)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42803,21 +33894,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vrsadubi_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), -"$Vdd32 = vrsadub($Vuu32,$Rt32,#$Ii)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsathub : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vsat($Vu32.h,$Vv32.h)", tc_9b9642a1, TypeCVI_VINLANESAT>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -42827,22 +33906,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsathub_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.ub = vsat($Vu32.h,$Vv32.h)", -tc_9b9642a1, TypeCVI_VINLANESAT>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsathub_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsathub($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42851,21 +33917,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsathub_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vsathub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsatuwuh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vsat($Vu32.uw,$Vv32.uw)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b110; @@ -42875,22 +33929,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsatuwuh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.uh = vsat($Vu32.uw,$Vv32.uw)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsatuwuh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsatuwuh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -42899,21 +33940,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsatuwuh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vsatuwuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsatwh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vsat($Vu32.w,$Vv32.w)", tc_9b9642a1, TypeCVI_VINLANESAT>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -42923,22 +33952,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsatwh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.h = vsat($Vu32.w,$Vv32.w)", -tc_9b9642a1, TypeCVI_VINLANESAT>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsatwh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsatwh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42947,21 +33963,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsatwh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vsatwh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsb : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32.h = vsxt($Vu32.b)", tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -42971,22 +33975,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsb_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), -"$Vdd32.h = vsxt($Vu32.b)", -tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsb_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32 = vsxtb($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42995,21 +33986,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsb_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), -"$Vdd32 = vsxtb($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsh : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32.w = vsxt($Vu32.h)", tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -43019,22 +33998,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsh_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), -"$Vdd32.w = vsxt($Vu32.h)", -tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsh_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32 = vsxth($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43043,21 +34009,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsh_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), -"$Vdd32 = vsxth($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vshufeh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vshuffe($Vu32.h,$Vv32.h)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -43067,22 +34021,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vshufeh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.h = vshuffe($Vu32.h,$Vv32.h)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vshufeh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vshuffeh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43091,21 +34032,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vshufeh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vshuffeh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vshuff : HInst< -(outs VectorRegs:$Vy32, VectorRegs:$Vx32), -(ins VectorRegs:$Vy32in, VectorRegs:$Vx32in, IntRegs:$Rt32), +(outs HvxVR:$Vy32, HvxVR:$Vx32), +(ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32), "vshuff($Vy32,$Vx32,$Rt32)", tc_5c120602, TypeCVI_VP_VS>, Enc_989021, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -43118,25 +34047,9 @@ let opNewValue2 = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; } -def V6_vshuff_128B : HInst< -(outs VectorRegs128B:$Vy32, VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vy32in, VectorRegs128B:$Vx32in, IntRegs:$Rt32), -"vshuff($Vy32,$Vx32,$Rt32)", -tc_5c120602, TypeCVI_VP_VS>, Enc_989021, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001111; -let hasNewValue = 1; -let opNewValue = 0; -let hasNewValue2 = 1; -let opNewValue2 = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; -} def V6_vshuffb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32.b = vshuff($Vu32.b)", tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -43146,22 +34059,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vshuffb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32.b = vshuff($Vu32.b)", -tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vshuffb_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32 = vshuffb($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43170,21 +34070,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vshuffb_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32 = vshuffb($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vshuffeb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vshuffe($Vu32.b,$Vv32.b)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -43194,22 +34082,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vshuffeb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.b = vshuffe($Vu32.b,$Vv32.b)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vshuffeb_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vshuffeb($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43218,21 +34093,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vshuffeb_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vshuffeb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vshuffh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32.h = vshuff($Vu32.h)", tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -43242,22 +34105,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vshuffh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32.h = vshuff($Vu32.h)", -tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vshuffh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32 = vshuffh($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43266,21 +34116,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vshuffh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32 = vshuffh($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vshuffob : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vshuffo($Vu32.b,$Vv32.b)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -43290,22 +34128,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vshuffob_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.b = vshuffo($Vu32.b,$Vv32.b)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vshuffob_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vshuffob($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43314,21 +34139,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vshuffob_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vshuffob($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vshuffvdd : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vdd32 = vshuff($Vu32,$Vv32,$Rt8)", tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -43338,22 +34151,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vshuffvdd_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), -"$Vdd32 = vshuff($Vu32,$Vv32,$Rt8)", -tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b1; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vshufoeb : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.b = vshuffoe($Vu32.b,$Vv32.b)", tc_97c165b9, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -43363,22 +34163,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vshufoeb_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32.b = vshuffoe($Vu32.b,$Vv32.b)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vshufoeb_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vshuffoeb($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43387,21 +34174,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vshufoeb_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32 = vshuffoeb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vshufoeh : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.h = vshuffoe($Vu32.h,$Vv32.h)", tc_97c165b9, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -43411,22 +34186,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vshufoeh_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32.h = vshuffoe($Vu32.h,$Vv32.h)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vshufoeh_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vshuffoeh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43435,21 +34197,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vshufoeh_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32 = vshuffoeh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vshufoh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vshuffo($Vu32.h,$Vv32.h)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -43459,22 +34209,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vshufoh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.h = vshuffo($Vu32.h,$Vv32.h)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vshufoh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vshuffoh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43483,21 +34220,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vshufoh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vshuffoh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vsub($Vu32.b,$Vv32.b)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -43507,22 +34232,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.b = vsub($Vu32.b,$Vv32.b)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubb_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsubb($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43531,21 +34243,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubb_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vsubb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubb_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.b = vsub($Vuu32.b,$Vvv32.b)", tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -43555,22 +34255,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubb_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32.b = vsub($Vuu32.b,$Vvv32.b)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubb_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vsubb($Vuu32,$Vvv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43579,21 +34266,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubb_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32 = vsubb($Vuu32,$Vvv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubbnq : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4) $Vx32.b -= $Vu32.b", tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -43605,24 +34280,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vsubbnq_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), -"if (!$Qv4) $Vx32.b -= $Vu32.b", -tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b1; -let Inst{21-16} = 0b000010; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vsubbnq_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4.b) $Vx32.b -= $Vu32.b", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43632,22 +34292,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vsubbnq_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), -"if (!$Qv4.b) $Vx32.b -= $Vu32.b", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vsubbq : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4) $Vx32.b -= $Vu32.b", tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -43659,24 +34306,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vsubbq_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), -"if ($Qv4) $Vx32.b -= $Vu32.b", -tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b1; -let Inst{21-16} = 0b000001; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vsubbq_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4.b) $Vx32.b -= $Vu32.b", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43686,22 +34318,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vsubbq_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), -"if ($Qv4.b) $Vx32.b -= $Vu32.b", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vsubbsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vsub($Vu32.b,$Vv32.b):sat", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b010; @@ -43711,22 +34330,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubbsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.b = vsub($Vu32.b,$Vv32.b):sat", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubbsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsubb($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -43735,21 +34341,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubbsat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vsubb($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubbsat_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.b = vsub($Vuu32.b,$Vvv32.b):sat", tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b001; @@ -43759,22 +34353,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubbsat_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32.b = vsub($Vuu32.b,$Vvv32.b):sat", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011110101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubbsat_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vsubb($Vuu32,$Vvv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -43783,21 +34364,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubbsat_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32 = vsubb($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubcarry : HInst< -(outs VectorRegs:$Vd32, VecPredRegs:$Qx4), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, VecPredRegs:$Qx4in), +(outs HvxVR:$Vd32, HvxQR:$Qx4), +(ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qx4in), "$Vd32.w = vsub($Vu32.w,$Vv32.w,$Qx4):carry", tc_5a9fc4ec, TypeCVI_VA>, Enc_b43b67, Requires<[HasV62T,UseHVX]> { let Inst{7-7} = 0b1; @@ -43810,25 +34379,9 @@ let opNewValue2 = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vsubcarry_128B : HInst< -(outs VectorRegs128B:$Vd32, VecPredRegs128B:$Qx4), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, VecPredRegs128B:$Qx4in), -"$Vd32.w = vsub($Vu32.w,$Vv32.w,$Qx4):carry", -tc_5a9fc4ec, TypeCVI_VA>, Enc_b43b67, Requires<[HasV62T,UseHVX]> { -let Inst{7-7} = 0b1; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100101; -let hasNewValue = 1; -let opNewValue = 0; -let hasNewValue2 = 1; -let opNewValue2 = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_vsubh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vsub($Vu32.h,$Vv32.h)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -43838,22 +34391,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.h = vsub($Vu32.h,$Vv32.h)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsubh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43862,21 +34402,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vsubh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubh_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.h = vsub($Vuu32.h,$Vvv32.h)", tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -43886,22 +34414,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubh_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32.h = vsub($Vuu32.h,$Vvv32.h)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubh_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vsubh($Vuu32,$Vvv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43910,21 +34425,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubh_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32 = vsubh($Vuu32,$Vvv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubhnq : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4) $Vx32.h -= $Vu32.h", tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -43936,24 +34439,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vsubhnq_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), -"if (!$Qv4) $Vx32.h -= $Vu32.h", -tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b1; -let Inst{21-16} = 0b000010; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vsubhnq_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4.h) $Vx32.h -= $Vu32.h", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43963,22 +34451,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vsubhnq_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), -"if (!$Qv4.h) $Vx32.h -= $Vu32.h", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vsubhq : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4) $Vx32.h -= $Vu32.h", tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -43990,24 +34465,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vsubhq_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), -"if ($Qv4) $Vx32.h -= $Vu32.h", -tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b1; -let Inst{21-16} = 0b000001; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vsubhq_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4.h) $Vx32.h -= $Vu32.h", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44017,22 +34477,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vsubhq_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), -"if ($Qv4.h) $Vx32.h -= $Vu32.h", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vsubhsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vsub($Vu32.h,$Vv32.h):sat", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -44042,22 +34489,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubhsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.h = vsub($Vu32.h,$Vv32.h):sat", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubhsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsubh($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44066,21 +34500,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubhsat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vsubh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubhsat_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.h = vsub($Vuu32.h,$Vvv32.h):sat", tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -44090,22 +34512,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubhsat_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32.h = vsub($Vuu32.h,$Vvv32.h):sat", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubhsat_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vsubh($Vuu32,$Vvv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44114,21 +34523,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubhsat_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32 = vsubh($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubhw : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.w = vsub($Vu32.h,$Vv32.h)", tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -44138,22 +34535,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubhw_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32.w = vsub($Vu32.h,$Vv32.h)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubhw_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vsubh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44162,21 +34546,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubhw_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32 = vsubh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsububh : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.h = vsub($Vu32.ub,$Vv32.ub)", tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -44186,22 +34558,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsububh_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32.h = vsub($Vu32.ub,$Vv32.ub)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsububh_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vsubub($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44210,21 +34569,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsububh_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32 = vsubub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsububsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vsub($Vu32.ub,$Vv32.ub):sat", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -44234,22 +34581,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsububsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.ub = vsub($Vu32.ub,$Vv32.ub):sat", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsububsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsubub($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44258,21 +34592,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsububsat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vsubub($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsububsat_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.ub = vsub($Vuu32.ub,$Vvv32.ub):sat", tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -44282,22 +34604,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsububsat_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32.ub = vsub($Vuu32.ub,$Vvv32.ub):sat", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsububsat_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vsubub($Vuu32,$Vvv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44306,21 +34615,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsububsat_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32 = vsubub($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubububb_sat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vsub($Vu32.ub,$Vv32.b):sat", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b101; @@ -44330,22 +34627,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubububb_sat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.ub = vsub($Vu32.ub,$Vv32.b):sat", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011110101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubuhsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vsub($Vu32.uh,$Vv32.uh):sat", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -44355,22 +34639,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubuhsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.uh = vsub($Vu32.uh,$Vv32.uh):sat", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubuhsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsubuh($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44379,21 +34650,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubuhsat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vsubuh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubuhsat_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.uh = vsub($Vuu32.uh,$Vvv32.uh):sat", tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -44403,22 +34662,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubuhsat_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32.uh = vsub($Vuu32.uh,$Vvv32.uh):sat", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubuhsat_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vsubuh($Vuu32,$Vvv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44427,21 +34673,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubuhsat_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32 = vsubuh($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubuhw : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.w = vsub($Vu32.uh,$Vv32.uh)", tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -44451,22 +34685,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubuhw_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32.w = vsub($Vu32.uh,$Vv32.uh)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubuhw_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vsubuh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44475,21 +34696,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubuhw_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32 = vsubuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubuwsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uw = vsub($Vu32.uw,$Vv32.uw):sat", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b100; @@ -44499,22 +34708,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubuwsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.uw = vsub($Vu32.uw,$Vv32.uw):sat", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubuwsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsubuw($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -44523,21 +34719,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubuwsat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vsubuw($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubuwsat_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.uw = vsub($Vuu32.uw,$Vvv32.uw):sat", tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b011; @@ -44547,22 +34731,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubuwsat_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32.uw = vsub($Vuu32.uw,$Vvv32.uw):sat", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011110101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubuwsat_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vsubuw($Vuu32,$Vvv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -44571,21 +34742,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubuwsat_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32 = vsubuw($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubw : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vsub($Vu32.w,$Vv32.w)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -44595,22 +34754,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubw_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.w = vsub($Vu32.w,$Vv32.w)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubw_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsubw($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44619,21 +34765,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubw_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vsubw($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubw_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.w = vsub($Vuu32.w,$Vvv32.w)", tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -44643,22 +34777,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubw_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32.w = vsub($Vuu32.w,$Vvv32.w)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubw_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vsubw($Vuu32,$Vvv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44667,21 +34788,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubw_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32 = vsubw($Vuu32,$Vvv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubwnq : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4) $Vx32.w -= $Vu32.w", tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -44693,24 +34802,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vsubwnq_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), -"if (!$Qv4) $Vx32.w -= $Vu32.w", -tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b1; -let Inst{21-16} = 0b000010; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vsubwnq_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4.w) $Vx32.w -= $Vu32.w", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44720,22 +34814,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vsubwnq_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), -"if (!$Qv4.w) $Vx32.w -= $Vu32.w", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vsubwq : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4) $Vx32.w -= $Vu32.w", tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -44747,24 +34828,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vsubwq_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), -"if ($Qv4) $Vx32.w -= $Vu32.w", -tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b1; -let Inst{21-16} = 0b000010; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vsubwq_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4.w) $Vx32.w -= $Vu32.w", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44774,22 +34840,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vsubwq_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), -"if ($Qv4.w) $Vx32.w -= $Vu32.w", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vsubwsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vsub($Vu32.w,$Vv32.w):sat", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -44799,22 +34852,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubwsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.w = vsub($Vu32.w,$Vv32.w):sat", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubwsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsubw($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44823,21 +34863,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubwsat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vsubw($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubwsat_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.w = vsub($Vuu32.w,$Vvv32.w):sat", tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -44847,22 +34875,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubwsat_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32.w = vsub($Vuu32.w,$Vvv32.w):sat", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubwsat_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vsubw($Vuu32,$Vvv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44871,21 +34886,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubwsat_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32 = vsubw($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vswap : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecPredRegs:$Qt4, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxWR:$Vdd32), +(ins HvxQR:$Qt4, HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vswap($Qt4,$Vu32,$Vv32)", tc_316c637c, TypeCVI_VA_DV>, Enc_3dac0b, Requires<[HasV60T,UseHVX]> { let Inst{7-7} = 0b0; @@ -44895,22 +34898,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vswap_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecPredRegs128B:$Qt4, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32 = vswap($Qt4,$Vu32,$Vv32)", -tc_316c637c, TypeCVI_VA_DV>, Enc_3dac0b, Requires<[HasV60T,UseHVX]> { -let Inst{7-7} = 0b0; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011110101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vtmpyb : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32.h = vtmpy($Vuu32.b,$Rt32.b)", tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -44920,22 +34910,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vtmpyb_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vdd32.h = vtmpy($Vuu32.b,$Rt32.b)", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vtmpyb_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32.h += vtmpy($Vuu32.b,$Rt32.b)", tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -44947,24 +34924,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vtmpyb_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vxx32.h += vtmpy($Vuu32.b,$Rt32.b)", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vtmpyb_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32 += vtmpyb($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44975,23 +34937,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vtmpyb_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vxx32 += vtmpyb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vtmpyb_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32 = vtmpyb($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -45000,21 +34948,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vtmpyb_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vdd32 = vtmpyb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vtmpybus : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32.h = vtmpy($Vuu32.ub,$Rt32.b)", tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -45024,22 +34960,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vtmpybus_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vdd32.h = vtmpy($Vuu32.ub,$Rt32.b)", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vtmpybus_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32.h += vtmpy($Vuu32.ub,$Rt32.b)", tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -45051,24 +34974,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vtmpybus_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vxx32.h += vtmpy($Vuu32.ub,$Rt32.b)", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vtmpybus_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32 += vtmpybus($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -45079,23 +34987,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vtmpybus_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vxx32 += vtmpybus($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vtmpybus_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32 = vtmpybus($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -45104,21 +34998,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vtmpybus_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vdd32 = vtmpybus($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vtmpyhb : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32.w = vtmpy($Vuu32.h,$Rt32.b)", tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -45128,22 +35010,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vtmpyhb_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vdd32.w = vtmpy($Vuu32.h,$Rt32.b)", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vtmpyhb_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32.w += vtmpy($Vuu32.h,$Rt32.b)", tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -45155,24 +35024,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vtmpyhb_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vxx32.w += vtmpy($Vuu32.h,$Rt32.b)", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vtmpyhb_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32 += vtmpyhb($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -45183,23 +35037,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vtmpyhb_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vxx32 += vtmpyhb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vtmpyhb_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32 = vtmpyhb($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -45208,21 +35048,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vtmpyhb_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vdd32 = vtmpyhb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vtran2x2_map : HInst< -(outs VectorRegs:$Vy32, VectorRegs:$Vx32), -(ins VectorRegs:$Vy32in, VectorRegs:$Vx32in, IntRegs:$Rt32), +(outs HvxVR:$Vy32, HvxVR:$Vx32), +(ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32), "vtrans2x2($Vy32,$Vx32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -45234,24 +35062,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; } -def V6_vtran2x2_map_128B : HInst< -(outs VectorRegs128B:$Vy32, VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vy32in, VectorRegs128B:$Vx32in, IntRegs:$Rt32), -"vtrans2x2($Vy32,$Vx32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let hasNewValue2 = 1; -let opNewValue2 = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; -} def V6_vunpackb : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32.h = vunpack($Vu32.b)", tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -45261,22 +35074,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vunpackb_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), -"$Vdd32.h = vunpack($Vu32.b)", -tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vunpackb_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32 = vunpackb($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -45285,21 +35085,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vunpackb_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), -"$Vdd32 = vunpackb($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vunpackh : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32.w = vunpack($Vu32.h)", tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -45309,22 +35097,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vunpackh_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), -"$Vdd32.w = vunpack($Vu32.h)", -tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vunpackh_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32 = vunpackh($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -45333,21 +35108,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vunpackh_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), -"$Vdd32 = vunpackh($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vunpackob : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32), "$Vxx32.h |= vunpacko($Vu32.b)", tc_72ad7b54, TypeCVI_VP_VS>, Enc_500cb0, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -45359,24 +35122,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vunpackob_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32), -"$Vxx32.h |= vunpacko($Vu32.b)", -tc_72ad7b54, TypeCVI_VP_VS>, Enc_500cb0, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b1; -let Inst{31-16} = 0b0001111000000000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vunpackob_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32), "$Vxx32 |= vunpackob($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -45386,22 +35134,9 @@ let isPseudo = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vunpackob_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32), -"$Vxx32 |= vunpackob($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vunpackoh : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32), "$Vxx32.w |= vunpacko($Vu32.h)", tc_72ad7b54, TypeCVI_VP_VS>, Enc_500cb0, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -45413,24 +35148,9 @@ let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vunpackoh_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32), -"$Vxx32.w |= vunpacko($Vu32.h)", -tc_72ad7b54, TypeCVI_VP_VS>, Enc_500cb0, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b1; -let Inst{31-16} = 0b0001111000000000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vunpackoh_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32), +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32), "$Vxx32 |= vunpackoh($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -45441,23 +35161,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vunpackoh_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32), -"$Vxx32 |= vunpackoh($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vunpackub : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32.uh = vunpack($Vu32.ub)", tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -45467,22 +35173,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vunpackub_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), -"$Vdd32.uh = vunpack($Vu32.ub)", -tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vunpackub_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32 = vunpackub($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -45491,21 +35184,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vunpackub_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), -"$Vdd32 = vunpackub($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vunpackuh : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32.uw = vunpack($Vu32.uh)", tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -45515,22 +35196,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vunpackuh_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), -"$Vdd32.uw = vunpack($Vu32.uh)", -tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vunpackuh_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32 = vunpackuh($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -45539,18 +35207,6 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vunpackuh_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), -"$Vdd32 = vunpackuh($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vwhist128 : HInst< (outs), (ins), @@ -45560,16 +35216,6 @@ let Inst{13-0} = 0b10010010000000; let Inst{31-16} = 0b0001111000000000; let DecoderNamespace = "EXT_mmvec"; } -def V6_vwhist128_128B : HInst< -(outs), -(ins), -"vwhist128", -tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[HasV62T,UseHVX]> { -let Inst{13-0} = 0b10010010000000; -let Inst{31-16} = 0b0001111000000000; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vwhist128m : HInst< (outs), (ins u1_0Imm:$Ii), @@ -45580,20 +35226,9 @@ let Inst{13-9} = 0b10011; let Inst{31-16} = 0b0001111000000000; let DecoderNamespace = "EXT_mmvec"; } -def V6_vwhist128m_128B : HInst< -(outs), -(ins u1_0Imm:$Ii), -"vwhist128(#$Ii)", -tc_b77635b4, TypeCVI_HIST>, Enc_efaed8, Requires<[HasV62T,UseHVX]> { -let Inst{7-0} = 0b10000000; -let Inst{13-9} = 0b10011; -let Inst{31-16} = 0b0001111000000000; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vwhist128q : HInst< (outs), -(ins VecPredRegs:$Qv4), +(ins HvxQR:$Qv4), "vwhist128($Qv4)", tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[HasV62T,UseHVX]> { let Inst{13-0} = 0b10010010000000; @@ -45601,20 +35236,9 @@ let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; let DecoderNamespace = "EXT_mmvec"; } -def V6_vwhist128q_128B : HInst< -(outs), -(ins VecPredRegs128B:$Qv4), -"vwhist128($Qv4)", -tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[HasV62T,UseHVX]> { -let Inst{13-0} = 0b10010010000000; -let Inst{21-16} = 0b000010; -let Inst{31-24} = 0b00011110; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vwhist128qm : HInst< (outs), -(ins VecPredRegs:$Qv4, u1_0Imm:$Ii), +(ins HvxQR:$Qv4, u1_0Imm:$Ii), "vwhist128($Qv4,#$Ii)", tc_28978789, TypeCVI_HIST>, Enc_802dc0, Requires<[HasV62T,UseHVX]> { let Inst{7-0} = 0b10000000; @@ -45623,18 +35247,6 @@ let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; let DecoderNamespace = "EXT_mmvec"; } -def V6_vwhist128qm_128B : HInst< -(outs), -(ins VecPredRegs128B:$Qv4, u1_0Imm:$Ii), -"vwhist128($Qv4,#$Ii)", -tc_28978789, TypeCVI_HIST>, Enc_802dc0, Requires<[HasV62T,UseHVX]> { -let Inst{7-0} = 0b10000000; -let Inst{13-9} = 0b10011; -let Inst{21-16} = 0b000010; -let Inst{31-24} = 0b00011110; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vwhist256 : HInst< (outs), (ins), @@ -45644,16 +35256,6 @@ let Inst{13-0} = 0b10001010000000; let Inst{31-16} = 0b0001111000000000; let DecoderNamespace = "EXT_mmvec"; } -def V6_vwhist256_128B : HInst< -(outs), -(ins), -"vwhist256", -tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[HasV62T,UseHVX]> { -let Inst{13-0} = 0b10001010000000; -let Inst{31-16} = 0b0001111000000000; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vwhist256_sat : HInst< (outs), (ins), @@ -45663,19 +35265,9 @@ let Inst{13-0} = 0b10001110000000; let Inst{31-16} = 0b0001111000000000; let DecoderNamespace = "EXT_mmvec"; } -def V6_vwhist256_sat_128B : HInst< -(outs), -(ins), -"vwhist256:sat", -tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[HasV62T,UseHVX]> { -let Inst{13-0} = 0b10001110000000; -let Inst{31-16} = 0b0001111000000000; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vwhist256q : HInst< (outs), -(ins VecPredRegs:$Qv4), +(ins HvxQR:$Qv4), "vwhist256($Qv4)", tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[HasV62T,UseHVX]> { let Inst{13-0} = 0b10001010000000; @@ -45683,20 +35275,9 @@ let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; let DecoderNamespace = "EXT_mmvec"; } -def V6_vwhist256q_128B : HInst< -(outs), -(ins VecPredRegs128B:$Qv4), -"vwhist256($Qv4)", -tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[HasV62T,UseHVX]> { -let Inst{13-0} = 0b10001010000000; -let Inst{21-16} = 0b000010; -let Inst{31-24} = 0b00011110; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vwhist256q_sat : HInst< (outs), -(ins VecPredRegs:$Qv4), +(ins HvxQR:$Qv4), "vwhist256($Qv4):sat", tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[HasV62T,UseHVX]> { let Inst{13-0} = 0b10001110000000; @@ -45704,20 +35285,9 @@ let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; let DecoderNamespace = "EXT_mmvec"; } -def V6_vwhist256q_sat_128B : HInst< -(outs), -(ins VecPredRegs128B:$Qv4), -"vwhist256($Qv4):sat", -tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[HasV62T,UseHVX]> { -let Inst{13-0} = 0b10001110000000; -let Inst{21-16} = 0b000010; -let Inst{31-24} = 0b00011110; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vxor : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vxor($Vu32,$Vv32)", tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -45727,22 +35297,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vxor_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vxor($Vu32,$Vv32)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vzb : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32.uh = vzxt($Vu32.ub)", tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -45752,22 +35309,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vzb_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), -"$Vdd32.uh = vzxt($Vu32.ub)", -tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vzb_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32 = vzxtb($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -45776,21 +35320,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vzb_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), -"$Vdd32 = vzxtb($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vzh : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32.uw = vzxt($Vu32.uh)", tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -45800,22 +35332,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vzh_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), -"$Vdd32.uw = vzxt($Vu32.uh)", -tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vzh_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32 = vzxth($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -45824,18 +35343,6 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vzh_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), -"$Vdd32 = vzxth($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def Y2_barrier : HInst< (outs), (ins), diff --git a/llvm/lib/Target/Hexagon/HexagonDepMappings.td b/llvm/lib/Target/Hexagon/HexagonDepMappings.td index 77a56a9adf10..ebef4f10acb8 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepMappings.td +++ b/llvm/lib/Target/Hexagon/HexagonDepMappings.td @@ -140,515 +140,263 @@ def S4_storeirif_zomapAlias : InstAlias<"if (!$Pv4) memw($Rs32)=#$II", (S4_store def S4_storeirifnew_zomapAlias : InstAlias<"if (!$Pv4.new) memw($Rs32)=#$II", (S4_storeirifnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; def S4_storeirit_zomapAlias : InstAlias<"if ($Pv4) memw($Rs32)=#$II", (S4_storeirit_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; def S4_storeiritnew_zomapAlias : InstAlias<"if ($Pv4.new) memw($Rs32)=#$II", (S4_storeiritnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; -def V6_MAP_equbAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equb_128BAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equb_andAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equb_and_128BAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equb_iorAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equb_ior_128BAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equb_xorAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equb_xor_128BAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equhAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equh_128BAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equh_andAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equh_and_128BAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equh_iorAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equh_ior_128BAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equh_xorAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equh_xor_128BAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equwAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equw_128BAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equw_andAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equw_and_128BAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equw_iorAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equw_ior_128BAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equw_xorAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equw_xor_128BAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_extractw_altAlias : InstAlias<"$Rd32.w=vextract($Vu32,$Rs32)", (V6_extractw IntRegs:$Rd32, VectorRegs:$Vu32, IntRegs:$Rs32)>, Requires<[UseHVX]>; -def V6_extractw_alt_128BAlias : InstAlias<"$Rd32.w=vextract($Vu32,$Rs32)", (V6_extractw IntRegs:$Rd32, VectorRegs:$Vu32, IntRegs:$Rs32)>, Requires<[UseHVX]>; -def V6_ld0Alias : InstAlias<"$Vd32=vmem($Rt32)", (V6_vL32b_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; -def V6_ld0_128BAlias : InstAlias<"$Vd32=vmem($Rt32)", (V6_vL32b_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; -def V6_ldnt0Alias : InstAlias<"$Vd32=vmem($Rt32):nt", (V6_vL32b_nt_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; -def V6_ldnt0_128BAlias : InstAlias<"$Vd32=vmem($Rt32):nt", (V6_vL32b_nt_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; -def V6_ldu0Alias : InstAlias<"$Vd32=vmemu($Rt32)", (V6_vL32Ub_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; -def V6_ldu0_128BAlias : InstAlias<"$Vd32=vmemu($Rt32)", (V6_vL32Ub_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; -def V6_st0Alias : InstAlias<"vmem($Rt32)=$Vs32", (V6_vS32b_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_st0_128BAlias : InstAlias<"vmem($Rt32)=$Vs32", (V6_vS32b_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stn0Alias : InstAlias<"vmem($Rt32)=$Os8.new", (V6_vS32b_new_ai IntRegs:$Rt32, 0, VectorRegs:$Os8)>, Requires<[UseHVX]>; -def V6_stn0_128BAlias : InstAlias<"vmem($Rt32)=$Os8.new", (V6_vS32b_new_ai IntRegs:$Rt32, 0, VectorRegs:$Os8)>, Requires<[UseHVX]>; -def V6_stnnt0Alias : InstAlias<"vmem($Rt32):nt=$Os8.new", (V6_vS32b_nt_new_ai IntRegs:$Rt32, 0, VectorRegs:$Os8)>, Requires<[UseHVX]>; -def V6_stnnt0_128BAlias : InstAlias<"vmem($Rt32):nt=$Os8.new", (V6_vS32b_nt_new_ai IntRegs:$Rt32, 0, VectorRegs:$Os8)>, Requires<[UseHVX]>; -def V6_stnp0Alias : InstAlias<"if (!$Pv4) vmem($Rt32)=$Vs32", (V6_vS32b_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stnp0_128BAlias : InstAlias<"if (!$Pv4) vmem($Rt32)=$Vs32", (V6_vS32b_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stnpnt0Alias : InstAlias<"if (!$Pv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stnpnt0_128BAlias : InstAlias<"if (!$Pv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stnq0Alias : InstAlias<"if (!$Qv4) vmem($Rt32)=$Vs32", (V6_vS32b_nqpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stnq0_128BAlias : InstAlias<"if (!$Qv4) vmem($Rt32)=$Vs32", (V6_vS32b_nqpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stnqnt0Alias : InstAlias<"if (!$Qv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_nqpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stnqnt0_128BAlias : InstAlias<"if (!$Qv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_nqpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stnt0Alias : InstAlias<"vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stnt0_128BAlias : InstAlias<"vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stp0Alias : InstAlias<"if ($Pv4) vmem($Rt32)=$Vs32", (V6_vS32b_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stp0_128BAlias : InstAlias<"if ($Pv4) vmem($Rt32)=$Vs32", (V6_vS32b_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stpnt0Alias : InstAlias<"if ($Pv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stpnt0_128BAlias : InstAlias<"if ($Pv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stq0Alias : InstAlias<"if ($Qv4) vmem($Rt32)=$Vs32", (V6_vS32b_qpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stq0_128BAlias : InstAlias<"if ($Qv4) vmem($Rt32)=$Vs32", (V6_vS32b_qpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stqnt0Alias : InstAlias<"if ($Qv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_qpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stqnt0_128BAlias : InstAlias<"if ($Qv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_qpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stu0Alias : InstAlias<"vmemu($Rt32)=$Vs32", (V6_vS32Ub_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stu0_128BAlias : InstAlias<"vmemu($Rt32)=$Vs32", (V6_vS32Ub_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stunp0Alias : InstAlias<"if (!$Pv4) vmemu($Rt32)=$Vs32", (V6_vS32Ub_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stunp0_128BAlias : InstAlias<"if (!$Pv4) vmemu($Rt32)=$Vs32", (V6_vS32Ub_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stup0Alias : InstAlias<"if ($Pv4) vmemu($Rt32)=$Vs32", (V6_vS32Ub_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stup0_128BAlias : InstAlias<"if ($Pv4) vmemu($Rt32)=$Vs32", (V6_vS32Ub_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_vabsdiffh_altAlias : InstAlias<"$Vd32=vabsdiffh($Vu32,$Vv32)", (V6_vabsdiffh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vabsdiffh_alt_128BAlias : InstAlias<"$Vd32=vabsdiffh($Vu32,$Vv32)", (V6_vabsdiffh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vabsdiffub_altAlias : InstAlias<"$Vd32=vabsdiffub($Vu32,$Vv32)", (V6_vabsdiffub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vabsdiffub_alt_128BAlias : InstAlias<"$Vd32=vabsdiffub($Vu32,$Vv32)", (V6_vabsdiffub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vabsdiffuh_altAlias : InstAlias<"$Vd32=vabsdiffuh($Vu32,$Vv32)", (V6_vabsdiffuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vabsdiffuh_alt_128BAlias : InstAlias<"$Vd32=vabsdiffuh($Vu32,$Vv32)", (V6_vabsdiffuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vabsdiffw_altAlias : InstAlias<"$Vd32=vabsdiffw($Vu32,$Vv32)", (V6_vabsdiffw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vabsdiffw_alt_128BAlias : InstAlias<"$Vd32=vabsdiffw($Vu32,$Vv32)", (V6_vabsdiffw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vabsh_altAlias : InstAlias<"$Vd32=vabsh($Vu32)", (V6_vabsh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vabsh_alt_128BAlias : InstAlias<"$Vd32=vabsh($Vu32)", (V6_vabsh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vabsh_sat_altAlias : InstAlias<"$Vd32=vabsh($Vu32):sat", (V6_vabsh_sat VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vabsh_sat_alt_128BAlias : InstAlias<"$Vd32=vabsh($Vu32):sat", (V6_vabsh_sat VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vabsuh_altAlias : InstAlias<"$Vd32.uh=vabs($Vu32.h)", (V6_vabsh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vabsuh_alt_128BAlias : InstAlias<"$Vd32.uh=vabs($Vu32.h)", (V6_vabsh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vabsuw_altAlias : InstAlias<"$Vd32.uw=vabs($Vu32.w)", (V6_vabsw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vabsuw_alt_128BAlias : InstAlias<"$Vd32.uw=vabs($Vu32.w)", (V6_vabsw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vabsw_altAlias : InstAlias<"$Vd32=vabsw($Vu32)", (V6_vabsw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vabsw_alt_128BAlias : InstAlias<"$Vd32=vabsw($Vu32)", (V6_vabsw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vabsw_sat_altAlias : InstAlias<"$Vd32=vabsw($Vu32):sat", (V6_vabsw_sat VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vabsw_sat_alt_128BAlias : InstAlias<"$Vd32=vabsw($Vu32):sat", (V6_vabsw_sat VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddb_altAlias : InstAlias<"$Vd32=vaddb($Vu32,$Vv32)", (V6_vaddb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddb_alt_128BAlias : InstAlias<"$Vd32=vaddb($Vu32,$Vv32)", (V6_vaddb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddb_dv_altAlias : InstAlias<"$Vdd32=vaddb($Vuu32,$Vvv32)", (V6_vaddb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vaddb_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddb($Vuu32,$Vvv32)", (V6_vaddb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vaddbnq_altAlias : InstAlias<"if (!$Qv4.b) $Vx32.b+=$Vu32.b", (V6_vaddbnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddbnq_alt_128BAlias : InstAlias<"if (!$Qv4.b) $Vx32.b+=$Vu32.b", (V6_vaddbnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddbq_altAlias : InstAlias<"if ($Qv4.b) $Vx32.b+=$Vu32.b", (V6_vaddbq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddbq_alt_128BAlias : InstAlias<"if ($Qv4.b) $Vx32.b+=$Vu32.b", (V6_vaddbq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddh_altAlias : InstAlias<"$Vd32=vaddh($Vu32,$Vv32)", (V6_vaddh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddh_alt_128BAlias : InstAlias<"$Vd32=vaddh($Vu32,$Vv32)", (V6_vaddh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddh_dv_altAlias : InstAlias<"$Vdd32=vaddh($Vuu32,$Vvv32)", (V6_vaddh_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vaddh_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddh($Vuu32,$Vvv32)", (V6_vaddh_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vaddhnq_altAlias : InstAlias<"if (!$Qv4.h) $Vx32.h+=$Vu32.h", (V6_vaddhnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddhnq_alt_128BAlias : InstAlias<"if (!$Qv4.h) $Vx32.h+=$Vu32.h", (V6_vaddhnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddhq_altAlias : InstAlias<"if ($Qv4.h) $Vx32.h+=$Vu32.h", (V6_vaddhq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddhq_alt_128BAlias : InstAlias<"if ($Qv4.h) $Vx32.h+=$Vu32.h", (V6_vaddhq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddhsat_altAlias : InstAlias<"$Vd32=vaddh($Vu32,$Vv32):sat", (V6_vaddhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddhsat_alt_128BAlias : InstAlias<"$Vd32=vaddh($Vu32,$Vv32):sat", (V6_vaddhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddhsat_dv_altAlias : InstAlias<"$Vdd32=vaddh($Vuu32,$Vvv32):sat", (V6_vaddhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vaddhsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddh($Vuu32,$Vvv32):sat", (V6_vaddhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vaddhw_altAlias : InstAlias<"$Vdd32=vaddh($Vu32,$Vv32)", (V6_vaddhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddhw_alt_128BAlias : InstAlias<"$Vdd32=vaddh($Vu32,$Vv32)", (V6_vaddhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddubh_altAlias : InstAlias<"$Vdd32=vaddub($Vu32,$Vv32)", (V6_vaddubh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddubh_alt_128BAlias : InstAlias<"$Vdd32=vaddub($Vu32,$Vv32)", (V6_vaddubh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddubsat_altAlias : InstAlias<"$Vd32=vaddub($Vu32,$Vv32):sat", (V6_vaddubsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddubsat_alt_128BAlias : InstAlias<"$Vd32=vaddub($Vu32,$Vv32):sat", (V6_vaddubsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddubsat_dv_altAlias : InstAlias<"$Vdd32=vaddub($Vuu32,$Vvv32):sat", (V6_vaddubsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vaddubsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddub($Vuu32,$Vvv32):sat", (V6_vaddubsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vadduhsat_altAlias : InstAlias<"$Vd32=vadduh($Vu32,$Vv32):sat", (V6_vadduhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vadduhsat_alt_128BAlias : InstAlias<"$Vd32=vadduh($Vu32,$Vv32):sat", (V6_vadduhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vadduhsat_dv_altAlias : InstAlias<"$Vdd32=vadduh($Vuu32,$Vvv32):sat", (V6_vadduhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vadduhsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vadduh($Vuu32,$Vvv32):sat", (V6_vadduhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vadduhw_altAlias : InstAlias<"$Vdd32=vadduh($Vu32,$Vv32)", (V6_vadduhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vadduhw_alt_128BAlias : InstAlias<"$Vdd32=vadduh($Vu32,$Vv32)", (V6_vadduhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddw_altAlias : InstAlias<"$Vd32=vaddw($Vu32,$Vv32)", (V6_vaddw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddw_alt_128BAlias : InstAlias<"$Vd32=vaddw($Vu32,$Vv32)", (V6_vaddw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddw_dv_altAlias : InstAlias<"$Vdd32=vaddw($Vuu32,$Vvv32)", (V6_vaddw_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vaddw_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddw($Vuu32,$Vvv32)", (V6_vaddw_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vaddwnq_altAlias : InstAlias<"if (!$Qv4.w) $Vx32.w+=$Vu32.w", (V6_vaddwnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddwnq_alt_128BAlias : InstAlias<"if (!$Qv4.w) $Vx32.w+=$Vu32.w", (V6_vaddwnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddwq_altAlias : InstAlias<"if ($Qv4.w) $Vx32.w+=$Vu32.w", (V6_vaddwq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddwq_alt_128BAlias : InstAlias<"if ($Qv4.w) $Vx32.w+=$Vu32.w", (V6_vaddwq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddwsat_altAlias : InstAlias<"$Vd32=vaddw($Vu32,$Vv32):sat", (V6_vaddwsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddwsat_alt_128BAlias : InstAlias<"$Vd32=vaddw($Vu32,$Vv32):sat", (V6_vaddwsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddwsat_dv_altAlias : InstAlias<"$Vdd32=vaddw($Vuu32,$Vvv32):sat", (V6_vaddwsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vaddwsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddw($Vuu32,$Vvv32):sat", (V6_vaddwsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vandqrt_acc_altAlias : InstAlias<"$Vx32.ub|=vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt_acc VectorRegs:$Vx32, VecPredRegs:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vandqrt_acc_alt_128BAlias : InstAlias<"$Vx32.ub|=vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt_acc VectorRegs:$Vx32, VecPredRegs:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vandqrt_altAlias : InstAlias<"$Vd32.ub=vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt VectorRegs:$Vd32, VecPredRegs:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vandqrt_alt_128BAlias : InstAlias<"$Vd32.ub=vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt VectorRegs:$Vd32, VecPredRegs:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vandvrt_acc_altAlias : InstAlias<"$Qx4.ub|=vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt_acc VecPredRegs:$Qx4, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vandvrt_acc_alt_128BAlias : InstAlias<"$Qx4.ub|=vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt_acc VecPredRegs:$Qx4, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vandvrt_altAlias : InstAlias<"$Qd4.ub=vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt VecPredRegs:$Qd4, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vandvrt_alt_128BAlias : InstAlias<"$Qd4.ub=vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt VecPredRegs:$Qd4, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vaslh_altAlias : InstAlias<"$Vd32=vaslh($Vu32,$Rt32)", (V6_vaslh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vaslh_alt_128BAlias : InstAlias<"$Vd32=vaslh($Vu32,$Rt32)", (V6_vaslh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vaslhv_altAlias : InstAlias<"$Vd32=vaslh($Vu32,$Vv32)", (V6_vaslhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaslhv_alt_128BAlias : InstAlias<"$Vd32=vaslh($Vu32,$Vv32)", (V6_vaslhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaslw_acc_altAlias : InstAlias<"$Vx32+=vaslw($Vu32,$Rt32)", (V6_vaslw_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vaslw_acc_alt_128BAlias : InstAlias<"$Vx32+=vaslw($Vu32,$Rt32)", (V6_vaslw_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vaslw_altAlias : InstAlias<"$Vd32=vaslw($Vu32,$Rt32)", (V6_vaslw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vaslw_alt_128BAlias : InstAlias<"$Vd32=vaslw($Vu32,$Rt32)", (V6_vaslw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vaslwv_altAlias : InstAlias<"$Vd32=vaslw($Vu32,$Vv32)", (V6_vaslwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaslwv_alt_128BAlias : InstAlias<"$Vd32=vaslw($Vu32,$Vv32)", (V6_vaslwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vasrh_altAlias : InstAlias<"$Vd32=vasrh($Vu32,$Rt32)", (V6_vasrh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vasrh_alt_128BAlias : InstAlias<"$Vd32=vasrh($Vu32,$Rt32)", (V6_vasrh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vasrhbrndsat_altAlias : InstAlias<"$Vd32=vasrhb($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrhbrndsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>; -def V6_vasrhubrndsat_altAlias : InstAlias<"$Vd32=vasrhub($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrhubrndsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>; -def V6_vasrhubsat_altAlias : InstAlias<"$Vd32=vasrhub($Vu32,$Vv32,$Rt8):sat", (V6_vasrhubsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>; -def V6_vasrhv_altAlias : InstAlias<"$Vd32=vasrh($Vu32,$Vv32)", (V6_vasrhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vasrhv_alt_128BAlias : InstAlias<"$Vd32=vasrh($Vu32,$Vv32)", (V6_vasrhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vasrw_acc_altAlias : InstAlias<"$Vx32+=vasrw($Vu32,$Rt32)", (V6_vasrw_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vasrw_acc_alt_128BAlias : InstAlias<"$Vx32+=vasrw($Vu32,$Rt32)", (V6_vasrw_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vasrw_altAlias : InstAlias<"$Vd32=vasrw($Vu32,$Rt32)", (V6_vasrw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vasrw_alt_128BAlias : InstAlias<"$Vd32=vasrw($Vu32,$Rt32)", (V6_vasrw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vasrwh_altAlias : InstAlias<"$Vd32=vasrwh($Vu32,$Vv32,$Rt8)", (V6_vasrwhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>; -def V6_vasrwhrndsat_altAlias : InstAlias<"$Vd32=vasrwh($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrwhrndsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>; -def V6_vasrwhsat_altAlias : InstAlias<"$Vd32=vasrwh($Vu32,$Vv32,$Rt8):sat", (V6_vasrwhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>; -def V6_vasrwuhsat_altAlias : InstAlias<"$Vd32=vasrwuh($Vu32,$Vv32,$Rt8):sat", (V6_vasrwuhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>; -def V6_vasrwv_altAlias : InstAlias<"$Vd32=vasrw($Vu32,$Vv32)", (V6_vasrwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vasrwv_alt_128BAlias : InstAlias<"$Vd32=vasrw($Vu32,$Vv32)", (V6_vasrwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavgh_altAlias : InstAlias<"$Vd32=vavgh($Vu32,$Vv32)", (V6_vavgh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavgh_alt_128BAlias : InstAlias<"$Vd32=vavgh($Vu32,$Vv32)", (V6_vavgh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavghrnd_altAlias : InstAlias<"$Vd32=vavgh($Vu32,$Vv32):rnd", (V6_vavghrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavghrnd_alt_128BAlias : InstAlias<"$Vd32=vavgh($Vu32,$Vv32):rnd", (V6_vavghrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavgub_altAlias : InstAlias<"$Vd32=vavgub($Vu32,$Vv32)", (V6_vavgub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavgub_alt_128BAlias : InstAlias<"$Vd32=vavgub($Vu32,$Vv32)", (V6_vavgub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavgubrnd_altAlias : InstAlias<"$Vd32=vavgub($Vu32,$Vv32):rnd", (V6_vavgubrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavgubrnd_alt_128BAlias : InstAlias<"$Vd32=vavgub($Vu32,$Vv32):rnd", (V6_vavgubrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavguh_altAlias : InstAlias<"$Vd32=vavguh($Vu32,$Vv32)", (V6_vavguh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavguh_alt_128BAlias : InstAlias<"$Vd32=vavguh($Vu32,$Vv32)", (V6_vavguh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavguhrnd_altAlias : InstAlias<"$Vd32=vavguh($Vu32,$Vv32):rnd", (V6_vavguhrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavguhrnd_alt_128BAlias : InstAlias<"$Vd32=vavguh($Vu32,$Vv32):rnd", (V6_vavguhrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavgw_altAlias : InstAlias<"$Vd32=vavgw($Vu32,$Vv32)", (V6_vavgw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavgw_alt_128BAlias : InstAlias<"$Vd32=vavgw($Vu32,$Vv32)", (V6_vavgw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavgwrnd_altAlias : InstAlias<"$Vd32=vavgw($Vu32,$Vv32):rnd", (V6_vavgwrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavgwrnd_alt_128BAlias : InstAlias<"$Vd32=vavgw($Vu32,$Vv32):rnd", (V6_vavgwrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vcl0h_altAlias : InstAlias<"$Vd32=vcl0h($Vu32)", (V6_vcl0h VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vcl0h_alt_128BAlias : InstAlias<"$Vd32=vcl0h($Vu32)", (V6_vcl0h VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vcl0w_altAlias : InstAlias<"$Vd32=vcl0w($Vu32)", (V6_vcl0w VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vcl0w_alt_128BAlias : InstAlias<"$Vd32=vcl0w($Vu32)", (V6_vcl0w VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vd0Alias : InstAlias<"$Vd32=#0", (V6_vxor VectorRegs:$Vd32, VectorRegs:$Vd32, VectorRegs:$Vd32)>, Requires<[UseHVX]>; -def V6_vd0_128BAlias : InstAlias<"$Vd32=#0", (V6_vxor VectorRegs:$Vd32, VectorRegs:$Vd32, VectorRegs:$Vd32)>, Requires<[UseHVX]>; -def V6_vdd0Alias : InstAlias<"$Vdd32=#0", (V6_vsubw_dv VecDblRegs:$Vdd32, W15, W15)>, Requires<[UseHVX]>; -def V6_vdd0_128BAlias : InstAlias<"$Vdd32=#0", (V6_vsubw_dv VecDblRegs:$Vdd32, W15, W15)>, Requires<[UseHVX]>; -def V6_vdealb4w_altAlias : InstAlias<"$Vd32=vdealb4w($Vu32,$Vv32)", (V6_vdealb4w VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vdealb4w_alt_128BAlias : InstAlias<"$Vd32=vdealb4w($Vu32,$Vv32)", (V6_vdealb4w VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vdealb_altAlias : InstAlias<"$Vd32=vdealb($Vu32)", (V6_vdealb VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vdealb_alt_128BAlias : InstAlias<"$Vd32=vdealb($Vu32)", (V6_vdealb VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vdealh_altAlias : InstAlias<"$Vd32=vdealh($Vu32)", (V6_vdealh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vdealh_alt_128BAlias : InstAlias<"$Vd32=vdealh($Vu32)", (V6_vdealh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vdmpybus_acc_altAlias : InstAlias<"$Vx32+=vdmpybus($Vu32,$Rt32)", (V6_vdmpybus_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpybus_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpybus($Vu32,$Rt32)", (V6_vdmpybus_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpybus_altAlias : InstAlias<"$Vd32=vdmpybus($Vu32,$Rt32)", (V6_vdmpybus VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpybus_alt_128BAlias : InstAlias<"$Vd32=vdmpybus($Vu32,$Rt32)", (V6_vdmpybus VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpybus_dv_acc_altAlias : InstAlias<"$Vxx32+=vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpybus_dv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpybus_dv_altAlias : InstAlias<"$Vdd32=vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpybus_dv_alt_128BAlias : InstAlias<"$Vdd32=vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhb_acc_altAlias : InstAlias<"$Vx32+=vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhb_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhb_altAlias : InstAlias<"$Vd32=vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhb_alt_128BAlias : InstAlias<"$Vd32=vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhb_dv_acc_altAlias : InstAlias<"$Vxx32+=vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhb_dv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhb_dv_altAlias : InstAlias<"$Vdd32=vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhb_dv_alt_128BAlias : InstAlias<"$Vdd32=vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhisat_acc_altAlias : InstAlias<"$Vx32+=vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat_acc VectorRegs:$Vx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhisat_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat_acc VectorRegs:$Vx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhisat_altAlias : InstAlias<"$Vd32=vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat VectorRegs:$Vd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhisat_alt_128BAlias : InstAlias<"$Vd32=vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat VectorRegs:$Vd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhsat_acc_altAlias : InstAlias<"$Vx32+=vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhsat_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhsat_altAlias : InstAlias<"$Vd32=vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhsat_alt_128BAlias : InstAlias<"$Vd32=vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhsuisat_acc_altAlias : InstAlias<"$Vx32+=vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat_acc VectorRegs:$Vx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhsuisat_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat_acc VectorRegs:$Vx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhsuisat_altAlias : InstAlias<"$Vd32=vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat VectorRegs:$Vd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhsuisat_alt_128BAlias : InstAlias<"$Vd32=vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat VectorRegs:$Vd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhsusat_acc_altAlias : InstAlias<"$Vx32+=vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhsusat_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhsusat_altAlias : InstAlias<"$Vd32=vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhsusat_alt_128BAlias : InstAlias<"$Vd32=vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhvsat_acc_altAlias : InstAlias<"$Vx32+=vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vdmpyhvsat_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vdmpyhvsat_altAlias : InstAlias<"$Vd32=vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vdmpyhvsat_alt_128BAlias : InstAlias<"$Vd32=vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vdsaduh_acc_altAlias : InstAlias<"$Vxx32+=vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdsaduh_acc_alt_128BAlias : InstAlias<"$Vxx32+=vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdsaduh_altAlias : InstAlias<"$Vdd32=vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdsaduh_alt_128BAlias : InstAlias<"$Vdd32=vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vlsrh_altAlias : InstAlias<"$Vd32=vlsrh($Vu32,$Rt32)", (V6_vlsrh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vlsrh_alt_128BAlias : InstAlias<"$Vd32=vlsrh($Vu32,$Rt32)", (V6_vlsrh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vlsrhv_altAlias : InstAlias<"$Vd32=vlsrh($Vu32,$Vv32)", (V6_vlsrhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vlsrhv_alt_128BAlias : InstAlias<"$Vd32=vlsrh($Vu32,$Vv32)", (V6_vlsrhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vlsrw_altAlias : InstAlias<"$Vd32=vlsrw($Vu32,$Rt32)", (V6_vlsrw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vlsrw_alt_128BAlias : InstAlias<"$Vd32=vlsrw($Vu32,$Rt32)", (V6_vlsrw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vlsrwv_altAlias : InstAlias<"$Vd32=vlsrw($Vu32,$Vv32)", (V6_vlsrwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vlsrwv_alt_128BAlias : InstAlias<"$Vd32=vlsrw($Vu32,$Vv32)", (V6_vlsrwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmaxh_altAlias : InstAlias<"$Vd32=vmaxh($Vu32,$Vv32)", (V6_vmaxh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmaxh_alt_128BAlias : InstAlias<"$Vd32=vmaxh($Vu32,$Vv32)", (V6_vmaxh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmaxub_altAlias : InstAlias<"$Vd32=vmaxub($Vu32,$Vv32)", (V6_vmaxub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmaxub_alt_128BAlias : InstAlias<"$Vd32=vmaxub($Vu32,$Vv32)", (V6_vmaxub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmaxuh_altAlias : InstAlias<"$Vd32=vmaxuh($Vu32,$Vv32)", (V6_vmaxuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmaxuh_alt_128BAlias : InstAlias<"$Vd32=vmaxuh($Vu32,$Vv32)", (V6_vmaxuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmaxw_altAlias : InstAlias<"$Vd32=vmaxw($Vu32,$Vv32)", (V6_vmaxw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmaxw_alt_128BAlias : InstAlias<"$Vd32=vmaxw($Vu32,$Vv32)", (V6_vmaxw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vminh_altAlias : InstAlias<"$Vd32=vminh($Vu32,$Vv32)", (V6_vminh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vminh_alt_128BAlias : InstAlias<"$Vd32=vminh($Vu32,$Vv32)", (V6_vminh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vminub_altAlias : InstAlias<"$Vd32=vminub($Vu32,$Vv32)", (V6_vminub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vminub_alt_128BAlias : InstAlias<"$Vd32=vminub($Vu32,$Vv32)", (V6_vminub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vminuh_altAlias : InstAlias<"$Vd32=vminuh($Vu32,$Vv32)", (V6_vminuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vminuh_alt_128BAlias : InstAlias<"$Vd32=vminuh($Vu32,$Vv32)", (V6_vminuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vminw_altAlias : InstAlias<"$Vd32=vminw($Vu32,$Vv32)", (V6_vminw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vminw_alt_128BAlias : InstAlias<"$Vd32=vminw($Vu32,$Vv32)", (V6_vminw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpabus_acc_altAlias : InstAlias<"$Vxx32+=vmpabus($Vuu32,$Rt32)", (V6_vmpabus_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpabus_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpabus($Vuu32,$Rt32)", (V6_vmpabus_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpabus_altAlias : InstAlias<"$Vdd32=vmpabus($Vuu32,$Rt32)", (V6_vmpabus VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpabus_alt_128BAlias : InstAlias<"$Vdd32=vmpabus($Vuu32,$Rt32)", (V6_vmpabus VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpabusv_altAlias : InstAlias<"$Vdd32=vmpabus($Vuu32,$Vvv32)", (V6_vmpabusv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vmpabusv_alt_128BAlias : InstAlias<"$Vdd32=vmpabus($Vuu32,$Vvv32)", (V6_vmpabusv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vmpabuuv_altAlias : InstAlias<"$Vdd32=vmpabuu($Vuu32,$Vvv32)", (V6_vmpabuuv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vmpabuuv_alt_128BAlias : InstAlias<"$Vdd32=vmpabuu($Vuu32,$Vvv32)", (V6_vmpabuuv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vmpahb_acc_altAlias : InstAlias<"$Vxx32+=vmpahb($Vuu32,$Rt32)", (V6_vmpahb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpahb_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpahb($Vuu32,$Rt32)", (V6_vmpahb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpahb_altAlias : InstAlias<"$Vdd32=vmpahb($Vuu32,$Rt32)", (V6_vmpahb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpahb_alt_128BAlias : InstAlias<"$Vdd32=vmpahb($Vuu32,$Rt32)", (V6_vmpahb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpybus_acc_altAlias : InstAlias<"$Vxx32+=vmpybus($Vu32,$Rt32)", (V6_vmpybus_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpybus_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpybus($Vu32,$Rt32)", (V6_vmpybus_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpybus_altAlias : InstAlias<"$Vdd32=vmpybus($Vu32,$Rt32)", (V6_vmpybus VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpybus_alt_128BAlias : InstAlias<"$Vdd32=vmpybus($Vu32,$Rt32)", (V6_vmpybus VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpybusv_acc_altAlias : InstAlias<"$Vxx32+=vmpybus($Vu32,$Vv32)", (V6_vmpybusv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpybusv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpybus($Vu32,$Vv32)", (V6_vmpybusv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpybusv_altAlias : InstAlias<"$Vdd32=vmpybus($Vu32,$Vv32)", (V6_vmpybusv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpybusv_alt_128BAlias : InstAlias<"$Vdd32=vmpybus($Vu32,$Vv32)", (V6_vmpybusv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpybv_acc_altAlias : InstAlias<"$Vxx32+=vmpyb($Vu32,$Vv32)", (V6_vmpybv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpybv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyb($Vu32,$Vv32)", (V6_vmpybv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpybv_altAlias : InstAlias<"$Vdd32=vmpyb($Vu32,$Vv32)", (V6_vmpybv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpybv_alt_128BAlias : InstAlias<"$Vdd32=vmpyb($Vu32,$Vv32)", (V6_vmpybv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyewuh_altAlias : InstAlias<"$Vd32=vmpyewuh($Vu32,$Vv32)", (V6_vmpyewuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyewuh_alt_128BAlias : InstAlias<"$Vd32=vmpyewuh($Vu32,$Vv32)", (V6_vmpyewuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyh_altAlias : InstAlias<"$Vdd32=vmpyh($Vu32,$Rt32)", (V6_vmpyh VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyh_alt_128BAlias : InstAlias<"$Vdd32=vmpyh($Vu32,$Rt32)", (V6_vmpyh VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyhsat_acc_altAlias : InstAlias<"$Vxx32+=vmpyh($Vu32,$Rt32):sat", (V6_vmpyhsat_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyhsat_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyh($Vu32,$Rt32):sat", (V6_vmpyhsat_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyhsrs_altAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Rt32):<<1:rnd:sat", (V6_vmpyhsrs VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyhsrs_alt_128BAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Rt32):<<1:rnd:sat", (V6_vmpyhsrs VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyhss_altAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Rt32):<<1:sat", (V6_vmpyhss VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyhss_alt_128BAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Rt32):<<1:sat", (V6_vmpyhss VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyhus_acc_altAlias : InstAlias<"$Vxx32+=vmpyhus($Vu32,$Vv32)", (V6_vmpyhus_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyhus_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyhus($Vu32,$Vv32)", (V6_vmpyhus_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyhus_altAlias : InstAlias<"$Vdd32=vmpyhus($Vu32,$Vv32)", (V6_vmpyhus VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyhus_alt_128BAlias : InstAlias<"$Vdd32=vmpyhus($Vu32,$Vv32)", (V6_vmpyhus VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyhv_acc_altAlias : InstAlias<"$Vxx32+=vmpyh($Vu32,$Vv32)", (V6_vmpyhv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyhv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyh($Vu32,$Vv32)", (V6_vmpyhv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyhv_altAlias : InstAlias<"$Vdd32=vmpyh($Vu32,$Vv32)", (V6_vmpyhv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyhv_alt_128BAlias : InstAlias<"$Vdd32=vmpyh($Vu32,$Vv32)", (V6_vmpyhv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyhvsrs_altAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyhvsrs VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyhvsrs_alt_128BAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyhvsrs VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyiewh_acc_altAlias : InstAlias<"$Vx32+=vmpyiewh($Vu32,$Vv32)", (V6_vmpyiewh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyiewh_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyiewh($Vu32,$Vv32)", (V6_vmpyiewh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyiewuh_acc_altAlias : InstAlias<"$Vx32+=vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyiewuh_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyiewuh_altAlias : InstAlias<"$Vd32=vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyiewuh_alt_128BAlias : InstAlias<"$Vd32=vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyih_acc_altAlias : InstAlias<"$Vx32+=vmpyih($Vu32,$Vv32)", (V6_vmpyih_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyih_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyih($Vu32,$Vv32)", (V6_vmpyih_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyih_altAlias : InstAlias<"$Vd32=vmpyih($Vu32,$Vv32)", (V6_vmpyih VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyih_alt_128BAlias : InstAlias<"$Vd32=vmpyih($Vu32,$Vv32)", (V6_vmpyih VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyihb_acc_altAlias : InstAlias<"$Vx32+=vmpyihb($Vu32,$Rt32)", (V6_vmpyihb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyihb_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyihb($Vu32,$Rt32)", (V6_vmpyihb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyihb_altAlias : InstAlias<"$Vd32=vmpyihb($Vu32,$Rt32)", (V6_vmpyihb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyihb_alt_128BAlias : InstAlias<"$Vd32=vmpyihb($Vu32,$Rt32)", (V6_vmpyihb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyiowh_altAlias : InstAlias<"$Vd32=vmpyiowh($Vu32,$Vv32)", (V6_vmpyiowh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyiowh_alt_128BAlias : InstAlias<"$Vd32=vmpyiowh($Vu32,$Vv32)", (V6_vmpyiowh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyiwb_acc_altAlias : InstAlias<"$Vx32+=vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyiwb_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyiwb_altAlias : InstAlias<"$Vd32=vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyiwb_alt_128BAlias : InstAlias<"$Vd32=vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyiwh_acc_altAlias : InstAlias<"$Vx32+=vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyiwh_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyiwh_altAlias : InstAlias<"$Vd32=vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyiwh_alt_128BAlias : InstAlias<"$Vd32=vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyowh_altAlias : InstAlias<"$Vd32=vmpyowh($Vu32,$Vv32):<<1:sat", (V6_vmpyowh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyowh_alt_128BAlias : InstAlias<"$Vd32=vmpyowh($Vu32,$Vv32):<<1:sat", (V6_vmpyowh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyowh_rnd_altAlias : InstAlias<"$Vd32=vmpyowh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyowh_rnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyowh_rnd_alt_128BAlias : InstAlias<"$Vd32=vmpyowh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyowh_rnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyub_acc_altAlias : InstAlias<"$Vxx32+=vmpyub($Vu32,$Rt32)", (V6_vmpyub_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyub_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyub($Vu32,$Rt32)", (V6_vmpyub_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyub_altAlias : InstAlias<"$Vdd32=vmpyub($Vu32,$Rt32)", (V6_vmpyub VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyub_alt_128BAlias : InstAlias<"$Vdd32=vmpyub($Vu32,$Rt32)", (V6_vmpyub VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyubv_acc_altAlias : InstAlias<"$Vxx32+=vmpyub($Vu32,$Vv32)", (V6_vmpyubv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyubv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyub($Vu32,$Vv32)", (V6_vmpyubv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyubv_altAlias : InstAlias<"$Vdd32=vmpyub($Vu32,$Vv32)", (V6_vmpyubv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyubv_alt_128BAlias : InstAlias<"$Vdd32=vmpyub($Vu32,$Vv32)", (V6_vmpyubv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyuh_acc_altAlias : InstAlias<"$Vxx32+=vmpyuh($Vu32,$Rt32)", (V6_vmpyuh_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyuh_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyuh($Vu32,$Rt32)", (V6_vmpyuh_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyuh_altAlias : InstAlias<"$Vdd32=vmpyuh($Vu32,$Rt32)", (V6_vmpyuh VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyuh_alt_128BAlias : InstAlias<"$Vdd32=vmpyuh($Vu32,$Rt32)", (V6_vmpyuh VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyuhv_acc_altAlias : InstAlias<"$Vxx32+=vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyuhv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyuhv_altAlias : InstAlias<"$Vdd32=vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyuhv_alt_128BAlias : InstAlias<"$Vdd32=vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vnavgh_altAlias : InstAlias<"$Vd32=vnavgh($Vu32,$Vv32)", (V6_vnavgh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vnavgh_alt_128BAlias : InstAlias<"$Vd32=vnavgh($Vu32,$Vv32)", (V6_vnavgh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vnavgub_altAlias : InstAlias<"$Vd32=vnavgub($Vu32,$Vv32)", (V6_vnavgub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vnavgub_alt_128BAlias : InstAlias<"$Vd32=vnavgub($Vu32,$Vv32)", (V6_vnavgub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vnavgw_altAlias : InstAlias<"$Vd32=vnavgw($Vu32,$Vv32)", (V6_vnavgw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vnavgw_alt_128BAlias : InstAlias<"$Vd32=vnavgw($Vu32,$Vv32)", (V6_vnavgw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vnormamth_altAlias : InstAlias<"$Vd32=vnormamth($Vu32)", (V6_vnormamth VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vnormamth_alt_128BAlias : InstAlias<"$Vd32=vnormamth($Vu32)", (V6_vnormamth VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vnormamtw_altAlias : InstAlias<"$Vd32=vnormamtw($Vu32)", (V6_vnormamtw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vnormamtw_alt_128BAlias : InstAlias<"$Vd32=vnormamtw($Vu32)", (V6_vnormamtw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vpackeb_altAlias : InstAlias<"$Vd32=vpackeb($Vu32,$Vv32)", (V6_vpackeb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackeb_alt_128BAlias : InstAlias<"$Vd32=vpackeb($Vu32,$Vv32)", (V6_vpackeb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackeh_altAlias : InstAlias<"$Vd32=vpackeh($Vu32,$Vv32)", (V6_vpackeh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackeh_alt_128BAlias : InstAlias<"$Vd32=vpackeh($Vu32,$Vv32)", (V6_vpackeh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackhb_sat_altAlias : InstAlias<"$Vd32=vpackhb($Vu32,$Vv32):sat", (V6_vpackhb_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackhb_sat_alt_128BAlias : InstAlias<"$Vd32=vpackhb($Vu32,$Vv32):sat", (V6_vpackhb_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackhub_sat_altAlias : InstAlias<"$Vd32=vpackhub($Vu32,$Vv32):sat", (V6_vpackhub_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackhub_sat_alt_128BAlias : InstAlias<"$Vd32=vpackhub($Vu32,$Vv32):sat", (V6_vpackhub_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackob_altAlias : InstAlias<"$Vd32=vpackob($Vu32,$Vv32)", (V6_vpackob VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackob_alt_128BAlias : InstAlias<"$Vd32=vpackob($Vu32,$Vv32)", (V6_vpackob VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackoh_altAlias : InstAlias<"$Vd32=vpackoh($Vu32,$Vv32)", (V6_vpackoh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackoh_alt_128BAlias : InstAlias<"$Vd32=vpackoh($Vu32,$Vv32)", (V6_vpackoh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackwh_sat_altAlias : InstAlias<"$Vd32=vpackwh($Vu32,$Vv32):sat", (V6_vpackwh_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackwh_sat_alt_128BAlias : InstAlias<"$Vd32=vpackwh($Vu32,$Vv32):sat", (V6_vpackwh_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackwuh_sat_altAlias : InstAlias<"$Vd32=vpackwuh($Vu32,$Vv32):sat", (V6_vpackwuh_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackwuh_sat_alt_128BAlias : InstAlias<"$Vd32=vpackwuh($Vu32,$Vv32):sat", (V6_vpackwuh_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpopcounth_altAlias : InstAlias<"$Vd32=vpopcounth($Vu32)", (V6_vpopcounth VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vpopcounth_alt_128BAlias : InstAlias<"$Vd32=vpopcounth($Vu32)", (V6_vpopcounth VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vrmpybus_acc_altAlias : InstAlias<"$Vx32+=vrmpybus($Vu32,$Rt32)", (V6_vrmpybus_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vrmpybus_acc_alt_128BAlias : InstAlias<"$Vx32+=vrmpybus($Vu32,$Rt32)", (V6_vrmpybus_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vrmpybus_altAlias : InstAlias<"$Vd32=vrmpybus($Vu32,$Rt32)", (V6_vrmpybus VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vrmpybus_alt_128BAlias : InstAlias<"$Vd32=vrmpybus($Vu32,$Rt32)", (V6_vrmpybus VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vrmpybusi_acc_altAlias : InstAlias<"$Vxx32+=vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; -def V6_vrmpybusi_acc_alt_128BAlias : InstAlias<"$Vxx32+=vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; -def V6_vrmpybusi_altAlias : InstAlias<"$Vdd32=vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; -def V6_vrmpybusi_alt_128BAlias : InstAlias<"$Vdd32=vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; -def V6_vrmpybusv_acc_altAlias : InstAlias<"$Vx32+=vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vrmpybusv_acc_alt_128BAlias : InstAlias<"$Vx32+=vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vrmpybusv_altAlias : InstAlias<"$Vd32=vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vrmpybusv_alt_128BAlias : InstAlias<"$Vd32=vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vrmpybv_acc_altAlias : InstAlias<"$Vx32+=vrmpyb($Vu32,$Vv32)", (V6_vrmpybv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vrmpybv_acc_alt_128BAlias : InstAlias<"$Vx32+=vrmpyb($Vu32,$Vv32)", (V6_vrmpybv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vrmpybv_altAlias : InstAlias<"$Vd32=vrmpyb($Vu32,$Vv32)", (V6_vrmpybv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vrmpybv_alt_128BAlias : InstAlias<"$Vd32=vrmpyb($Vu32,$Vv32)", (V6_vrmpybv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vrmpyub_acc_altAlias : InstAlias<"$Vx32+=vrmpyub($Vu32,$Rt32)", (V6_vrmpyub_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vrmpyub_acc_alt_128BAlias : InstAlias<"$Vx32+=vrmpyub($Vu32,$Rt32)", (V6_vrmpyub_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vrmpyub_altAlias : InstAlias<"$Vd32=vrmpyub($Vu32,$Rt32)", (V6_vrmpyub VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vrmpyub_alt_128BAlias : InstAlias<"$Vd32=vrmpyub($Vu32,$Rt32)", (V6_vrmpyub VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vrmpyubi_acc_altAlias : InstAlias<"$Vxx32+=vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; -def V6_vrmpyubi_acc_alt_128BAlias : InstAlias<"$Vxx32+=vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; -def V6_vrmpyubi_altAlias : InstAlias<"$Vdd32=vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; -def V6_vrmpyubi_alt_128BAlias : InstAlias<"$Vdd32=vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; -def V6_vrmpyubv_acc_altAlias : InstAlias<"$Vx32+=vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vrmpyubv_acc_alt_128BAlias : InstAlias<"$Vx32+=vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vrmpyubv_altAlias : InstAlias<"$Vd32=vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vrmpyubv_alt_128BAlias : InstAlias<"$Vd32=vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vroundhb_altAlias : InstAlias<"$Vd32=vroundhb($Vu32,$Vv32):sat", (V6_vroundhb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vroundhb_alt_128BAlias : InstAlias<"$Vd32=vroundhb($Vu32,$Vv32):sat", (V6_vroundhb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vroundhub_altAlias : InstAlias<"$Vd32=vroundhub($Vu32,$Vv32):sat", (V6_vroundhub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vroundhub_alt_128BAlias : InstAlias<"$Vd32=vroundhub($Vu32,$Vv32):sat", (V6_vroundhub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vroundwh_altAlias : InstAlias<"$Vd32=vroundwh($Vu32,$Vv32):sat", (V6_vroundwh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vroundwh_alt_128BAlias : InstAlias<"$Vd32=vroundwh($Vu32,$Vv32):sat", (V6_vroundwh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vroundwuh_altAlias : InstAlias<"$Vd32=vroundwuh($Vu32,$Vv32):sat", (V6_vroundwuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vroundwuh_alt_128BAlias : InstAlias<"$Vd32=vroundwuh($Vu32,$Vv32):sat", (V6_vroundwuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vrsadubi_acc_altAlias : InstAlias<"$Vxx32+=vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; -def V6_vrsadubi_acc_alt_128BAlias : InstAlias<"$Vxx32+=vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; -def V6_vrsadubi_altAlias : InstAlias<"$Vdd32=vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; -def V6_vrsadubi_alt_128BAlias : InstAlias<"$Vdd32=vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; -def V6_vsathub_altAlias : InstAlias<"$Vd32=vsathub($Vu32,$Vv32)", (V6_vsathub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsathub_alt_128BAlias : InstAlias<"$Vd32=vsathub($Vu32,$Vv32)", (V6_vsathub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsatwh_altAlias : InstAlias<"$Vd32=vsatwh($Vu32,$Vv32)", (V6_vsatwh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsatwh_alt_128BAlias : InstAlias<"$Vd32=vsatwh($Vu32,$Vv32)", (V6_vsatwh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsb_altAlias : InstAlias<"$Vdd32=vsxtb($Vu32)", (V6_vsb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vsb_alt_128BAlias : InstAlias<"$Vdd32=vsxtb($Vu32)", (V6_vsb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vsh_altAlias : InstAlias<"$Vdd32=vsxth($Vu32)", (V6_vsh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vsh_alt_128BAlias : InstAlias<"$Vdd32=vsxth($Vu32)", (V6_vsh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vshufeh_altAlias : InstAlias<"$Vd32=vshuffeh($Vu32,$Vv32)", (V6_vshufeh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vshufeh_alt_128BAlias : InstAlias<"$Vd32=vshuffeh($Vu32,$Vv32)", (V6_vshufeh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vshuffb_altAlias : InstAlias<"$Vd32=vshuffb($Vu32)", (V6_vshuffb VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vshuffb_alt_128BAlias : InstAlias<"$Vd32=vshuffb($Vu32)", (V6_vshuffb VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vshuffeb_altAlias : InstAlias<"$Vd32=vshuffeb($Vu32,$Vv32)", (V6_vshuffeb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vshuffeb_alt_128BAlias : InstAlias<"$Vd32=vshuffeb($Vu32,$Vv32)", (V6_vshuffeb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vshuffh_altAlias : InstAlias<"$Vd32=vshuffh($Vu32)", (V6_vshuffh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vshuffh_alt_128BAlias : InstAlias<"$Vd32=vshuffh($Vu32)", (V6_vshuffh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vshuffob_altAlias : InstAlias<"$Vd32=vshuffob($Vu32,$Vv32)", (V6_vshuffob VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vshuffob_alt_128BAlias : InstAlias<"$Vd32=vshuffob($Vu32,$Vv32)", (V6_vshuffob VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vshufoeb_altAlias : InstAlias<"$Vdd32=vshuffoeb($Vu32,$Vv32)", (V6_vshufoeb VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vshufoeb_alt_128BAlias : InstAlias<"$Vdd32=vshuffoeb($Vu32,$Vv32)", (V6_vshufoeb VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vshufoeh_altAlias : InstAlias<"$Vdd32=vshuffoeh($Vu32,$Vv32)", (V6_vshufoeh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vshufoeh_alt_128BAlias : InstAlias<"$Vdd32=vshuffoeh($Vu32,$Vv32)", (V6_vshufoeh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vshufoh_altAlias : InstAlias<"$Vd32=vshuffoh($Vu32,$Vv32)", (V6_vshufoh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vshufoh_alt_128BAlias : InstAlias<"$Vd32=vshuffoh($Vu32,$Vv32)", (V6_vshufoh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubb_altAlias : InstAlias<"$Vd32=vsubb($Vu32,$Vv32)", (V6_vsubb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubb_alt_128BAlias : InstAlias<"$Vd32=vsubb($Vu32,$Vv32)", (V6_vsubb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubb_dv_altAlias : InstAlias<"$Vdd32=vsubb($Vuu32,$Vvv32)", (V6_vsubb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsubb_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubb($Vuu32,$Vvv32)", (V6_vsubb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsubbnq_altAlias : InstAlias<"if (!$Qv4.b) $Vx32.b-=$Vu32.b", (V6_vsubbnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vsubbnq_alt_128BAlias : InstAlias<"if (!$Qv4.b) $Vx32.b-=$Vu32.b", (V6_vsubbnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vsubbq_altAlias : InstAlias<"if ($Qv4.b) $Vx32.b-=$Vu32.b", (V6_vsubbq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vsubbq_alt_128BAlias : InstAlias<"if ($Qv4.b) $Vx32.b-=$Vu32.b", (V6_vsubbq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vsubh_altAlias : InstAlias<"$Vd32=vsubh($Vu32,$Vv32)", (V6_vsubh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubh_alt_128BAlias : InstAlias<"$Vd32=vsubh($Vu32,$Vv32)", (V6_vsubh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubh_dv_altAlias : InstAlias<"$Vdd32=vsubh($Vuu32,$Vvv32)", (V6_vsubh_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsubh_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubh($Vuu32,$Vvv32)", (V6_vsubh_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsubhnq_altAlias : InstAlias<"if (!$Qv4.h) $Vx32.h-=$Vu32.h", (V6_vsubhnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vsubhnq_alt_128BAlias : InstAlias<"if (!$Qv4.h) $Vx32.h-=$Vu32.h", (V6_vsubhnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vsubhq_altAlias : InstAlias<"if ($Qv4.h) $Vx32.h-=$Vu32.h", (V6_vsubhq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vsubhq_alt_128BAlias : InstAlias<"if ($Qv4.h) $Vx32.h-=$Vu32.h", (V6_vsubhq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vsubhsat_altAlias : InstAlias<"$Vd32=vsubh($Vu32,$Vv32):sat", (V6_vsubhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubhsat_alt_128BAlias : InstAlias<"$Vd32=vsubh($Vu32,$Vv32):sat", (V6_vsubhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubhsat_dv_altAlias : InstAlias<"$Vdd32=vsubh($Vuu32,$Vvv32):sat", (V6_vsubhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsubhsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubh($Vuu32,$Vvv32):sat", (V6_vsubhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsubhw_altAlias : InstAlias<"$Vdd32=vsubh($Vu32,$Vv32)", (V6_vsubhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubhw_alt_128BAlias : InstAlias<"$Vdd32=vsubh($Vu32,$Vv32)", (V6_vsubhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsububh_altAlias : InstAlias<"$Vdd32=vsubub($Vu32,$Vv32)", (V6_vsububh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsububh_alt_128BAlias : InstAlias<"$Vdd32=vsubub($Vu32,$Vv32)", (V6_vsububh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsububsat_altAlias : InstAlias<"$Vd32=vsubub($Vu32,$Vv32):sat", (V6_vsububsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsububsat_alt_128BAlias : InstAlias<"$Vd32=vsubub($Vu32,$Vv32):sat", (V6_vsububsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsububsat_dv_altAlias : InstAlias<"$Vdd32=vsubub($Vuu32,$Vvv32):sat", (V6_vsububsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsububsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubub($Vuu32,$Vvv32):sat", (V6_vsububsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsubuhsat_altAlias : InstAlias<"$Vd32=vsubuh($Vu32,$Vv32):sat", (V6_vsubuhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubuhsat_alt_128BAlias : InstAlias<"$Vd32=vsubuh($Vu32,$Vv32):sat", (V6_vsubuhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubuhsat_dv_altAlias : InstAlias<"$Vdd32=vsubuh($Vuu32,$Vvv32):sat", (V6_vsubuhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsubuhsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubuh($Vuu32,$Vvv32):sat", (V6_vsubuhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsubuhw_altAlias : InstAlias<"$Vdd32=vsubuh($Vu32,$Vv32)", (V6_vsubuhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubuhw_alt_128BAlias : InstAlias<"$Vdd32=vsubuh($Vu32,$Vv32)", (V6_vsubuhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubw_altAlias : InstAlias<"$Vd32=vsubw($Vu32,$Vv32)", (V6_vsubw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubw_alt_128BAlias : InstAlias<"$Vd32=vsubw($Vu32,$Vv32)", (V6_vsubw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubw_dv_altAlias : InstAlias<"$Vdd32=vsubw($Vuu32,$Vvv32)", (V6_vsubw_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsubw_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubw($Vuu32,$Vvv32)", (V6_vsubw_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsubwnq_altAlias : InstAlias<"if (!$Qv4.w) $Vx32.w-=$Vu32.w", (V6_vsubwnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vsubwnq_alt_128BAlias : InstAlias<"if (!$Qv4.w) $Vx32.w-=$Vu32.w", (V6_vsubwnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vsubwq_altAlias : InstAlias<"if ($Qv4.w) $Vx32.w-=$Vu32.w", (V6_vsubwq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vsubwq_alt_128BAlias : InstAlias<"if ($Qv4.w) $Vx32.w-=$Vu32.w", (V6_vsubwq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vsubwsat_altAlias : InstAlias<"$Vd32=vsubw($Vu32,$Vv32):sat", (V6_vsubwsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubwsat_alt_128BAlias : InstAlias<"$Vd32=vsubw($Vu32,$Vv32):sat", (V6_vsubwsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubwsat_dv_altAlias : InstAlias<"$Vdd32=vsubw($Vuu32,$Vvv32):sat", (V6_vsubwsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsubwsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubw($Vuu32,$Vvv32):sat", (V6_vsubwsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vtmpyb_acc_altAlias : InstAlias<"$Vxx32+=vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtmpyb_acc_alt_128BAlias : InstAlias<"$Vxx32+=vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtmpyb_altAlias : InstAlias<"$Vdd32=vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtmpyb_alt_128BAlias : InstAlias<"$Vdd32=vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtmpybus_acc_altAlias : InstAlias<"$Vxx32+=vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtmpybus_acc_alt_128BAlias : InstAlias<"$Vxx32+=vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtmpybus_altAlias : InstAlias<"$Vdd32=vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtmpybus_alt_128BAlias : InstAlias<"$Vdd32=vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtmpyhb_acc_altAlias : InstAlias<"$Vxx32+=vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtmpyhb_acc_alt_128BAlias : InstAlias<"$Vxx32+=vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtmpyhb_altAlias : InstAlias<"$Vdd32=vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtmpyhb_alt_128BAlias : InstAlias<"$Vdd32=vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtran2x2_mapAlias : InstAlias<"vtrans2x2($Vy32,$Vx32,$Rt32)", (V6_vshuff VectorRegs:$Vy32, VectorRegs:$Vx32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtran2x2_map_128BAlias : InstAlias<"vtrans2x2($Vy32,$Vx32,$Rt32)", (V6_vshuff VectorRegs:$Vy32, VectorRegs:$Vx32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vunpackb_altAlias : InstAlias<"$Vdd32=vunpackb($Vu32)", (V6_vunpackb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vunpackb_alt_128BAlias : InstAlias<"$Vdd32=vunpackb($Vu32)", (V6_vunpackb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vunpackh_altAlias : InstAlias<"$Vdd32=vunpackh($Vu32)", (V6_vunpackh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vunpackh_alt_128BAlias : InstAlias<"$Vdd32=vunpackh($Vu32)", (V6_vunpackh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vunpackoh_altAlias : InstAlias<"$Vxx32|=vunpackoh($Vu32)", (V6_vunpackoh VecDblRegs:$Vxx32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vunpackoh_alt_128BAlias : InstAlias<"$Vxx32|=vunpackoh($Vu32)", (V6_vunpackoh VecDblRegs:$Vxx32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vunpackub_altAlias : InstAlias<"$Vdd32=vunpackub($Vu32)", (V6_vunpackub VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vunpackub_alt_128BAlias : InstAlias<"$Vdd32=vunpackub($Vu32)", (V6_vunpackub VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vunpackuh_altAlias : InstAlias<"$Vdd32=vunpackuh($Vu32)", (V6_vunpackuh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vunpackuh_alt_128BAlias : InstAlias<"$Vdd32=vunpackuh($Vu32)", (V6_vunpackuh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vzb_altAlias : InstAlias<"$Vdd32=vzxtb($Vu32)", (V6_vzb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vzb_alt_128BAlias : InstAlias<"$Vdd32=vzxtb($Vu32)", (V6_vzb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vzh_altAlias : InstAlias<"$Vdd32=vzxth($Vu32)", (V6_vzh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vzh_alt_128BAlias : InstAlias<"$Vdd32=vzxth($Vu32)", (V6_vzh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_MAP_equbAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb HvxQR:$Qd4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equb_andAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equb_iorAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_or HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equb_xorAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_xor HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equhAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh HvxQR:$Qd4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equh_andAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equh_iorAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_or HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equh_xorAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_xor HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equwAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw HvxQR:$Qd4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equw_andAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equw_iorAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_or HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equw_xorAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_xor HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_extractw_altAlias : InstAlias<"$Rd32.w=vextract($Vu32,$Rs32)", (V6_extractw IntRegs:$Rd32, HvxVR:$Vu32, IntRegs:$Rs32)>, Requires<[UseHVX]>; +def V6_ld0Alias : InstAlias<"$Vd32=vmem($Rt32)", (V6_vL32b_ai HvxVR:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; +def V6_ldnt0Alias : InstAlias<"$Vd32=vmem($Rt32):nt", (V6_vL32b_nt_ai HvxVR:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; +def V6_ldu0Alias : InstAlias<"$Vd32=vmemu($Rt32)", (V6_vL32Ub_ai HvxVR:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; +def V6_st0Alias : InstAlias<"vmem($Rt32)=$Vs32", (V6_vS32b_ai IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stn0Alias : InstAlias<"vmem($Rt32)=$Os8.new", (V6_vS32b_new_ai IntRegs:$Rt32, 0, HvxVR:$Os8)>, Requires<[UseHVX]>; +def V6_stnnt0Alias : InstAlias<"vmem($Rt32):nt=$Os8.new", (V6_vS32b_nt_new_ai IntRegs:$Rt32, 0, HvxVR:$Os8)>, Requires<[UseHVX]>; +def V6_stnp0Alias : InstAlias<"if (!$Pv4) vmem($Rt32)=$Vs32", (V6_vS32b_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stnpnt0Alias : InstAlias<"if (!$Pv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stnq0Alias : InstAlias<"if (!$Qv4) vmem($Rt32)=$Vs32", (V6_vS32b_nqpred_ai HvxQR:$Qv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stnqnt0Alias : InstAlias<"if (!$Qv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_nqpred_ai HvxQR:$Qv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stnt0Alias : InstAlias<"vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_ai IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stp0Alias : InstAlias<"if ($Pv4) vmem($Rt32)=$Vs32", (V6_vS32b_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stpnt0Alias : InstAlias<"if ($Pv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stq0Alias : InstAlias<"if ($Qv4) vmem($Rt32)=$Vs32", (V6_vS32b_qpred_ai HvxQR:$Qv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stqnt0Alias : InstAlias<"if ($Qv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_qpred_ai HvxQR:$Qv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stu0Alias : InstAlias<"vmemu($Rt32)=$Vs32", (V6_vS32Ub_ai IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stunp0Alias : InstAlias<"if (!$Pv4) vmemu($Rt32)=$Vs32", (V6_vS32Ub_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stup0Alias : InstAlias<"if ($Pv4) vmemu($Rt32)=$Vs32", (V6_vS32Ub_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_vabsdiffh_altAlias : InstAlias<"$Vd32=vabsdiffh($Vu32,$Vv32)", (V6_vabsdiffh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vabsdiffub_altAlias : InstAlias<"$Vd32=vabsdiffub($Vu32,$Vv32)", (V6_vabsdiffub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vabsdiffuh_altAlias : InstAlias<"$Vd32=vabsdiffuh($Vu32,$Vv32)", (V6_vabsdiffuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vabsdiffw_altAlias : InstAlias<"$Vd32=vabsdiffw($Vu32,$Vv32)", (V6_vabsdiffw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vabsh_altAlias : InstAlias<"$Vd32=vabsh($Vu32)", (V6_vabsh HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsh_sat_altAlias : InstAlias<"$Vd32=vabsh($Vu32):sat", (V6_vabsh_sat HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsuh_altAlias : InstAlias<"$Vd32.uh=vabs($Vu32.h)", (V6_vabsh HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsuw_altAlias : InstAlias<"$Vd32.uw=vabs($Vu32.w)", (V6_vabsw HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsw_altAlias : InstAlias<"$Vd32=vabsw($Vu32)", (V6_vabsw HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsw_sat_altAlias : InstAlias<"$Vd32=vabsw($Vu32):sat", (V6_vabsw_sat HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddb_altAlias : InstAlias<"$Vd32=vaddb($Vu32,$Vv32)", (V6_vaddb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddb_dv_altAlias : InstAlias<"$Vdd32=vaddb($Vuu32,$Vvv32)", (V6_vaddb_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddbnq_altAlias : InstAlias<"if (!$Qv4.b) $Vx32.b+=$Vu32.b", (V6_vaddbnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddbq_altAlias : InstAlias<"if ($Qv4.b) $Vx32.b+=$Vu32.b", (V6_vaddbq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddh_altAlias : InstAlias<"$Vd32=vaddh($Vu32,$Vv32)", (V6_vaddh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddh_dv_altAlias : InstAlias<"$Vdd32=vaddh($Vuu32,$Vvv32)", (V6_vaddh_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddhnq_altAlias : InstAlias<"if (!$Qv4.h) $Vx32.h+=$Vu32.h", (V6_vaddhnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddhq_altAlias : InstAlias<"if ($Qv4.h) $Vx32.h+=$Vu32.h", (V6_vaddhq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddhsat_altAlias : InstAlias<"$Vd32=vaddh($Vu32,$Vv32):sat", (V6_vaddhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddhsat_dv_altAlias : InstAlias<"$Vdd32=vaddh($Vuu32,$Vvv32):sat", (V6_vaddhsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddhw_altAlias : InstAlias<"$Vdd32=vaddh($Vu32,$Vv32)", (V6_vaddhw HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddubh_altAlias : InstAlias<"$Vdd32=vaddub($Vu32,$Vv32)", (V6_vaddubh HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddubsat_altAlias : InstAlias<"$Vd32=vaddub($Vu32,$Vv32):sat", (V6_vaddubsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddubsat_dv_altAlias : InstAlias<"$Vdd32=vaddub($Vuu32,$Vvv32):sat", (V6_vaddubsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vadduhsat_altAlias : InstAlias<"$Vd32=vadduh($Vu32,$Vv32):sat", (V6_vadduhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vadduhsat_dv_altAlias : InstAlias<"$Vdd32=vadduh($Vuu32,$Vvv32):sat", (V6_vadduhsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vadduhw_altAlias : InstAlias<"$Vdd32=vadduh($Vu32,$Vv32)", (V6_vadduhw HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddw_altAlias : InstAlias<"$Vd32=vaddw($Vu32,$Vv32)", (V6_vaddw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddw_dv_altAlias : InstAlias<"$Vdd32=vaddw($Vuu32,$Vvv32)", (V6_vaddw_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddwnq_altAlias : InstAlias<"if (!$Qv4.w) $Vx32.w+=$Vu32.w", (V6_vaddwnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddwq_altAlias : InstAlias<"if ($Qv4.w) $Vx32.w+=$Vu32.w", (V6_vaddwq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddwsat_altAlias : InstAlias<"$Vd32=vaddw($Vu32,$Vv32):sat", (V6_vaddwsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddwsat_dv_altAlias : InstAlias<"$Vdd32=vaddw($Vuu32,$Vvv32):sat", (V6_vaddwsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vandqrt_acc_altAlias : InstAlias<"$Vx32.ub|=vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt_acc HvxVR:$Vx32, HvxQR:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vandqrt_altAlias : InstAlias<"$Vd32.ub=vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt HvxVR:$Vd32, HvxQR:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vandvrt_acc_altAlias : InstAlias<"$Qx4.ub|=vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt_acc HvxQR:$Qx4, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vandvrt_altAlias : InstAlias<"$Qd4.ub=vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt HvxQR:$Qd4, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vaslh_altAlias : InstAlias<"$Vd32=vaslh($Vu32,$Rt32)", (V6_vaslh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vaslhv_altAlias : InstAlias<"$Vd32=vaslh($Vu32,$Vv32)", (V6_vaslhv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaslw_acc_altAlias : InstAlias<"$Vx32+=vaslw($Vu32,$Rt32)", (V6_vaslw_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vaslw_altAlias : InstAlias<"$Vd32=vaslw($Vu32,$Rt32)", (V6_vaslw HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vaslwv_altAlias : InstAlias<"$Vd32=vaslw($Vu32,$Vv32)", (V6_vaslwv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vasrh_altAlias : InstAlias<"$Vd32=vasrh($Vu32,$Rt32)", (V6_vasrh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vasrhbrndsat_altAlias : InstAlias<"$Vd32=vasrhb($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrhbrndsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrhubrndsat_altAlias : InstAlias<"$Vd32=vasrhub($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrhubrndsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrhubsat_altAlias : InstAlias<"$Vd32=vasrhub($Vu32,$Vv32,$Rt8):sat", (V6_vasrhubsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrhv_altAlias : InstAlias<"$Vd32=vasrh($Vu32,$Vv32)", (V6_vasrhv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vasrw_acc_altAlias : InstAlias<"$Vx32+=vasrw($Vu32,$Rt32)", (V6_vasrw_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vasrw_altAlias : InstAlias<"$Vd32=vasrw($Vu32,$Rt32)", (V6_vasrw HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vasrwh_altAlias : InstAlias<"$Vd32=vasrwh($Vu32,$Vv32,$Rt8)", (V6_vasrwhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrwhrndsat_altAlias : InstAlias<"$Vd32=vasrwh($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrwhrndsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrwhsat_altAlias : InstAlias<"$Vd32=vasrwh($Vu32,$Vv32,$Rt8):sat", (V6_vasrwhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrwuhsat_altAlias : InstAlias<"$Vd32=vasrwuh($Vu32,$Vv32,$Rt8):sat", (V6_vasrwuhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrwv_altAlias : InstAlias<"$Vd32=vasrw($Vu32,$Vv32)", (V6_vasrwv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgh_altAlias : InstAlias<"$Vd32=vavgh($Vu32,$Vv32)", (V6_vavgh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vavghrnd_altAlias : InstAlias<"$Vd32=vavgh($Vu32,$Vv32):rnd", (V6_vavghrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgub_altAlias : InstAlias<"$Vd32=vavgub($Vu32,$Vv32)", (V6_vavgub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgubrnd_altAlias : InstAlias<"$Vd32=vavgub($Vu32,$Vv32):rnd", (V6_vavgubrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vavguh_altAlias : InstAlias<"$Vd32=vavguh($Vu32,$Vv32)", (V6_vavguh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vavguhrnd_altAlias : InstAlias<"$Vd32=vavguh($Vu32,$Vv32):rnd", (V6_vavguhrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgw_altAlias : InstAlias<"$Vd32=vavgw($Vu32,$Vv32)", (V6_vavgw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgwrnd_altAlias : InstAlias<"$Vd32=vavgw($Vu32,$Vv32):rnd", (V6_vavgwrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vcl0h_altAlias : InstAlias<"$Vd32=vcl0h($Vu32)", (V6_vcl0h HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vcl0w_altAlias : InstAlias<"$Vd32=vcl0w($Vu32)", (V6_vcl0w HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vd0Alias : InstAlias<"$Vd32=#0", (V6_vxor HvxVR:$Vd32, HvxVR:$Vd32, HvxVR:$Vd32)>, Requires<[UseHVX]>; +def V6_vdd0Alias : InstAlias<"$Vdd32=#0", (V6_vsubw_dv HvxWR:$Vdd32, W15, W15)>, Requires<[UseHVX]>; +def V6_vdealb4w_altAlias : InstAlias<"$Vd32=vdealb4w($Vu32,$Vv32)", (V6_vdealb4w HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vdealb_altAlias : InstAlias<"$Vd32=vdealb($Vu32)", (V6_vdealb HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vdealh_altAlias : InstAlias<"$Vd32=vdealh($Vu32)", (V6_vdealh HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vdmpybus_acc_altAlias : InstAlias<"$Vx32+=vdmpybus($Vu32,$Rt32)", (V6_vdmpybus_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpybus_altAlias : InstAlias<"$Vd32=vdmpybus($Vu32,$Rt32)", (V6_vdmpybus HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpybus_dv_acc_altAlias : InstAlias<"$Vxx32+=vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpybus_dv_altAlias : InstAlias<"$Vdd32=vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhb_acc_altAlias : InstAlias<"$Vx32+=vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhb_altAlias : InstAlias<"$Vd32=vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhb_dv_acc_altAlias : InstAlias<"$Vxx32+=vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhb_dv_altAlias : InstAlias<"$Vdd32=vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhisat_acc_altAlias : InstAlias<"$Vx32+=vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat_acc HvxVR:$Vx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhisat_altAlias : InstAlias<"$Vd32=vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat HvxVR:$Vd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsat_acc_altAlias : InstAlias<"$Vx32+=vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsat_altAlias : InstAlias<"$Vd32=vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsuisat_acc_altAlias : InstAlias<"$Vx32+=vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat_acc HvxVR:$Vx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsuisat_altAlias : InstAlias<"$Vd32=vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat HvxVR:$Vd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsusat_acc_altAlias : InstAlias<"$Vx32+=vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsusat_altAlias : InstAlias<"$Vd32=vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhvsat_acc_altAlias : InstAlias<"$Vx32+=vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vdmpyhvsat_altAlias : InstAlias<"$Vd32=vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vdsaduh_acc_altAlias : InstAlias<"$Vxx32+=vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdsaduh_altAlias : InstAlias<"$Vdd32=vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vlsrh_altAlias : InstAlias<"$Vd32=vlsrh($Vu32,$Rt32)", (V6_vlsrh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vlsrhv_altAlias : InstAlias<"$Vd32=vlsrh($Vu32,$Vv32)", (V6_vlsrhv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vlsrw_altAlias : InstAlias<"$Vd32=vlsrw($Vu32,$Rt32)", (V6_vlsrw HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vlsrwv_altAlias : InstAlias<"$Vd32=vlsrw($Vu32,$Vv32)", (V6_vlsrwv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmaxh_altAlias : InstAlias<"$Vd32=vmaxh($Vu32,$Vv32)", (V6_vmaxh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmaxub_altAlias : InstAlias<"$Vd32=vmaxub($Vu32,$Vv32)", (V6_vmaxub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmaxuh_altAlias : InstAlias<"$Vd32=vmaxuh($Vu32,$Vv32)", (V6_vmaxuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmaxw_altAlias : InstAlias<"$Vd32=vmaxw($Vu32,$Vv32)", (V6_vmaxw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vminh_altAlias : InstAlias<"$Vd32=vminh($Vu32,$Vv32)", (V6_vminh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vminub_altAlias : InstAlias<"$Vd32=vminub($Vu32,$Vv32)", (V6_vminub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vminuh_altAlias : InstAlias<"$Vd32=vminuh($Vu32,$Vv32)", (V6_vminuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vminw_altAlias : InstAlias<"$Vd32=vminw($Vu32,$Vv32)", (V6_vminw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpabus_acc_altAlias : InstAlias<"$Vxx32+=vmpabus($Vuu32,$Rt32)", (V6_vmpabus_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpabus_altAlias : InstAlias<"$Vdd32=vmpabus($Vuu32,$Rt32)", (V6_vmpabus HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpabusv_altAlias : InstAlias<"$Vdd32=vmpabus($Vuu32,$Vvv32)", (V6_vmpabusv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vmpabuuv_altAlias : InstAlias<"$Vdd32=vmpabuu($Vuu32,$Vvv32)", (V6_vmpabuuv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vmpahb_acc_altAlias : InstAlias<"$Vxx32+=vmpahb($Vuu32,$Rt32)", (V6_vmpahb_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpahb_altAlias : InstAlias<"$Vdd32=vmpahb($Vuu32,$Rt32)", (V6_vmpahb HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpybus_acc_altAlias : InstAlias<"$Vxx32+=vmpybus($Vu32,$Rt32)", (V6_vmpybus_acc HvxWR:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpybus_altAlias : InstAlias<"$Vdd32=vmpybus($Vu32,$Rt32)", (V6_vmpybus HvxWR:$Vdd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpybusv_acc_altAlias : InstAlias<"$Vxx32+=vmpybus($Vu32,$Vv32)", (V6_vmpybusv_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpybusv_altAlias : InstAlias<"$Vdd32=vmpybus($Vu32,$Vv32)", (V6_vmpybusv HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpybv_acc_altAlias : InstAlias<"$Vxx32+=vmpyb($Vu32,$Vv32)", (V6_vmpybv_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpybv_altAlias : InstAlias<"$Vdd32=vmpyb($Vu32,$Vv32)", (V6_vmpybv HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyewuh_altAlias : InstAlias<"$Vd32=vmpyewuh($Vu32,$Vv32)", (V6_vmpyewuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyh_altAlias : InstAlias<"$Vdd32=vmpyh($Vu32,$Rt32)", (V6_vmpyh HvxWR:$Vdd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyhsat_acc_altAlias : InstAlias<"$Vxx32+=vmpyh($Vu32,$Rt32):sat", (V6_vmpyhsat_acc HvxWR:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyhsrs_altAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Rt32):<<1:rnd:sat", (V6_vmpyhsrs HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyhss_altAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Rt32):<<1:sat", (V6_vmpyhss HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyhus_acc_altAlias : InstAlias<"$Vxx32+=vmpyhus($Vu32,$Vv32)", (V6_vmpyhus_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyhus_altAlias : InstAlias<"$Vdd32=vmpyhus($Vu32,$Vv32)", (V6_vmpyhus HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyhv_acc_altAlias : InstAlias<"$Vxx32+=vmpyh($Vu32,$Vv32)", (V6_vmpyhv_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyhv_altAlias : InstAlias<"$Vdd32=vmpyh($Vu32,$Vv32)", (V6_vmpyhv HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyhvsrs_altAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyhvsrs HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyiewh_acc_altAlias : InstAlias<"$Vx32+=vmpyiewh($Vu32,$Vv32)", (V6_vmpyiewh_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyiewuh_acc_altAlias : InstAlias<"$Vx32+=vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyiewuh_altAlias : InstAlias<"$Vd32=vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyih_acc_altAlias : InstAlias<"$Vx32+=vmpyih($Vu32,$Vv32)", (V6_vmpyih_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyih_altAlias : InstAlias<"$Vd32=vmpyih($Vu32,$Vv32)", (V6_vmpyih HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyihb_acc_altAlias : InstAlias<"$Vx32+=vmpyihb($Vu32,$Rt32)", (V6_vmpyihb_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyihb_altAlias : InstAlias<"$Vd32=vmpyihb($Vu32,$Rt32)", (V6_vmpyihb HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyiowh_altAlias : InstAlias<"$Vd32=vmpyiowh($Vu32,$Vv32)", (V6_vmpyiowh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyiwb_acc_altAlias : InstAlias<"$Vx32+=vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyiwb_altAlias : InstAlias<"$Vd32=vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyiwh_acc_altAlias : InstAlias<"$Vx32+=vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyiwh_altAlias : InstAlias<"$Vd32=vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyowh_altAlias : InstAlias<"$Vd32=vmpyowh($Vu32,$Vv32):<<1:sat", (V6_vmpyowh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyowh_rnd_altAlias : InstAlias<"$Vd32=vmpyowh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyowh_rnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyub_acc_altAlias : InstAlias<"$Vxx32+=vmpyub($Vu32,$Rt32)", (V6_vmpyub_acc HvxWR:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyub_altAlias : InstAlias<"$Vdd32=vmpyub($Vu32,$Rt32)", (V6_vmpyub HvxWR:$Vdd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyubv_acc_altAlias : InstAlias<"$Vxx32+=vmpyub($Vu32,$Vv32)", (V6_vmpyubv_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyubv_altAlias : InstAlias<"$Vdd32=vmpyub($Vu32,$Vv32)", (V6_vmpyubv HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyuh_acc_altAlias : InstAlias<"$Vxx32+=vmpyuh($Vu32,$Rt32)", (V6_vmpyuh_acc HvxWR:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyuh_altAlias : InstAlias<"$Vdd32=vmpyuh($Vu32,$Rt32)", (V6_vmpyuh HvxWR:$Vdd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyuhv_acc_altAlias : InstAlias<"$Vxx32+=vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyuhv_altAlias : InstAlias<"$Vdd32=vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vnavgh_altAlias : InstAlias<"$Vd32=vnavgh($Vu32,$Vv32)", (V6_vnavgh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vnavgub_altAlias : InstAlias<"$Vd32=vnavgub($Vu32,$Vv32)", (V6_vnavgub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vnavgw_altAlias : InstAlias<"$Vd32=vnavgw($Vu32,$Vv32)", (V6_vnavgw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vnormamth_altAlias : InstAlias<"$Vd32=vnormamth($Vu32)", (V6_vnormamth HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vnormamtw_altAlias : InstAlias<"$Vd32=vnormamtw($Vu32)", (V6_vnormamtw HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vpackeb_altAlias : InstAlias<"$Vd32=vpackeb($Vu32,$Vv32)", (V6_vpackeb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackeh_altAlias : InstAlias<"$Vd32=vpackeh($Vu32,$Vv32)", (V6_vpackeh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackhb_sat_altAlias : InstAlias<"$Vd32=vpackhb($Vu32,$Vv32):sat", (V6_vpackhb_sat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackhub_sat_altAlias : InstAlias<"$Vd32=vpackhub($Vu32,$Vv32):sat", (V6_vpackhub_sat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackob_altAlias : InstAlias<"$Vd32=vpackob($Vu32,$Vv32)", (V6_vpackob HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackoh_altAlias : InstAlias<"$Vd32=vpackoh($Vu32,$Vv32)", (V6_vpackoh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackwh_sat_altAlias : InstAlias<"$Vd32=vpackwh($Vu32,$Vv32):sat", (V6_vpackwh_sat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackwuh_sat_altAlias : InstAlias<"$Vd32=vpackwuh($Vu32,$Vv32):sat", (V6_vpackwuh_sat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vpopcounth_altAlias : InstAlias<"$Vd32=vpopcounth($Vu32)", (V6_vpopcounth HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vrmpybus_acc_altAlias : InstAlias<"$Vx32+=vrmpybus($Vu32,$Rt32)", (V6_vrmpybus_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vrmpybus_altAlias : InstAlias<"$Vd32=vrmpybus($Vu32,$Rt32)", (V6_vrmpybus HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vrmpybusi_acc_altAlias : InstAlias<"$Vxx32+=vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrmpybusi_altAlias : InstAlias<"$Vdd32=vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrmpybusv_acc_altAlias : InstAlias<"$Vx32+=vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpybusv_altAlias : InstAlias<"$Vd32=vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpybv_acc_altAlias : InstAlias<"$Vx32+=vrmpyb($Vu32,$Vv32)", (V6_vrmpybv_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpybv_altAlias : InstAlias<"$Vd32=vrmpyb($Vu32,$Vv32)", (V6_vrmpybv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpyub_acc_altAlias : InstAlias<"$Vx32+=vrmpyub($Vu32,$Rt32)", (V6_vrmpyub_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vrmpyub_altAlias : InstAlias<"$Vd32=vrmpyub($Vu32,$Rt32)", (V6_vrmpyub HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vrmpyubi_acc_altAlias : InstAlias<"$Vxx32+=vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrmpyubi_altAlias : InstAlias<"$Vdd32=vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrmpyubv_acc_altAlias : InstAlias<"$Vx32+=vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpyubv_altAlias : InstAlias<"$Vd32=vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vroundhb_altAlias : InstAlias<"$Vd32=vroundhb($Vu32,$Vv32):sat", (V6_vroundhb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vroundhub_altAlias : InstAlias<"$Vd32=vroundhub($Vu32,$Vv32):sat", (V6_vroundhub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vroundwh_altAlias : InstAlias<"$Vd32=vroundwh($Vu32,$Vv32):sat", (V6_vroundwh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vroundwuh_altAlias : InstAlias<"$Vd32=vroundwuh($Vu32,$Vv32):sat", (V6_vroundwuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vrsadubi_acc_altAlias : InstAlias<"$Vxx32+=vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrsadubi_altAlias : InstAlias<"$Vdd32=vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vsathub_altAlias : InstAlias<"$Vd32=vsathub($Vu32,$Vv32)", (V6_vsathub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsatwh_altAlias : InstAlias<"$Vd32=vsatwh($Vu32,$Vv32)", (V6_vsatwh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsb_altAlias : InstAlias<"$Vdd32=vsxtb($Vu32)", (V6_vsb HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vsh_altAlias : InstAlias<"$Vdd32=vsxth($Vu32)", (V6_vsh HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vshufeh_altAlias : InstAlias<"$Vd32=vshuffeh($Vu32,$Vv32)", (V6_vshufeh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vshuffb_altAlias : InstAlias<"$Vd32=vshuffb($Vu32)", (V6_vshuffb HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vshuffeb_altAlias : InstAlias<"$Vd32=vshuffeb($Vu32,$Vv32)", (V6_vshuffeb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vshuffh_altAlias : InstAlias<"$Vd32=vshuffh($Vu32)", (V6_vshuffh HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vshuffob_altAlias : InstAlias<"$Vd32=vshuffob($Vu32,$Vv32)", (V6_vshuffob HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vshufoeb_altAlias : InstAlias<"$Vdd32=vshuffoeb($Vu32,$Vv32)", (V6_vshufoeb HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vshufoeh_altAlias : InstAlias<"$Vdd32=vshuffoeh($Vu32,$Vv32)", (V6_vshufoeh HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vshufoh_altAlias : InstAlias<"$Vd32=vshuffoh($Vu32,$Vv32)", (V6_vshufoh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubb_altAlias : InstAlias<"$Vd32=vsubb($Vu32,$Vv32)", (V6_vsubb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubb_dv_altAlias : InstAlias<"$Vdd32=vsubb($Vuu32,$Vvv32)", (V6_vsubb_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubbnq_altAlias : InstAlias<"if (!$Qv4.b) $Vx32.b-=$Vu32.b", (V6_vsubbnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubbq_altAlias : InstAlias<"if ($Qv4.b) $Vx32.b-=$Vu32.b", (V6_vsubbq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubh_altAlias : InstAlias<"$Vd32=vsubh($Vu32,$Vv32)", (V6_vsubh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubh_dv_altAlias : InstAlias<"$Vdd32=vsubh($Vuu32,$Vvv32)", (V6_vsubh_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubhnq_altAlias : InstAlias<"if (!$Qv4.h) $Vx32.h-=$Vu32.h", (V6_vsubhnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubhq_altAlias : InstAlias<"if ($Qv4.h) $Vx32.h-=$Vu32.h", (V6_vsubhq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubhsat_altAlias : InstAlias<"$Vd32=vsubh($Vu32,$Vv32):sat", (V6_vsubhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubhsat_dv_altAlias : InstAlias<"$Vdd32=vsubh($Vuu32,$Vvv32):sat", (V6_vsubhsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubhw_altAlias : InstAlias<"$Vdd32=vsubh($Vu32,$Vv32)", (V6_vsubhw HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsububh_altAlias : InstAlias<"$Vdd32=vsubub($Vu32,$Vv32)", (V6_vsububh HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsububsat_altAlias : InstAlias<"$Vd32=vsubub($Vu32,$Vv32):sat", (V6_vsububsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsububsat_dv_altAlias : InstAlias<"$Vdd32=vsubub($Vuu32,$Vvv32):sat", (V6_vsububsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubuhsat_altAlias : InstAlias<"$Vd32=vsubuh($Vu32,$Vv32):sat", (V6_vsubuhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubuhsat_dv_altAlias : InstAlias<"$Vdd32=vsubuh($Vuu32,$Vvv32):sat", (V6_vsubuhsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubuhw_altAlias : InstAlias<"$Vdd32=vsubuh($Vu32,$Vv32)", (V6_vsubuhw HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubw_altAlias : InstAlias<"$Vd32=vsubw($Vu32,$Vv32)", (V6_vsubw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubw_dv_altAlias : InstAlias<"$Vdd32=vsubw($Vuu32,$Vvv32)", (V6_vsubw_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubwnq_altAlias : InstAlias<"if (!$Qv4.w) $Vx32.w-=$Vu32.w", (V6_vsubwnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubwq_altAlias : InstAlias<"if ($Qv4.w) $Vx32.w-=$Vu32.w", (V6_vsubwq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubwsat_altAlias : InstAlias<"$Vd32=vsubw($Vu32,$Vv32):sat", (V6_vsubwsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubwsat_dv_altAlias : InstAlias<"$Vdd32=vsubw($Vuu32,$Vvv32):sat", (V6_vsubwsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vtmpyb_acc_altAlias : InstAlias<"$Vxx32+=vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpyb_altAlias : InstAlias<"$Vdd32=vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpybus_acc_altAlias : InstAlias<"$Vxx32+=vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpybus_altAlias : InstAlias<"$Vdd32=vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpyhb_acc_altAlias : InstAlias<"$Vxx32+=vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpyhb_altAlias : InstAlias<"$Vdd32=vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtran2x2_mapAlias : InstAlias<"vtrans2x2($Vy32,$Vx32,$Rt32)", (V6_vshuff HvxVR:$Vy32, HvxVR:$Vx32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vunpackb_altAlias : InstAlias<"$Vdd32=vunpackb($Vu32)", (V6_vunpackb HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackh_altAlias : InstAlias<"$Vdd32=vunpackh($Vu32)", (V6_vunpackh HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackoh_altAlias : InstAlias<"$Vxx32|=vunpackoh($Vu32)", (V6_vunpackoh HvxWR:$Vxx32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackub_altAlias : InstAlias<"$Vdd32=vunpackub($Vu32)", (V6_vunpackub HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackuh_altAlias : InstAlias<"$Vdd32=vunpackuh($Vu32)", (V6_vunpackuh HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vzb_altAlias : InstAlias<"$Vdd32=vzxtb($Vu32)", (V6_vzb HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vzh_altAlias : InstAlias<"$Vdd32=vzxth($Vu32)", (V6_vzh HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; def Y2_dcfetchAlias : InstAlias<"dcfetch($Rs32)", (Y2_dcfetchbo IntRegs:$Rs32, 0)>; diff --git a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp index b314e06f4822..a4c7f179b3da 100644 --- a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp +++ b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp @@ -389,8 +389,7 @@ bool HexagonEarlyIfConversion::isValidCandidate(const MachineBasicBlock *B) continue; switch (MRI->getRegClass(R)->getID()) { case Hexagon::PredRegsRegClassID: - case Hexagon::VecPredRegsRegClassID: - case Hexagon::VecPredRegs128BRegClassID: + case Hexagon::HvxQRRegClassID: break; default: continue; @@ -771,18 +770,12 @@ unsigned HexagonEarlyIfConversion::buildMux(MachineBasicBlock *B, case Hexagon::DoubleRegsRegClassID: Opc = Hexagon::PS_pselect; break; - case Hexagon::VectorRegsRegClassID: + case Hexagon::HvxVRRegClassID: Opc = Hexagon::PS_vselect; break; - case Hexagon::VecDblRegsRegClassID: + case Hexagon::HvxWRRegClassID: Opc = Hexagon::PS_wselect; break; - case Hexagon::VectorRegs128BRegClassID: - Opc = Hexagon::PS_vselect_128B; - break; - case Hexagon::VecDblRegs128BRegClassID: - Opc = Hexagon::PS_wselect_128B; - break; default: llvm_unreachable("unexpected register type"); } diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp index b37a1e716309..20d9469e0625 100644 --- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp +++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp @@ -87,6 +87,7 @@ // to be added, and updating the live ranges will be more involved. #include "HexagonInstrInfo.h" +#include "HexagonRegisterInfo.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SetVector.h" #include "llvm/ADT/SmallVector.h" diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp index 662223ccb004..367dd02275aa 100644 --- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -400,8 +400,7 @@ void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF, ShrinkCounter++; } - auto &HST = MF.getSubtarget(); - auto &HRI = *HST.getRegisterInfo(); + auto &HRI = *MF.getSubtarget().getRegisterInfo(); MachineDominatorTree MDT; MDT.runOnMachineFunction(MF); @@ -498,8 +497,7 @@ void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF, /// in one place allows shrink-wrapping of the stack frame. void HexagonFrameLowering::emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const { - auto &HST = MF.getSubtarget(); - auto &HRI = *HST.getRegisterInfo(); + auto &HRI = *MF.getSubtarget().getRegisterInfo(); MachineFrameInfo &MFI = MF.getFrameInfo(); const std::vector &CSI = MFI.getCalleeSavedInfo(); @@ -1603,7 +1601,6 @@ bool HexagonFrameLowering::expandLoadInt(MachineBasicBlock &B, bool HexagonFrameLowering::expandStoreVecPred(MachineBasicBlock &B, MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, const HexagonInstrInfo &HII, SmallVectorImpl &NewRegs) const { - auto &HST = B.getParent()->getSubtarget(); MachineInstr *MI = &*It; if (!MI->getOperand(0).isFI()) return false; @@ -1612,10 +1609,7 @@ bool HexagonFrameLowering::expandStoreVecPred(MachineBasicBlock &B, unsigned SrcR = MI->getOperand(2).getReg(); bool IsKill = MI->getOperand(2).isKill(); int FI = MI->getOperand(0).getIndex(); - - bool Is128B = HST.useHVXDblOps(); - auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass - : &Hexagon::VectorRegs128BRegClass; + auto *RC = &Hexagon::HvxVRRegClass; // Insert transfer to general vector register. // TmpR0 = A2_tfrsi 0x01010101 @@ -1627,8 +1621,7 @@ bool HexagonFrameLowering::expandStoreVecPred(MachineBasicBlock &B, BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0) .addImm(0x01010101); - unsigned VandOpc = !Is128B ? Hexagon::V6_vandqrt : Hexagon::V6_vandqrt_128B; - BuildMI(B, It, DL, HII.get(VandOpc), TmpR1) + BuildMI(B, It, DL, HII.get(Hexagon::V6_vandqrt), TmpR1) .addReg(SrcR, getKillRegState(IsKill)) .addReg(TmpR0, RegState::Kill); @@ -1645,7 +1638,6 @@ bool HexagonFrameLowering::expandStoreVecPred(MachineBasicBlock &B, bool HexagonFrameLowering::expandLoadVecPred(MachineBasicBlock &B, MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, const HexagonInstrInfo &HII, SmallVectorImpl &NewRegs) const { - auto &HST = B.getParent()->getSubtarget(); MachineInstr *MI = &*It; if (!MI->getOperand(1).isFI()) return false; @@ -1653,10 +1645,7 @@ bool HexagonFrameLowering::expandLoadVecPred(MachineBasicBlock &B, DebugLoc DL = MI->getDebugLoc(); unsigned DstR = MI->getOperand(0).getReg(); int FI = MI->getOperand(1).getIndex(); - - bool Is128B = HST.useHVXDblOps(); - auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass - : &Hexagon::VectorRegs128BRegClass; + auto *RC = &Hexagon::HvxVRRegClass; // TmpR0 = A2_tfrsi 0x01010101 // TmpR1 = load FI, 0 @@ -1666,12 +1655,12 @@ bool HexagonFrameLowering::expandLoadVecPred(MachineBasicBlock &B, BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0) .addImm(0x01010101); - auto *HRI = B.getParent()->getSubtarget().getRegisterInfo(); + MachineFunction &MF = *B.getParent(); + auto *HRI = MF.getSubtarget().getRegisterInfo(); HII.loadRegFromStackSlot(B, It, TmpR1, FI, RC, HRI); expandLoadVec(B, std::prev(It), MRI, HII, NewRegs); - unsigned VandOpc = !Is128B ? Hexagon::V6_vandvrt : Hexagon::V6_vandvrt_128B; - BuildMI(B, It, DL, HII.get(VandOpc), DstR) + BuildMI(B, It, DL, HII.get(Hexagon::V6_vandvrt), DstR) .addReg(TmpR1, RegState::Kill) .addReg(TmpR0, RegState::Kill); @@ -1685,7 +1674,6 @@ bool HexagonFrameLowering::expandStoreVec2(MachineBasicBlock &B, MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, const HexagonInstrInfo &HII, SmallVectorImpl &NewRegs) const { MachineFunction &MF = *B.getParent(); - auto &HST = MF.getSubtarget(); auto &MFI = MF.getFrameInfo(); auto &HRI = *MF.getSubtarget().getRegisterInfo(); MachineInstr *MI = &*It; @@ -1716,21 +1704,15 @@ bool HexagonFrameLowering::expandStoreVec2(MachineBasicBlock &B, bool IsKill = MI->getOperand(2).isKill(); int FI = MI->getOperand(0).getIndex(); - bool Is128B = HST.useHVXDblOps(); - const auto &RC = !Is128B ? Hexagon::VectorRegsRegClass - : Hexagon::VectorRegs128BRegClass; - unsigned Size = HRI.getSpillSize(RC); - unsigned NeedAlign = HRI.getSpillAlignment(RC); + unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass); + unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); unsigned HasAlign = MFI.getObjectAlignment(FI); unsigned StoreOpc; // Store low part. if (LPR.contains(SrcLo)) { - if (NeedAlign <= HasAlign) - StoreOpc = !Is128B ? Hexagon::V6_vS32b_ai : Hexagon::V6_vS32b_ai_128B; - else - StoreOpc = !Is128B ? Hexagon::V6_vS32Ub_ai : Hexagon::V6_vS32Ub_ai_128B; - + StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai + : Hexagon::V6_vS32Ub_ai; BuildMI(B, It, DL, HII.get(StoreOpc)) .addFrameIndex(FI) .addImm(0) @@ -1740,11 +1722,8 @@ bool HexagonFrameLowering::expandStoreVec2(MachineBasicBlock &B, // Store high part. if (LPR.contains(SrcHi)) { - if (NeedAlign <= MinAlign(HasAlign, Size)) - StoreOpc = !Is128B ? Hexagon::V6_vS32b_ai : Hexagon::V6_vS32b_ai_128B; - else - StoreOpc = !Is128B ? Hexagon::V6_vS32Ub_ai : Hexagon::V6_vS32Ub_ai_128B; - + StoreOpc = NeedAlign <= MinAlign(HasAlign, Size) ? Hexagon::V6_vS32b_ai + : Hexagon::V6_vS32Ub_ai; BuildMI(B, It, DL, HII.get(StoreOpc)) .addFrameIndex(FI) .addImm(Size) @@ -1760,7 +1739,6 @@ bool HexagonFrameLowering::expandLoadVec2(MachineBasicBlock &B, MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, const HexagonInstrInfo &HII, SmallVectorImpl &NewRegs) const { MachineFunction &MF = *B.getParent(); - auto &HST = MF.getSubtarget(); auto &MFI = MF.getFrameInfo(); auto &HRI = *MF.getSubtarget().getRegisterInfo(); MachineInstr *MI = &*It; @@ -1773,31 +1751,22 @@ bool HexagonFrameLowering::expandLoadVec2(MachineBasicBlock &B, unsigned DstLo = HRI.getSubReg(DstR, Hexagon::vsub_lo); int FI = MI->getOperand(1).getIndex(); - bool Is128B = HST.useHVXDblOps(); - const auto &RC = !Is128B ? Hexagon::VectorRegsRegClass - : Hexagon::VectorRegs128BRegClass; - unsigned Size = HRI.getSpillSize(RC); - unsigned NeedAlign = HRI.getSpillAlignment(RC); + unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass); + unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); unsigned HasAlign = MFI.getObjectAlignment(FI); unsigned LoadOpc; // Load low part. - if (NeedAlign <= HasAlign) - LoadOpc = !Is128B ? Hexagon::V6_vL32b_ai : Hexagon::V6_vL32b_ai_128B; - else - LoadOpc = !Is128B ? Hexagon::V6_vL32Ub_ai : Hexagon::V6_vL32Ub_ai_128B; - + LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai + : Hexagon::V6_vL32Ub_ai; BuildMI(B, It, DL, HII.get(LoadOpc), DstLo) .addFrameIndex(FI) .addImm(0) .setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); // Load high part. - if (NeedAlign <= MinAlign(HasAlign, Size)) - LoadOpc = !Is128B ? Hexagon::V6_vL32b_ai : Hexagon::V6_vL32b_ai_128B; - else - LoadOpc = !Is128B ? Hexagon::V6_vL32Ub_ai : Hexagon::V6_vL32Ub_ai_128B; - + LoadOpc = NeedAlign <= MinAlign(HasAlign, Size) ? Hexagon::V6_vL32b_ai + : Hexagon::V6_vL32Ub_ai; BuildMI(B, It, DL, HII.get(LoadOpc), DstHi) .addFrameIndex(FI) .addImm(Size) @@ -1811,30 +1780,21 @@ bool HexagonFrameLowering::expandStoreVec(MachineBasicBlock &B, MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, const HexagonInstrInfo &HII, SmallVectorImpl &NewRegs) const { MachineFunction &MF = *B.getParent(); - auto &HST = MF.getSubtarget(); auto &MFI = MF.getFrameInfo(); MachineInstr *MI = &*It; if (!MI->getOperand(0).isFI()) return false; - auto &HRI = *HST.getRegisterInfo(); + auto &HRI = *MF.getSubtarget().getRegisterInfo(); DebugLoc DL = MI->getDebugLoc(); unsigned SrcR = MI->getOperand(2).getReg(); bool IsKill = MI->getOperand(2).isKill(); int FI = MI->getOperand(0).getIndex(); - bool Is128B = HST.useHVXDblOps(); - const auto &RC = !Is128B ? Hexagon::VectorRegsRegClass - : Hexagon::VectorRegs128BRegClass; - unsigned NeedAlign = HRI.getSpillAlignment(RC); + unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); unsigned HasAlign = MFI.getObjectAlignment(FI); - unsigned StoreOpc; - - if (NeedAlign <= HasAlign) - StoreOpc = !Is128B ? Hexagon::V6_vS32b_ai : Hexagon::V6_vS32b_ai_128B; - else - StoreOpc = !Is128B ? Hexagon::V6_vS32Ub_ai : Hexagon::V6_vS32Ub_ai_128B; - + unsigned StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai + : Hexagon::V6_vS32Ub_ai; BuildMI(B, It, DL, HII.get(StoreOpc)) .addFrameIndex(FI) .addImm(0) @@ -1849,29 +1809,20 @@ bool HexagonFrameLowering::expandLoadVec(MachineBasicBlock &B, MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, const HexagonInstrInfo &HII, SmallVectorImpl &NewRegs) const { MachineFunction &MF = *B.getParent(); - auto &HST = MF.getSubtarget(); auto &MFI = MF.getFrameInfo(); MachineInstr *MI = &*It; if (!MI->getOperand(1).isFI()) return false; - auto &HRI = *HST.getRegisterInfo(); + auto &HRI = *MF.getSubtarget().getRegisterInfo(); DebugLoc DL = MI->getDebugLoc(); unsigned DstR = MI->getOperand(0).getReg(); int FI = MI->getOperand(1).getIndex(); - bool Is128B = HST.useHVXDblOps(); - const auto &RC = !Is128B ? Hexagon::VectorRegsRegClass - : Hexagon::VectorRegs128BRegClass; - unsigned NeedAlign = HRI.getSpillAlignment(RC); + unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); unsigned HasAlign = MFI.getObjectAlignment(FI); - unsigned LoadOpc; - - if (NeedAlign <= HasAlign) - LoadOpc = !Is128B ? Hexagon::V6_vL32b_ai : Hexagon::V6_vL32b_ai_128B; - else - LoadOpc = !Is128B ? Hexagon::V6_vL32Ub_ai : Hexagon::V6_vL32Ub_ai_128B; - + unsigned LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai + : Hexagon::V6_vL32Ub_ai; BuildMI(B, It, DL, HII.get(LoadOpc), DstR) .addFrameIndex(FI) .addImm(0) @@ -1883,8 +1834,7 @@ bool HexagonFrameLowering::expandLoadVec(MachineBasicBlock &B, bool HexagonFrameLowering::expandSpillMacros(MachineFunction &MF, SmallVectorImpl &NewRegs) const { - auto &HST = MF.getSubtarget(); - auto &HII = *HST.getInstrInfo(); + auto &HII = *MF.getSubtarget().getInstrInfo(); MachineRegisterInfo &MRI = MF.getRegInfo(); bool Changed = false; @@ -1909,23 +1859,17 @@ bool HexagonFrameLowering::expandSpillMacros(MachineFunction &MF, Changed |= expandLoadInt(B, I, MRI, HII, NewRegs); break; case Hexagon::PS_vstorerq_ai: - case Hexagon::PS_vstorerq_ai_128B: Changed |= expandStoreVecPred(B, I, MRI, HII, NewRegs); break; case Hexagon::PS_vloadrq_ai: - case Hexagon::PS_vloadrq_ai_128B: Changed |= expandLoadVecPred(B, I, MRI, HII, NewRegs); break; case Hexagon::PS_vloadrw_ai: case Hexagon::PS_vloadrwu_ai: - case Hexagon::PS_vloadrw_ai_128B: - case Hexagon::PS_vloadrwu_ai_128B: Changed |= expandLoadVec2(B, I, MRI, HII, NewRegs); break; case Hexagon::PS_vstorerw_ai: case Hexagon::PS_vstorerwu_ai: - case Hexagon::PS_vstorerw_ai_128B: - case Hexagon::PS_vstorerwu_ai_128B: Changed |= expandStoreVec2(B, I, MRI, HII, NewRegs); break; } @@ -1938,8 +1882,7 @@ bool HexagonFrameLowering::expandSpillMacros(MachineFunction &MF, void HexagonFrameLowering::determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const { - auto &HST = MF.getSubtarget(); - auto &HRI = *HST.getRegisterInfo(); + auto &HRI = *MF.getSubtarget().getRegisterInfo(); SavedRegs.resize(HRI.getNumRegs()); diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp index 3f63f102371e..7fa5b7525bd4 100644 --- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -1238,7 +1238,7 @@ bool HexagonHardwareLoops::convertToHardwareLoop(MachineLoop *L, // if the immediate fits in the instructions. Otherwise, we need to // create a new virtual register. int64_t CountImm = TripCount->getImm(); - if (!TII->isValidOffset(LOOP_i, CountImm)) { + if (!TII->isValidOffset(LOOP_i, CountImm, TRI)) { unsigned CountReg = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass); BuildMI(*Preheader, InsertPos, DL, TII->get(Hexagon::A2_tfrsi), CountReg) .addImm(CountImm); diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index 0163b2e2bdc4..74405374665c 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -241,6 +241,10 @@ void HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl) { case MVT::v32i16: case MVT::v16i32: case MVT::v8i64: + case MVT::v128i8: + case MVT::v64i16: + case MVT::v32i32: + case MVT::v16i64: if (isAlignedMemNode(LD)) { if (LD->isNonTemporal()) Opcode = IsValidInc ? Hexagon::V6_vL32b_nt_pi : Hexagon::V6_vL32b_nt_ai; @@ -250,23 +254,6 @@ void HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl) { Opcode = IsValidInc ? Hexagon::V6_vL32Ub_pi : Hexagon::V6_vL32Ub_ai; } break; - // 128B - case MVT::v128i8: - case MVT::v64i16: - case MVT::v32i32: - case MVT::v16i64: - if (isAlignedMemNode(LD)) { - if (LD->isNonTemporal()) - Opcode = IsValidInc ? Hexagon::V6_vL32b_nt_pi_128B - : Hexagon::V6_vL32b_nt_ai_128B; - else - Opcode = IsValidInc ? Hexagon::V6_vL32b_pi_128B - : Hexagon::V6_vL32b_ai_128B; - } else { - Opcode = IsValidInc ? Hexagon::V6_vL32Ub_pi_128B - : Hexagon::V6_vL32Ub_ai_128B; - } - break; default: llvm_unreachable("Unexpected memory type in indexed load"); } @@ -533,11 +520,14 @@ void HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl) { case MVT::i64: Opcode = IsValidInc ? Hexagon::S2_storerd_pi : Hexagon::S2_storerd_io; break; - // 64B case MVT::v64i8: case MVT::v32i16: case MVT::v16i32: case MVT::v8i64: + case MVT::v128i8: + case MVT::v64i16: + case MVT::v32i32: + case MVT::v16i64: if (isAlignedMemNode(ST)) { if (ST->isNonTemporal()) Opcode = IsValidInc ? Hexagon::V6_vS32b_nt_pi : Hexagon::V6_vS32b_nt_ai; @@ -547,23 +537,6 @@ void HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl) { Opcode = IsValidInc ? Hexagon::V6_vS32Ub_pi : Hexagon::V6_vS32Ub_ai; } break; - // 128B - case MVT::v128i8: - case MVT::v64i16: - case MVT::v32i32: - case MVT::v16i64: - if (isAlignedMemNode(ST)) { - if (ST->isNonTemporal()) - Opcode = IsValidInc ? Hexagon::V6_vS32b_nt_pi_128B - : Hexagon::V6_vS32b_nt_ai_128B; - else - Opcode = IsValidInc ? Hexagon::V6_vS32b_pi_128B - : Hexagon::V6_vS32b_ai_128B; - } else { - Opcode = IsValidInc ? Hexagon::V6_vS32Ub_pi_128B - : Hexagon::V6_vS32Ub_ai_128B; - } - break; default: llvm_unreachable("Unexpected memory type in indexed store"); } diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index 906501c6ff11..fcde4224a007 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -381,7 +381,6 @@ static bool CC_HexagonVector(unsigned ValNo, MVT ValVT, State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); return false; } - // 128B Mode if ((UseHVX && UseHVXDbl) && (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 || LocVT == MVT::v256i8)) { @@ -1191,14 +1190,14 @@ SDValue HexagonTargetLowering::LowerFormalArguments( } else if ((RegVT == MVT::v8i64 || RegVT == MVT::v16i32 || RegVT == MVT::v32i16 || RegVT == MVT::v64i8)) { unsigned VReg = - RegInfo.createVirtualRegister(&Hexagon::VectorRegsRegClass); + RegInfo.createVirtualRegister(&Hexagon::HvxVRRegClass); RegInfo.addLiveIn(VA.getLocReg(), VReg); InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); } else if (UseHVX && UseHVXDbl && ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 || RegVT == MVT::v64i16 || RegVT == MVT::v128i8))) { unsigned VReg = - RegInfo.createVirtualRegister(&Hexagon::VectorRegs128BRegClass); + RegInfo.createVirtualRegister(&Hexagon::HvxVRRegClass); RegInfo.addLiveIn(VA.getLocReg(), VReg); InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); @@ -1206,20 +1205,20 @@ SDValue HexagonTargetLowering::LowerFormalArguments( } else if ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 || RegVT == MVT::v64i16 || RegVT == MVT::v128i8)) { unsigned VReg = - RegInfo.createVirtualRegister(&Hexagon::VecDblRegsRegClass); + RegInfo.createVirtualRegister(&Hexagon::HvxWRRegClass); RegInfo.addLiveIn(VA.getLocReg(), VReg); InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); } else if (UseHVX && UseHVXDbl && ((RegVT == MVT::v32i64 || RegVT == MVT::v64i32 || RegVT == MVT::v128i16 || RegVT == MVT::v256i8))) { unsigned VReg = - RegInfo.createVirtualRegister(&Hexagon::VecDblRegs128BRegClass); + RegInfo.createVirtualRegister(&Hexagon::HvxWRRegClass); RegInfo.addLiveIn(VA.getLocReg(), VReg); InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); } else if (RegVT == MVT::v512i1 || RegVT == MVT::v1024i1) { assert(0 && "need to support VecPred regs"); unsigned VReg = - RegInfo.createVirtualRegister(&Hexagon::VecPredRegsRegClass); + RegInfo.createVirtualRegister(&Hexagon::HvxQRRegClass); RegInfo.addLiveIn(VA.getLocReg(), VReg); InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); } else { @@ -1759,25 +1758,25 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, if (Subtarget.hasV60TOps()) { if (Subtarget.useHVXSglOps()) { - addRegisterClass(MVT::v64i8, &Hexagon::VectorRegsRegClass); - addRegisterClass(MVT::v32i16, &Hexagon::VectorRegsRegClass); - addRegisterClass(MVT::v16i32, &Hexagon::VectorRegsRegClass); - addRegisterClass(MVT::v8i64, &Hexagon::VectorRegsRegClass); - addRegisterClass(MVT::v128i8, &Hexagon::VecDblRegsRegClass); - addRegisterClass(MVT::v64i16, &Hexagon::VecDblRegsRegClass); - addRegisterClass(MVT::v32i32, &Hexagon::VecDblRegsRegClass); - addRegisterClass(MVT::v16i64, &Hexagon::VecDblRegsRegClass); - addRegisterClass(MVT::v512i1, &Hexagon::VecPredRegsRegClass); + addRegisterClass(MVT::v64i8, &Hexagon::HvxVRRegClass); + addRegisterClass(MVT::v32i16, &Hexagon::HvxVRRegClass); + addRegisterClass(MVT::v16i32, &Hexagon::HvxVRRegClass); + addRegisterClass(MVT::v8i64, &Hexagon::HvxVRRegClass); + addRegisterClass(MVT::v128i8, &Hexagon::HvxWRRegClass); + addRegisterClass(MVT::v64i16, &Hexagon::HvxWRRegClass); + addRegisterClass(MVT::v32i32, &Hexagon::HvxWRRegClass); + addRegisterClass(MVT::v16i64, &Hexagon::HvxWRRegClass); + addRegisterClass(MVT::v512i1, &Hexagon::HvxQRRegClass); } else if (Subtarget.useHVXDblOps()) { - addRegisterClass(MVT::v128i8, &Hexagon::VectorRegs128BRegClass); - addRegisterClass(MVT::v64i16, &Hexagon::VectorRegs128BRegClass); - addRegisterClass(MVT::v32i32, &Hexagon::VectorRegs128BRegClass); - addRegisterClass(MVT::v16i64, &Hexagon::VectorRegs128BRegClass); - addRegisterClass(MVT::v256i8, &Hexagon::VecDblRegs128BRegClass); - addRegisterClass(MVT::v128i16, &Hexagon::VecDblRegs128BRegClass); - addRegisterClass(MVT::v64i32, &Hexagon::VecDblRegs128BRegClass); - addRegisterClass(MVT::v32i64, &Hexagon::VecDblRegs128BRegClass); - addRegisterClass(MVT::v1024i1, &Hexagon::VecPredRegs128BRegClass); + addRegisterClass(MVT::v128i8, &Hexagon::HvxVRRegClass); + addRegisterClass(MVT::v64i16, &Hexagon::HvxVRRegClass); + addRegisterClass(MVT::v32i32, &Hexagon::HvxVRRegClass); + addRegisterClass(MVT::v16i64, &Hexagon::HvxVRRegClass); + addRegisterClass(MVT::v256i8, &Hexagon::HvxWRRegClass); + addRegisterClass(MVT::v128i16, &Hexagon::HvxWRRegClass); + addRegisterClass(MVT::v64i32, &Hexagon::HvxWRRegClass); + addRegisterClass(MVT::v32i64, &Hexagon::HvxWRRegClass); + addRegisterClass(MVT::v1024i1, &Hexagon::HvxQRRegClass); } } @@ -2999,9 +2998,9 @@ HexagonTargetLowering::getRegForInlineAsmConstraint( default: llvm_unreachable("getRegForInlineAsmConstraint Unhandled vector size"); case 512: - return std::make_pair(0U, &Hexagon::VecPredRegsRegClass); + return std::make_pair(0U, &Hexagon::HvxQRRegClass); case 1024: - return std::make_pair(0U, &Hexagon::VecPredRegs128BRegClass); + return std::make_pair(0U, &Hexagon::HvxQRRegClass); } break; case 'v': // V0-V31 @@ -3009,13 +3008,13 @@ HexagonTargetLowering::getRegForInlineAsmConstraint( default: llvm_unreachable("getRegForInlineAsmConstraint Unhandled vector size"); case 512: - return std::make_pair(0U, &Hexagon::VectorRegsRegClass); + return std::make_pair(0U, &Hexagon::HvxVRRegClass); case 1024: if (Subtarget.hasV60TOps() && UseHVX && UseHVXDbl) - return std::make_pair(0U, &Hexagon::VectorRegs128BRegClass); - return std::make_pair(0U, &Hexagon::VecDblRegsRegClass); + return std::make_pair(0U, &Hexagon::HvxVRRegClass); + return std::make_pair(0U, &Hexagon::HvxWRRegClass); case 2048: - return std::make_pair(0U, &Hexagon::VecDblRegs128BRegClass); + return std::make_pair(0U, &Hexagon::HvxWRRegClass); } break; default: @@ -3207,7 +3206,7 @@ HexagonTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI, case MVT::v32i16: case MVT::v16i32: case MVT::v8i64: - RRC = &Hexagon::VectorRegsRegClass; + RRC = &Hexagon::HvxVRRegClass; break; case MVT::v128i8: case MVT::v64i16: @@ -3215,15 +3214,15 @@ HexagonTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI, case MVT::v16i64: if (Subtarget.hasV60TOps() && Subtarget.useHVXOps() && Subtarget.useHVXDblOps()) - RRC = &Hexagon::VectorRegs128BRegClass; + RRC = &Hexagon::HvxVRRegClass; else - RRC = &Hexagon::VecDblRegsRegClass; + RRC = &Hexagon::HvxWRRegClass; break; case MVT::v256i8: case MVT::v128i16: case MVT::v64i32: case MVT::v32i64: - RRC = &Hexagon::VecDblRegs128BRegClass; + RRC = &Hexagon::HvxWRRegClass; break; } return std::make_pair(RRC, Cost); diff --git a/llvm/lib/Target/Hexagon/HexagonInstrFormats.td b/llvm/lib/Target/Hexagon/HexagonInstrFormats.td index bc9ee71111e8..4da2edc24f3a 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrFormats.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrFormats.td @@ -31,8 +31,7 @@ def ByteAccess : MemAccessSize<1>; def HalfWordAccess : MemAccessSize<2>; def WordAccess : MemAccessSize<3>; def DoubleWordAccess : MemAccessSize<4>; -def Vector64Access : MemAccessSize<5>; -def Vector128Access : MemAccessSize<6>; +def HVXVectorAccess : MemAccessSize<5>; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index fd10fc789fee..2f6da901d897 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -104,25 +104,12 @@ const int Hexagon_MEMB_OFFSET_MAX = 1023; const int Hexagon_MEMB_OFFSET_MIN = -1024; const int Hexagon_ADDI_OFFSET_MAX = 32767; const int Hexagon_ADDI_OFFSET_MIN = -32768; -const int Hexagon_MEMD_AUTOINC_MAX = 56; -const int Hexagon_MEMD_AUTOINC_MIN = -64; -const int Hexagon_MEMW_AUTOINC_MAX = 28; -const int Hexagon_MEMW_AUTOINC_MIN = -32; -const int Hexagon_MEMH_AUTOINC_MAX = 14; -const int Hexagon_MEMH_AUTOINC_MIN = -16; -const int Hexagon_MEMB_AUTOINC_MAX = 7; -const int Hexagon_MEMB_AUTOINC_MIN = -8; -const int Hexagon_MEMV_AUTOINC_MAX = 192; // #s3 -const int Hexagon_MEMV_AUTOINC_MIN = -256; // #s3 -const int Hexagon_MEMV_AUTOINC_MAX_128B = 384; // #s3 -const int Hexagon_MEMV_AUTOINC_MIN_128B = -512; // #s3 // Pin the vtable to this file. void HexagonInstrInfo::anchor() {} HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST) - : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP), - RI() {} + : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP) {} static bool isIntRegForSubInst(unsigned Reg) { return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) || @@ -251,18 +238,12 @@ unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, case Hexagon::L2_loadrd_io: case Hexagon::V6_vL32b_ai: case Hexagon::V6_vL32b_nt_ai: - case Hexagon::V6_vL32b_ai_128B: - case Hexagon::V6_vL32b_nt_ai_128B: case Hexagon::V6_vL32Ub_ai: - case Hexagon::V6_vL32Ub_ai_128B: case Hexagon::LDriw_pred: case Hexagon::LDriw_mod: case Hexagon::PS_vloadrq_ai: case Hexagon::PS_vloadrw_ai: - case Hexagon::PS_vloadrw_nt_ai: - case Hexagon::PS_vloadrq_ai_128B: - case Hexagon::PS_vloadrw_ai_128B: - case Hexagon::PS_vloadrw_nt_ai_128B: { + case Hexagon::PS_vloadrw_nt_ai: { const MachineOperand OpFI = MI.getOperand(1); if (!OpFI.isFI()) return 0; @@ -306,15 +287,11 @@ unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr &MI, case Hexagon::S2_storeri_io: case Hexagon::S2_storerd_io: case Hexagon::V6_vS32b_ai: - case Hexagon::V6_vS32b_ai_128B: case Hexagon::V6_vS32Ub_ai: - case Hexagon::V6_vS32Ub_ai_128B: case Hexagon::STriw_pred: case Hexagon::STriw_mod: case Hexagon::PS_vstorerq_ai: - case Hexagon::PS_vstorerw_ai: - case Hexagon::PS_vstorerq_ai_128B: - case Hexagon::PS_vstorerw_ai_128B: { + case Hexagon::PS_vstorerw_ai: { const MachineOperand &OpFI = MI.getOperand(0); if (!OpFI.isFI()) return 0; @@ -715,10 +692,11 @@ unsigned HexagonInstrInfo::reduceLoopCount(MachineBasicBlock &MBB, unsigned NewLoopCount = createVR(MF, MVT::i32); MachineInstr *NewAdd = BuildMI(&MBB, DL, get(Hexagon::A2_addi), NewLoopCount). addReg(LoopCount).addImm(-1); + const auto &HRI = *MF->getSubtarget().getRegisterInfo(); // Update the previously generated instructions with the new loop counter. for (SmallVectorImpl::iterator I = PrevInsts.begin(), E = PrevInsts.end(); I != E; ++I) - (*I)->substituteRegister(LoopCount, NewLoopCount, 0, getRegisterInfo()); + (*I)->substituteRegister(LoopCount, NewLoopCount, 0, HRI); PrevInsts.clear(); PrevInsts.push_back(NewCmp); PrevInsts.push_back(NewAdd); @@ -757,7 +735,8 @@ void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const { - auto &HRI = getRegisterInfo(); + MachineFunction &MF = *MBB.getParent(); + auto &HRI = *MF.getSubtarget().getRegisterInfo(); unsigned KillFlag = getKillRegState(KillSrc); if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) { @@ -812,12 +791,12 @@ void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB, .addReg(SrcReg, KillFlag); return; } - if (Hexagon::VectorRegsRegClass.contains(SrcReg, DestReg)) { + if (Hexagon::HvxVRRegClass.contains(SrcReg, DestReg)) { BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg). addReg(SrcReg, KillFlag); return; } - if (Hexagon::VecDblRegsRegClass.contains(SrcReg, DestReg)) { + if (Hexagon::HvxWRRegClass.contains(SrcReg, DestReg)) { unsigned LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); unsigned HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg) @@ -825,33 +804,22 @@ void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB, .addReg(LoSrc, KillFlag); return; } - if (Hexagon::VecPredRegsRegClass.contains(SrcReg, DestReg)) { + if (Hexagon::HvxQRRegClass.contains(SrcReg, DestReg)) { BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg) .addReg(SrcReg) .addReg(SrcReg, KillFlag); return; } - if (Hexagon::VecPredRegsRegClass.contains(SrcReg) && - Hexagon::VectorRegsRegClass.contains(DestReg)) { + if (Hexagon::HvxQRRegClass.contains(SrcReg) && + Hexagon::HvxVRRegClass.contains(DestReg)) { llvm_unreachable("Unimplemented pred to vec"); return; } - if (Hexagon::VecPredRegsRegClass.contains(DestReg) && - Hexagon::VectorRegsRegClass.contains(SrcReg)) { + if (Hexagon::HvxQRRegClass.contains(DestReg) && + Hexagon::HvxVRRegClass.contains(SrcReg)) { llvm_unreachable("Unimplemented vec to pred"); return; } - if (Hexagon::VecPredRegs128BRegClass.contains(SrcReg, DestReg)) { - unsigned HiDst = HRI.getSubReg(DestReg, Hexagon::vsub_hi); - unsigned LoDst = HRI.getSubReg(DestReg, Hexagon::vsub_lo); - unsigned HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); - unsigned LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); - BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), HiDst) - .addReg(HiSrc, KillFlag); - BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), LoDst) - .addReg(LoSrc, KillFlag); - return; - } #ifndef NDEBUG // Show the invalid registers to ease debugging. @@ -868,7 +836,8 @@ void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, DebugLoc DL = MBB.findDebugLoc(I); MachineFunction &MF = *MBB.getParent(); MachineFrameInfo &MFI = MF.getFrameInfo(); - unsigned Align = MFI.getObjectAlignment(FI); + unsigned SlotAlign = MFI.getObjectAlignment(FI); + unsigned RegAlign = TRI->getSpillAlignment(*RC); unsigned KillFlag = getKillRegState(isKill); bool HasAlloca = MFI.hasVarSizedObjects(); const auto &HST = MF.getSubtarget(); @@ -876,7 +845,7 @@ void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineMemOperand *MMO = MF.getMachineMemOperand( MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore, - MFI.getObjectSize(FI), Align); + MFI.getObjectSize(FI), SlotAlign); if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io)) @@ -894,50 +863,34 @@ void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, BuildMI(MBB, I, DL, get(Hexagon::STriw_mod)) .addFrameIndex(FI).addImm(0) .addReg(SrcReg, KillFlag).addMemOperand(MMO); - } else if (Hexagon::VecPredRegs128BRegClass.hasSubClassEq(RC)) { - BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai_128B)) - .addFrameIndex(FI).addImm(0) - .addReg(SrcReg, KillFlag).addMemOperand(MMO); - } else if (Hexagon::VecPredRegsRegClass.hasSubClassEq(RC)) { + } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) { BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai)) .addFrameIndex(FI).addImm(0) .addReg(SrcReg, KillFlag).addMemOperand(MMO); - } else if (Hexagon::VectorRegs128BRegClass.hasSubClassEq(RC)) { + } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) { // If there are variable-sized objects, spills will not be aligned. if (HasAlloca) - Align = HFI.getStackAlignment(); - unsigned Opc = Align < 128 ? Hexagon::V6_vS32Ub_ai_128B - : Hexagon::V6_vS32b_ai_128B; + SlotAlign = HFI.getStackAlignment(); + unsigned Opc = SlotAlign < RegAlign ? Hexagon::V6_vS32Ub_ai + : Hexagon::V6_vS32b_ai; + MachineMemOperand *MMOA = MF.getMachineMemOperand( + MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore, + MFI.getObjectSize(FI), SlotAlign); BuildMI(MBB, I, DL, get(Opc)) .addFrameIndex(FI).addImm(0) - .addReg(SrcReg, KillFlag).addMemOperand(MMO); - } else if (Hexagon::VectorRegsRegClass.hasSubClassEq(RC)) { + .addReg(SrcReg, KillFlag).addMemOperand(MMOA); + } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) { // If there are variable-sized objects, spills will not be aligned. if (HasAlloca) - Align = HFI.getStackAlignment(); - unsigned Opc = Align < 64 ? Hexagon::V6_vS32Ub_ai - : Hexagon::V6_vS32b_ai; + SlotAlign = HFI.getStackAlignment(); + unsigned Opc = SlotAlign < RegAlign ? Hexagon::PS_vstorerwu_ai + : Hexagon::PS_vstorerw_ai; + MachineMemOperand *MMOA = MF.getMachineMemOperand( + MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore, + MFI.getObjectSize(FI), SlotAlign); BuildMI(MBB, I, DL, get(Opc)) .addFrameIndex(FI).addImm(0) - .addReg(SrcReg, KillFlag).addMemOperand(MMO); - } else if (Hexagon::VecDblRegsRegClass.hasSubClassEq(RC)) { - // If there are variable-sized objects, spills will not be aligned. - if (HasAlloca) - Align = HFI.getStackAlignment(); - unsigned Opc = Align < 64 ? Hexagon::PS_vstorerwu_ai - : Hexagon::PS_vstorerw_ai; - BuildMI(MBB, I, DL, get(Opc)) - .addFrameIndex(FI).addImm(0) - .addReg(SrcReg, KillFlag).addMemOperand(MMO); - } else if (Hexagon::VecDblRegs128BRegClass.hasSubClassEq(RC)) { - // If there are variable-sized objects, spills will not be aligned. - if (HasAlloca) - Align = HFI.getStackAlignment(); - unsigned Opc = Align < 128 ? Hexagon::PS_vstorerwu_ai_128B - : Hexagon::PS_vstorerw_ai_128B; - BuildMI(MBB, I, DL, get(Opc)) - .addFrameIndex(FI).addImm(0) - .addReg(SrcReg, KillFlag).addMemOperand(MMO); + .addReg(SrcReg, KillFlag).addMemOperand(MMOA); } else { llvm_unreachable("Unimplemented"); } @@ -950,14 +903,15 @@ void HexagonInstrInfo::loadRegFromStackSlot( DebugLoc DL = MBB.findDebugLoc(I); MachineFunction &MF = *MBB.getParent(); MachineFrameInfo &MFI = MF.getFrameInfo(); - unsigned Align = MFI.getObjectAlignment(FI); + unsigned SlotAlign = MFI.getObjectAlignment(FI); + unsigned RegAlign = TRI->getSpillAlignment(*RC); bool HasAlloca = MFI.hasVarSizedObjects(); const auto &HST = MF.getSubtarget(); const HexagonFrameLowering &HFI = *HST.getFrameLowering(); MachineMemOperand *MMO = MF.getMachineMemOperand( MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad, - MFI.getObjectSize(FI), Align); + MFI.getObjectSize(FI), SlotAlign); if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg) @@ -971,44 +925,31 @@ void HexagonInstrInfo::loadRegFromStackSlot( } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) { BuildMI(MBB, I, DL, get(Hexagon::LDriw_mod), DestReg) .addFrameIndex(FI).addImm(0).addMemOperand(MMO); - } else if (Hexagon::VecPredRegs128BRegClass.hasSubClassEq(RC)) { - BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai_128B), DestReg) - .addFrameIndex(FI).addImm(0).addMemOperand(MMO); - } else if (Hexagon::VecPredRegsRegClass.hasSubClassEq(RC)) { + } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) { BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai), DestReg) .addFrameIndex(FI).addImm(0).addMemOperand(MMO); - } else if (Hexagon::VecDblRegs128BRegClass.hasSubClassEq(RC)) { + } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) { // If there are variable-sized objects, spills will not be aligned. if (HasAlloca) - Align = HFI.getStackAlignment(); - unsigned Opc = Align < 128 ? Hexagon::PS_vloadrwu_ai_128B - : Hexagon::PS_vloadrw_ai_128B; + SlotAlign = HFI.getStackAlignment(); + unsigned Opc = SlotAlign < RegAlign ? Hexagon::V6_vL32Ub_ai + : Hexagon::V6_vL32b_ai; + MachineMemOperand *MMOA = MF.getMachineMemOperand( + MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad, + MFI.getObjectSize(FI), SlotAlign); BuildMI(MBB, I, DL, get(Opc), DestReg) - .addFrameIndex(FI).addImm(0).addMemOperand(MMO); - } else if (Hexagon::VectorRegs128BRegClass.hasSubClassEq(RC)) { + .addFrameIndex(FI).addImm(0).addMemOperand(MMOA); + } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) { // If there are variable-sized objects, spills will not be aligned. if (HasAlloca) - Align = HFI.getStackAlignment(); - unsigned Opc = Align < 128 ? Hexagon::V6_vL32Ub_ai_128B - : Hexagon::V6_vL32b_ai_128B; + SlotAlign = HFI.getStackAlignment(); + unsigned Opc = SlotAlign < RegAlign ? Hexagon::PS_vloadrwu_ai + : Hexagon::PS_vloadrw_ai; + MachineMemOperand *MMOA = MF.getMachineMemOperand( + MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad, + MFI.getObjectSize(FI), SlotAlign); BuildMI(MBB, I, DL, get(Opc), DestReg) - .addFrameIndex(FI).addImm(0).addMemOperand(MMO); - } else if (Hexagon::VectorRegsRegClass.hasSubClassEq(RC)) { - // If there are variable-sized objects, spills will not be aligned. - if (HasAlloca) - Align = HFI.getStackAlignment(); - unsigned Opc = Align < 64 ? Hexagon::V6_vL32Ub_ai - : Hexagon::V6_vL32b_ai; - BuildMI(MBB, I, DL, get(Opc), DestReg) - .addFrameIndex(FI).addImm(0).addMemOperand(MMO); - } else if (Hexagon::VecDblRegsRegClass.hasSubClassEq(RC)) { - // If there are variable-sized objects, spills will not be aligned. - if (HasAlloca) - Align = HFI.getStackAlignment(); - unsigned Opc = Align < 64 ? Hexagon::PS_vloadrwu_ai - : Hexagon::PS_vloadrw_ai; - BuildMI(MBB, I, DL, get(Opc), DestReg) - .addFrameIndex(FI).addImm(0).addMemOperand(MMO); + .addFrameIndex(FI).addImm(0).addMemOperand(MMOA); } else { llvm_unreachable("Can't store this register to stack slot"); } @@ -1029,12 +970,12 @@ static void getLiveRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) { /// new instructions and erase MI. The function should return true if /// anything was changed. bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { - const HexagonRegisterInfo &HRI = getRegisterInfo(); - MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); MachineBasicBlock &MBB = *MI.getParent(); + MachineFunction &MF = *MBB.getParent(); + MachineRegisterInfo &MRI = MF.getRegInfo(); + const auto &HRI = *MF.getSubtarget().getRegisterInfo(); DebugLoc DL = MI.getDebugLoc(); unsigned Opc = MI.getOpcode(); - const unsigned VecOffset = 1; switch (Opc) { case TargetOpcode::COPY: { @@ -1054,7 +995,6 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { .addImm(-MI.getOperand(1).getImm()); MBB.erase(MI); return true; - case Hexagon::V6_vassignp_128B: case Hexagon::V6_vassignp: { unsigned SrcReg = MI.getOperand(1).getReg(); unsigned DstReg = MI.getOperand(0).getReg(); @@ -1065,7 +1005,6 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { MBB.erase(MI); return true; } - case Hexagon::V6_lo_128B: case Hexagon::V6_lo: { unsigned SrcReg = MI.getOperand(1).getReg(); unsigned DstReg = MI.getOperand(0).getReg(); @@ -1075,7 +1014,6 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { MRI.clearKillFlags(SrcSubLo); return true; } - case Hexagon::V6_hi_128B: case Hexagon::V6_hi: { unsigned SrcReg = MI.getOperand(1).getReg(); unsigned DstReg = MI.getOperand(0).getReg(); @@ -1086,25 +1024,14 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { return true; } case Hexagon::PS_vstorerw_ai: - case Hexagon::PS_vstorerwu_ai: - case Hexagon::PS_vstorerw_ai_128B: - case Hexagon::PS_vstorerwu_ai_128B: { - bool Is128B = (Opc == Hexagon::PS_vstorerw_ai_128B || - Opc == Hexagon::PS_vstorerwu_ai_128B); - bool Aligned = (Opc == Hexagon::PS_vstorerw_ai || - Opc == Hexagon::PS_vstorerw_ai_128B); + case Hexagon::PS_vstorerwu_ai: { + bool Aligned = Opc == Hexagon::PS_vstorerw_ai; unsigned SrcReg = MI.getOperand(2).getReg(); unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); - unsigned NewOpc; - if (Aligned) - NewOpc = Is128B ? Hexagon::V6_vS32b_ai_128B - : Hexagon::V6_vS32b_ai; - else - NewOpc = Is128B ? Hexagon::V6_vS32Ub_ai_128B - : Hexagon::V6_vS32Ub_ai; + unsigned NewOpc = Aligned ? Hexagon::V6_vS32b_ai : Hexagon::V6_vS32Ub_ai; + unsigned Offset = HRI.getSpillSize(Hexagon::HvxVRRegClass); - unsigned Offset = Is128B ? VecOffset << 7 : VecOffset << 6; MachineInstr *MI1New = BuildMI(MBB, MI, DL, get(NewOpc)) .add(MI.getOperand(0)) @@ -1122,23 +1049,12 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { return true; } case Hexagon::PS_vloadrw_ai: - case Hexagon::PS_vloadrwu_ai: - case Hexagon::PS_vloadrw_ai_128B: - case Hexagon::PS_vloadrwu_ai_128B: { - bool Is128B = (Opc == Hexagon::PS_vloadrw_ai_128B || - Opc == Hexagon::PS_vloadrwu_ai_128B); - bool Aligned = (Opc == Hexagon::PS_vloadrw_ai || - Opc == Hexagon::PS_vloadrw_ai_128B); - unsigned NewOpc; - if (Aligned) - NewOpc = Is128B ? Hexagon::V6_vL32b_ai_128B - : Hexagon::V6_vL32b_ai; - else - NewOpc = Is128B ? Hexagon::V6_vL32Ub_ai_128B - : Hexagon::V6_vL32Ub_ai; - + case Hexagon::PS_vloadrwu_ai: { + bool Aligned = Opc == Hexagon::PS_vloadrw_ai; unsigned DstReg = MI.getOperand(0).getReg(); - unsigned Offset = Is128B ? VecOffset << 7 : VecOffset << 6; + unsigned NewOpc = Aligned ? Hexagon::V6_vL32b_ai : Hexagon::V6_vL32Ub_ai; + unsigned Offset = HRI.getSpillSize(Hexagon::HvxVRRegClass); + MachineInstr *MI1New = BuildMI(MBB, MI, DL, get(NewOpc), HRI.getSubReg(DstReg, Hexagon::vsub_lo)) .add(MI.getOperand(1)) @@ -1248,8 +1164,7 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { MBB.erase(MI); return true; } - case Hexagon::PS_vselect: - case Hexagon::PS_vselect_128B: { + case Hexagon::PS_vselect: { const MachineOperand &Op0 = MI.getOperand(0); const MachineOperand &Op1 = MI.getOperand(1); const MachineOperand &Op2 = MI.getOperand(2); @@ -1283,8 +1198,7 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { MBB.erase(MI); return true; } - case Hexagon::PS_wselect: - case Hexagon::PS_wselect_128B: { + case Hexagon::PS_wselect: { MachineOperand &Op0 = MI.getOperand(0); MachineOperand &Op1 = MI.getOperand(1); MachineOperand &Op2 = MI.getOperand(2); @@ -1452,9 +1366,11 @@ bool HexagonInstrInfo::SubsumesPredicate(ArrayRef Pred1, return false; } -bool HexagonInstrInfo::DefinesPredicate( - MachineInstr &MI, std::vector &Pred) const { - auto &HRI = getRegisterInfo(); +bool HexagonInstrInfo::DefinesPredicate(MachineInstr &MI, + std::vector &Pred) const { + MachineFunction &MF = *MI.getParent()->getParent(); + const auto &HRI = *MF.getSubtarget().getRegisterInfo(); + for (unsigned oper = 0; oper < MI.getNumOperands(); ++oper) { MachineOperand MO = MI.getOperand(oper); if (MO.isReg()) { @@ -1895,8 +1811,8 @@ bool HexagonInstrInfo::isDependent(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const { if (!ProdMI.getDesc().getNumDefs()) return false; - - auto &HRI = getRegisterInfo(); + const MachineFunction &MF = *ProdMI.getParent()->getParent(); + const auto &HRI = *MF.getSubtarget().getRegisterInfo(); SmallVector DefsA; SmallVector DefsB; @@ -1931,8 +1847,6 @@ bool HexagonInstrInfo::isDotCurInst(const MachineInstr &MI) const { switch (MI.getOpcode()) { case Hexagon::V6_vL32b_cur_pi: case Hexagon::V6_vL32b_cur_ai: - case Hexagon::V6_vL32b_cur_pi_128B: - case Hexagon::V6_vL32b_cur_ai_128B: return true; } return false; @@ -2444,44 +2358,38 @@ bool HexagonInstrInfo::isHVXVec(const MachineInstr &MI) const { // Check if the Offset is a valid auto-inc imm by Load/Store Type. // -bool HexagonInstrInfo::isValidAutoIncImm(const EVT VT, const int Offset) const { - if (VT == MVT::v16i32 || VT == MVT::v8i64 || - VT == MVT::v32i16 || VT == MVT::v64i8) { - return (Offset >= Hexagon_MEMV_AUTOINC_MIN && - Offset <= Hexagon_MEMV_AUTOINC_MAX && - (Offset & 0x3f) == 0); +bool HexagonInstrInfo::isValidAutoIncImm(const EVT VT, int Offset) const { + int Size = VT.getSizeInBits() / 8; + if (Offset % Size != 0) + return false; + int Count = Offset / Size; + + switch (VT.getSimpleVT().SimpleTy) { + // For scalars the auto-inc is s4 + case MVT::i8: + case MVT::i16: + case MVT::i32: + case MVT::i64: + return isInt<4>(Count); + // For HVX vectors the auto-inc is s3 + case MVT::v64i8: + case MVT::v32i16: + case MVT::v16i32: + case MVT::v8i64: + case MVT::v128i8: + case MVT::v64i16: + case MVT::v32i32: + case MVT::v16i64: + return isInt<3>(Count); + default: + break; } - // 128B - if (VT == MVT::v32i32 || VT == MVT::v16i64 || - VT == MVT::v64i16 || VT == MVT::v128i8) { - return (Offset >= Hexagon_MEMV_AUTOINC_MIN_128B && - Offset <= Hexagon_MEMV_AUTOINC_MAX_128B && - (Offset & 0x7f) == 0); - } - if (VT == MVT::i64) { - return (Offset >= Hexagon_MEMD_AUTOINC_MIN && - Offset <= Hexagon_MEMD_AUTOINC_MAX && - (Offset & 0x7) == 0); - } - if (VT == MVT::i32) { - return (Offset >= Hexagon_MEMW_AUTOINC_MIN && - Offset <= Hexagon_MEMW_AUTOINC_MAX && - (Offset & 0x3) == 0); - } - if (VT == MVT::i16) { - return (Offset >= Hexagon_MEMH_AUTOINC_MIN && - Offset <= Hexagon_MEMH_AUTOINC_MAX && - (Offset & 0x1) == 0); - } - if (VT == MVT::i8) { - return (Offset >= Hexagon_MEMB_AUTOINC_MIN && - Offset <= Hexagon_MEMB_AUTOINC_MAX); - } - llvm_unreachable("Not an auto-inc opc!"); + + llvm_unreachable("Not an valid type!"); } bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset, - bool Extend) const { + const TargetRegisterInfo *TRI, bool Extend) const { // This function is to check whether the "Offset" is in the correct range of // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is // inserted to calculate the final address. Due to this reason, the function @@ -2490,7 +2398,6 @@ bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset, // there are cases where a misaligned pointer recast can cause this // problem, and we need to allow for it. The front end warns of such // misaligns with respect to load size. - switch (Opcode) { case Hexagon::PS_vstorerq_ai: case Hexagon::PS_vstorerw_ai: @@ -2503,22 +2410,13 @@ bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset, case Hexagon::V6_vL32b_nt_ai: case Hexagon::V6_vS32b_nt_ai: case Hexagon::V6_vL32Ub_ai: - case Hexagon::V6_vS32Ub_ai: - return isShiftedInt<4,6>(Offset); - - case Hexagon::PS_vstorerq_ai_128B: - case Hexagon::PS_vstorerw_ai_128B: - case Hexagon::PS_vstorerw_nt_ai_128B: - case Hexagon::PS_vloadrq_ai_128B: - case Hexagon::PS_vloadrw_ai_128B: - case Hexagon::PS_vloadrw_nt_ai_128B: - case Hexagon::V6_vL32b_ai_128B: - case Hexagon::V6_vS32b_ai_128B: - case Hexagon::V6_vL32b_nt_ai_128B: - case Hexagon::V6_vS32b_nt_ai_128B: - case Hexagon::V6_vL32Ub_ai_128B: - case Hexagon::V6_vS32Ub_ai_128B: - return isShiftedInt<4,7>(Offset); + case Hexagon::V6_vS32Ub_ai: { + unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass); + assert(isPowerOf2_32(VectorSize)); + if (Offset & (VectorSize-1)) + return false; + return isInt<4>(Offset >> Log2_32(VectorSize)); + } case Hexagon::J2_loop0i: case Hexagon::J2_loop1i: @@ -3230,15 +3128,6 @@ int HexagonInstrInfo::getDotCurOp(const MachineInstr &MI) const { return Hexagon::V6_vL32b_nt_cur_pi; case Hexagon::V6_vL32b_nt_ai: return Hexagon::V6_vL32b_nt_cur_ai; - //128B - case Hexagon::V6_vL32b_pi_128B: - return Hexagon::V6_vL32b_cur_pi_128B; - case Hexagon::V6_vL32b_ai_128B: - return Hexagon::V6_vL32b_cur_ai_128B; - case Hexagon::V6_vL32b_nt_pi_128B: - return Hexagon::V6_vL32b_nt_cur_pi_128B; - case Hexagon::V6_vL32b_nt_ai_128B: - return Hexagon::V6_vL32b_nt_cur_ai_128B; } return 0; } @@ -3255,15 +3144,6 @@ int HexagonInstrInfo::getNonDotCurOp(const MachineInstr &MI) const { return Hexagon::V6_vL32b_nt_pi; case Hexagon::V6_vL32b_nt_cur_ai: return Hexagon::V6_vL32b_nt_ai; - //128B - case Hexagon::V6_vL32b_cur_pi_128B: - return Hexagon::V6_vL32b_pi_128B; - case Hexagon::V6_vL32b_cur_ai_128B: - return Hexagon::V6_vL32b_ai_128B; - case Hexagon::V6_vL32b_nt_cur_pi_128B: - return Hexagon::V6_vL32b_nt_pi_128B; - case Hexagon::V6_vL32b_nt_cur_ai_128B: - return Hexagon::V6_vL32b_nt_ai_128B; } return 0; } @@ -3383,13 +3263,6 @@ int HexagonInstrInfo::getDotNewOp(const MachineInstr &MI) const { case Hexagon::V6_vS32b_pi: return Hexagon::V6_vS32b_new_pi; - - // 128B - case Hexagon::V6_vS32b_ai_128B: - return Hexagon::V6_vS32b_new_ai_128B; - - case Hexagon::V6_vS32b_pi_128B: - return Hexagon::V6_vS32b_new_pi_128B; } return 0; } @@ -3556,7 +3429,8 @@ int HexagonInstrInfo::getDotOldOp(const MachineInstr &MI) const { HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( const MachineInstr &MI) const { unsigned DstReg, SrcReg, Src1Reg, Src2Reg; - auto &HRI = getRegisterInfo(); + const MachineFunction &MF = *MI.getParent()->getParent(); + const auto &HRI = *MF.getSubtarget().getRegisterInfo(); switch (MI.getOpcode()) { default: @@ -3924,14 +3798,16 @@ int HexagonInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const { - auto &RI = getRegisterInfo(); + const MachineFunction &MF = *DefMI.getParent()->getParent(); + const auto &HRI = *MF.getSubtarget().getRegisterInfo(); + // Get DefIdx and UseIdx for super registers. MachineOperand DefMO = DefMI.getOperand(DefIdx); - if (RI.isPhysicalRegister(DefMO.getReg())) { + if (HRI.isPhysicalRegister(DefMO.getReg())) { if (DefMO.isImplicit()) { - for (MCSuperRegIterator SR(DefMO.getReg(), &RI); SR.isValid(); ++SR) { - int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &RI); + for (MCSuperRegIterator SR(DefMO.getReg(), &HRI); SR.isValid(); ++SR) { + int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &HRI); if (Idx != -1) { DefIdx = Idx; break; @@ -3941,8 +3817,8 @@ int HexagonInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, MachineOperand UseMO = UseMI.getOperand(UseIdx); if (UseMO.isImplicit()) { - for (MCSuperRegIterator SR(UseMO.getReg(), &RI); SR.isValid(); ++SR) { - int Idx = UseMI.findRegisterUseOperandIdx(*SR, false, &RI); + for (MCSuperRegIterator SR(UseMO.getReg(), &HRI); SR.isValid(); ++SR) { + int Idx = UseMI.findRegisterUseOperandIdx(*SR, false, &HRI); if (Idx != -1) { UseIdx = Idx; break; @@ -3999,12 +3875,13 @@ unsigned HexagonInstrInfo::getMemAccessSize(const MachineInstr &MI) const { if (Size != 0) return Size; + const MachineFunction &MF = *MI.getParent()->getParent(); + const auto &HRI = *MF.getSubtarget().getRegisterInfo(); + // Handle vector access sizes. switch (S) { - case HexagonII::Vector64Access: - return 64; - case HexagonII::Vector128Access: - return 128; + case HexagonII::HVXVectorAccess: + return HRI.getSpillSize(Hexagon::HvxVRRegClass); default: llvm_unreachable("Unexpected instruction"); } diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h index 0436ce3ac475..5f81fc59f4f1 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h @@ -14,7 +14,6 @@ #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H #define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H -#include "HexagonRegisterInfo.h" #include "MCTargetDesc/HexagonBaseInfo.h" #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/SmallVector.h" @@ -32,10 +31,9 @@ namespace llvm { struct EVT; class HexagonSubtarget; +class HexagonRegisterInfo; class HexagonInstrInfo : public HexagonGenInstrInfo { - const HexagonRegisterInfo RI; - virtual void anchor(); public: @@ -327,8 +325,6 @@ public: /// HexagonInstrInfo specifics. /// - const HexagonRegisterInfo &getRegisterInfo() const { return RI; } - unsigned createVR(MachineFunction* MF, MVT VT) const; bool isAbsoluteSet(const MachineInstr &MI) const; @@ -387,7 +383,8 @@ public: const MachineInstr &MI2) const; bool isHVXVec(const MachineInstr &MI) const; bool isValidAutoIncImm(const EVT VT, const int Offset) const; - bool isValidOffset(unsigned Opcode, int Offset, bool Extend = true) const; + bool isValidOffset(unsigned Opcode, int Offset, + const TargetRegisterInfo *TRI, bool Extend = true) const; bool isVecAcc(const MachineInstr &MI) const; bool isVecALU(const MachineInstr &MI) const; bool isVecUsableNextPacket(const MachineInstr &ProdMI, diff --git a/llvm/lib/Target/Hexagon/HexagonIntrinsics.td b/llvm/lib/Target/Hexagon/HexagonIntrinsics.td index 104a28654dd5..8a77b7760df1 100644 --- a/llvm/lib/Target/Hexagon/HexagonIntrinsics.td +++ b/llvm/lib/Target/Hexagon/HexagonIntrinsics.td @@ -1348,17 +1348,11 @@ def: T_stc_pat; def: T_stc_pat; multiclass MaskedStore { - def : Pat<(IntID VecPredRegs:$src1, IntRegs:$src2, VectorRegs:$src3), - (MI VecPredRegs:$src1, IntRegs:$src2, #0, VectorRegs:$src3)>, - Requires<[UseHVXSgl]>; - - def : Pat<(!cast(IntID#"_128B") VecPredRegs128B:$src1, - IntRegs:$src2, - VectorRegs128B:$src3), - (!cast(MI#"_128B") VecPredRegs128B:$src1, - IntRegs:$src2, #0, - VectorRegs128B:$src3)>, - Requires<[UseHVXDbl]>; + def : Pat<(IntID HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), + (MI HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>; + def : Pat<(!cast(IntID#"_128B") HvxQR:$src1, IntRegs:$src2, + HvxVR:$src3), + (MI HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>; } defm : MaskedStore ; diff --git a/llvm/lib/Target/Hexagon/HexagonIntrinsicsV60.td b/llvm/lib/Target/Hexagon/HexagonIntrinsicsV60.td index f438b3e0368f..d26a3d1ae540 100644 --- a/llvm/lib/Target/Hexagon/HexagonIntrinsicsV60.td +++ b/llvm/lib/Target/Hexagon/HexagonIntrinsicsV60.td @@ -13,445 +13,298 @@ let AddedComplexity = 100 in { -def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 VecDblRegs:$src1))), - (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), vsub_lo)) >, - Requires<[UseHVXSgl]>; +def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 HvxWR:$src1))), + (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_lo)) >; -def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 VecDblRegs:$src1))), - (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), vsub_hi)) >, - Requires<[UseHVXSgl]>; +def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 HvxWR:$src1))), + (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_hi)) >; -def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 VecDblRegs128B:$src1))), - (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1), vsub_lo)) >, - Requires<[UseHVXDbl]>; +def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 HvxWR:$src1))), + (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_lo)) >; -def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 VecDblRegs128B:$src1))), - (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1), vsub_hi)) >, - Requires<[UseHVXDbl]>; +def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))), + (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_hi)) >; } -def : Pat <(v512i1 (bitconvert (v16i32 VectorRegs:$src1))), - (v512i1 (V6_vandvrt(v16i32 VectorRegs:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXSgl]>; +def : Pat <(v512i1 (bitconvert (v16i32 HvxVR:$src1))), + (v512i1 (V6_vandvrt(v16i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; -def : Pat <(v512i1 (bitconvert (v32i16 VectorRegs:$src1))), - (v512i1 (V6_vandvrt(v32i16 VectorRegs:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXSgl]>; +def : Pat <(v512i1 (bitconvert (v32i16 HvxVR:$src1))), + (v512i1 (V6_vandvrt(v32i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; -def : Pat <(v512i1 (bitconvert (v64i8 VectorRegs:$src1))), - (v512i1 (V6_vandvrt(v64i8 VectorRegs:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXSgl]>; +def : Pat <(v512i1 (bitconvert (v64i8 HvxVR:$src1))), + (v512i1 (V6_vandvrt(v64i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; -def : Pat <(v512i1 (bitconvert (v8i64 VectorRegs:$src1))), - (v512i1 (V6_vandvrt(v8i64 VectorRegs:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXSgl]>; +def : Pat <(v512i1 (bitconvert (v8i64 HvxVR:$src1))), + (v512i1 (V6_vandvrt(v8i64 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; -def : Pat <(v16i32 (bitconvert (v512i1 VecPredRegs:$src1))), - (v16i32 (V6_vandqrt(v512i1 VecPredRegs:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXSgl]>; +def : Pat <(v16i32 (bitconvert (v512i1 HvxQR:$src1))), + (v16i32 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; -def : Pat <(v32i16 (bitconvert (v512i1 VecPredRegs:$src1))), - (v32i16 (V6_vandqrt(v512i1 VecPredRegs:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXSgl]>; +def : Pat <(v32i16 (bitconvert (v512i1 HvxQR:$src1))), + (v32i16 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; -def : Pat <(v64i8 (bitconvert (v512i1 VecPredRegs:$src1))), - (v64i8 (V6_vandqrt(v512i1 VecPredRegs:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXSgl]>; +def : Pat <(v64i8 (bitconvert (v512i1 HvxQR:$src1))), + (v64i8 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; -def : Pat <(v8i64 (bitconvert (v512i1 VecPredRegs:$src1))), - (v8i64 (V6_vandqrt(v512i1 VecPredRegs:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXSgl]>; +def : Pat <(v8i64 (bitconvert (v512i1 HvxQR:$src1))), + (v8i64 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; -def : Pat <(v1024i1 (bitconvert (v32i32 VectorRegs128B:$src1))), - (v1024i1 (V6_vandvrt_128B(v32i32 VectorRegs128B:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXDbl]>; +def : Pat <(v1024i1 (bitconvert (v32i32 HvxVR:$src1))), + (v1024i1 (V6_vandvrt (v32i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; -def : Pat <(v1024i1 (bitconvert (v64i16 VectorRegs128B:$src1))), - (v1024i1 (V6_vandvrt_128B(v64i16 VectorRegs128B:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXDbl]>; +def : Pat <(v1024i1 (bitconvert (v64i16 HvxVR:$src1))), + (v1024i1 (V6_vandvrt (v64i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; -def : Pat <(v1024i1 (bitconvert (v128i8 VectorRegs128B:$src1))), - (v1024i1 (V6_vandvrt_128B(v128i8 VectorRegs128B:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXDbl]>; +def : Pat <(v1024i1 (bitconvert (v128i8 HvxVR:$src1))), + (v1024i1 (V6_vandvrt (v128i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; -def : Pat <(v1024i1 (bitconvert (v16i64 VectorRegs128B:$src1))), - (v1024i1 (V6_vandvrt_128B(v16i64 VectorRegs128B:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXDbl]>; +def : Pat <(v1024i1 (bitconvert (v16i64 HvxVR:$src1))), + (v1024i1 (V6_vandvrt (v16i64 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; -def : Pat <(v32i32 (bitconvert (v1024i1 VecPredRegs128B:$src1))), - (v32i32 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXDbl]>; +def : Pat <(v32i32 (bitconvert (v1024i1 HvxQR:$src1))), + (v32i32 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; -def : Pat <(v64i16 (bitconvert (v1024i1 VecPredRegs128B:$src1))), - (v64i16 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXDbl]>; +def : Pat <(v64i16 (bitconvert (v1024i1 HvxQR:$src1))), + (v64i16 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; -def : Pat <(v128i8 (bitconvert (v1024i1 VecPredRegs128B:$src1))), - (v128i8 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXDbl]>; +def : Pat <(v128i8 (bitconvert (v1024i1 HvxQR:$src1))), + (v128i8 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; -def : Pat <(v16i64 (bitconvert (v1024i1 VecPredRegs128B:$src1))), - (v16i64 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXDbl]>; +def : Pat <(v16i64 (bitconvert (v1024i1 HvxQR:$src1))), + (v16i64 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; let AddedComplexity = 140 in { -def : Pat <(store (v512i1 VecPredRegs:$src1), (i32 IntRegs:$addr)), +def : Pat <(store (v512i1 HvxQR:$src1), (i32 IntRegs:$addr)), (V6_vS32b_ai IntRegs:$addr, 0, - (v16i32 (V6_vandqrt (v512i1 VecPredRegs:$src1), - (A2_tfrsi 0x01010101))))>, - Requires<[UseHVXSgl]>; + (v16i32 (V6_vandqrt (v512i1 HvxQR:$src1), + (A2_tfrsi 0x01010101))))>; def : Pat <(v512i1 (load (i32 IntRegs:$addr))), (v512i1 (V6_vandvrt - (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXSgl]>; + (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>; -def : Pat <(store (v1024i1 VecPredRegs128B:$src1), (i32 IntRegs:$addr)), - (V6_vS32b_ai_128B IntRegs:$addr, 0, - (v32i32 (V6_vandqrt_128B (v1024i1 VecPredRegs128B:$src1), - (A2_tfrsi 0x01010101))))>, - Requires<[UseHVXDbl]>; +def : Pat <(store (v1024i1 HvxQR:$src1), (i32 IntRegs:$addr)), + (V6_vS32b_ai IntRegs:$addr, 0, + (v32i32 (V6_vandqrt (v1024i1 HvxQR:$src1), + (A2_tfrsi 0x01010101))))>; def : Pat <(v1024i1 (load (i32 IntRegs:$addr))), - (v1024i1 (V6_vandvrt_128B - (v32i32 (V6_vL32b_ai_128B IntRegs:$addr, 0)), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXDbl]>; + (v1024i1 (V6_vandvrt + (v32i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>; } multiclass T_R_pat { - def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>; def: Pat<(!cast(IntID#"_128B") IntRegs:$src1), - (!cast(MI#"_128B") IntRegs:$src1)>, - Requires<[UseHVXDbl]>; + (MI IntRegs:$src1)>; } multiclass T_V_pat { - def: Pat<(IntID VectorRegs:$src1), - (MI VectorRegs:$src1)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxVR:$src1), + (MI HvxVR:$src1)>; - def: Pat<(!cast(IntID#"_128B") VectorRegs128B:$src1), - (!cast(MI#"_128B") VectorRegs128B:$src1)>, - Requires<[UseHVXDbl]>; + def: Pat<(!cast(IntID#"_128B") HvxVR:$src1), + (MI HvxVR:$src1)>; } multiclass T_W_pat { - def: Pat<(IntID VecDblRegs:$src1), - (MI VecDblRegs:$src1)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxWR:$src1), + (MI HvxWR:$src1)>; - def: Pat<(!cast(IntID#"_128B") VecDblRegs128B:$src1), - (!cast(MI#"_128B") VecDblRegs128B:$src1)>, - Requires<[UseHVXDbl]>; + def: Pat<(!cast(IntID#"_128B") HvxWR:$src1), + (MI HvxWR:$src1)>; } multiclass T_Q_pat { - def: Pat<(IntID VecPredRegs:$src1), - (MI VecPredRegs:$src1)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxQR:$src1), + (MI HvxQR:$src1)>; - def: Pat<(!cast(IntID#"_128B") VecPredRegs128B:$src1), - (!cast(MI#"_128B") VecPredRegs128B:$src1)>, - Requires<[UseHVXDbl]>; + def: Pat<(!cast(IntID#"_128B") HvxQR:$src1), + (MI HvxQR:$src1)>; } multiclass T_WR_pat { - def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2), - (MI VecDblRegs:$src1, IntRegs:$src2)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxWR:$src1, IntRegs:$src2), + (MI HvxWR:$src1, IntRegs:$src2)>; - def: Pat<(!cast(IntID#"_128B")VecDblRegs128B:$src1, IntRegs:$src2), - (!cast(MI#"_128B")VecDblRegs128B:$src1, IntRegs:$src2)>, - Requires<[UseHVXDbl]>; + def: Pat<(!cast(IntID#"_128B")HvxWR:$src1, IntRegs:$src2), + (MI HvxWR:$src1, IntRegs:$src2)>; } multiclass T_VR_pat { - def: Pat<(IntID VectorRegs:$src1, IntRegs:$src2), - (MI VectorRegs:$src1, IntRegs:$src2)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxVR:$src1, IntRegs:$src2), + (MI HvxVR:$src1, IntRegs:$src2)>; - def: Pat<(!cast(IntID#"_128B")VectorRegs128B:$src1, IntRegs:$src2), - (!cast(MI#"_128B")VectorRegs128B:$src1, IntRegs:$src2)>, - Requires<[UseHVXDbl]>; + def: Pat<(!cast(IntID#"_128B")HvxVR:$src1, IntRegs:$src2), + (MI HvxVR:$src1, IntRegs:$src2)>; } multiclass T_WV_pat { - def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2), - (MI VecDblRegs:$src1, VectorRegs:$src2)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxWR:$src1, HvxVR:$src2), + (MI HvxWR:$src1, HvxVR:$src2)>; - def: Pat<(!cast(IntID#"_128B") VecDblRegs128B:$src1, - VectorRegs128B:$src2), - (!cast(MI#"_128B") VecDblRegs128B:$src1, - VectorRegs128B:$src2)>, - Requires<[UseHVXDbl]>; + def: Pat<(!cast(IntID#"_128B") HvxWR:$src1, HvxVR:$src2), + (MI HvxWR:$src1, HvxVR:$src2)>; } multiclass T_WW_pat { - def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2), - (MI VecDblRegs:$src1, VecDblRegs:$src2)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxWR:$src1, HvxWR:$src2), + (MI HvxWR:$src1, HvxWR:$src2)>; - def: Pat<(!cast(IntID#"_128B") VecDblRegs128B:$src1, - VecDblRegs128B:$src2), - (!cast(MI#"_128B") VecDblRegs128B:$src1, - VecDblRegs128B:$src2)>, - Requires<[UseHVXDbl]>; + def: Pat<(!cast(IntID#"_128B") HvxWR:$src1, HvxWR:$src2), + (MI HvxWR:$src1, HvxWR:$src2)>; } multiclass T_VV_pat { - def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2), - (MI VectorRegs:$src1, VectorRegs:$src2)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxVR:$src1, HvxVR:$src2), + (MI HvxVR:$src1, HvxVR:$src2)>; - def: Pat<(!cast(IntID#"_128B") VectorRegs128B:$src1, - VectorRegs128B:$src2), - (!cast(MI#"_128B") VectorRegs128B:$src1, - VectorRegs128B:$src2)>, - Requires<[UseHVXDbl]>; + def: Pat<(!cast(IntID#"_128B") HvxVR:$src1, HvxVR:$src2), + (MI HvxVR:$src1, HvxVR:$src2)>; } multiclass T_QR_pat { - def: Pat<(IntID VecPredRegs:$src1, IntRegs:$src2), - (MI VecPredRegs:$src1, IntRegs:$src2)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxQR:$src1, IntRegs:$src2), + (MI HvxQR:$src1, IntRegs:$src2)>; - def: Pat<(!cast(IntID#"_128B") VecPredRegs128B:$src1, - IntRegs:$src2), - (!cast(MI#"_128B") VecPredRegs128B:$src1, - IntRegs:$src2)>, - Requires<[UseHVXDbl]>; + def: Pat<(!cast(IntID#"_128B") HvxQR:$src1, IntRegs:$src2), + (MI HvxQR:$src1, IntRegs:$src2)>; } multiclass T_QQ_pat { - def: Pat<(IntID VecPredRegs:$src1, VecPredRegs:$src2), - (MI VecPredRegs:$src1, VecPredRegs:$src2)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxQR:$src1, HvxQR:$src2), + (MI HvxQR:$src1, HvxQR:$src2)>; - def: Pat<(!cast(IntID#"_128B") VecPredRegs128B:$src1, - VecPredRegs128B:$src2), - (!cast(MI#"_128B") VecPredRegs128B:$src1, - VecPredRegs128B:$src2)>, - Requires<[UseHVXDbl]>; + def: Pat<(!cast(IntID#"_128B") HvxQR:$src1, HvxQR:$src2), + (MI HvxQR:$src1, HvxQR:$src2)>; } multiclass T_WWR_pat { - def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3), - (MI VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>; - def: Pat<(!cast(IntID#"_128B") VecDblRegs128B:$src1, - VecDblRegs128B:$src2, + def: Pat<(!cast(IntID#"_128B") HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (!cast(MI#"_128B") VecDblRegs128B:$src1, - VecDblRegs128B:$src2, - IntRegs:$src3)>, - Requires<[UseHVXDbl]>; + (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>; } multiclass T_VVR_pat { - def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3), - (MI VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>; - def: Pat<(!cast(IntID#"_128B") VectorRegs128B:$src1, - VectorRegs128B:$src2, + def: Pat<(!cast(IntID#"_128B") HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (!cast(MI#"_128B") VectorRegs128B:$src1, - VectorRegs128B:$src2, - IntRegs:$src3)>, - Requires<[UseHVXDbl]>; + (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>; } multiclass T_WVR_pat { - def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, IntRegs:$src3), - (MI VecDblRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), + (MI HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>; - def: Pat<(!cast(IntID#"_128B") VecDblRegs128B:$src1, - VectorRegs128B:$src2, + def: Pat<(!cast(IntID#"_128B") HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), - (!cast(MI#"_128B") VecDblRegs128B:$src1, - VectorRegs128B:$src2, - IntRegs:$src3)>, - Requires<[UseHVXDbl]>; + (MI HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>; } multiclass T_VWR_pat { - def: Pat<(IntID VectorRegs:$src1, VecDblRegs:$src2, IntRegs:$src3), - (MI VectorRegs:$src1, VecDblRegs:$src2, IntRegs:$src3)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxVR:$src1, HvxWR:$src2, IntRegs:$src3), + (MI HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>; - def: Pat<(!cast(IntID#"_128B") VectorRegs128B:$src1, - VecDblRegs128B:$src2, + def: Pat<(!cast(IntID#"_128B") HvxVR:$src1, HvxWR:$src2, IntRegs:$src3), - (!cast(MI#"_128B") VectorRegs128B:$src1, - VecDblRegs128B:$src2, - IntRegs:$src3)>, - Requires<[UseHVXDbl]>; + (MI HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>; } multiclass T_VVV_pat { - def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3), - (MI VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>; - def: Pat<(!cast(IntID#"_128B") VectorRegs128B:$src1, - VectorRegs128B:$src2, - VectorRegs128B:$src3), - (!cast(MI#"_128B") VectorRegs128B:$src1, - VectorRegs128B:$src2, - VectorRegs128B:$src3)>, - Requires<[UseHVXDbl]>; + def: Pat<(!cast(IntID#"_128B") HvxVR:$src1, HvxVR:$src2, + HvxVR:$src3), + (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>; } multiclass T_WVV_pat { - def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3), - (MI VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>; - def: Pat<(!cast(IntID#"_128B") VecDblRegs128B:$src1, - VectorRegs128B:$src2, - VectorRegs128B:$src3), - (!cast(MI#"_128B") VecDblRegs128B:$src1, - VectorRegs128B:$src2, - VectorRegs128B:$src3)>, - Requires<[UseHVXDbl]>; + def: Pat<(!cast(IntID#"_128B") HvxWR:$src1, HvxVR:$src2, + HvxVR:$src3), + (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>; } multiclass T_QVV_pat { - def: Pat<(IntID VecPredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3), - (MI VecPredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (MI HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>; - def: Pat<(!cast(IntID#"_128B") VecPredRegs128B:$src1, - VectorRegs128B:$src2, - VectorRegs128B:$src3), - (!cast(MI#"_128B") VecPredRegs128B:$src1, - VectorRegs128B:$src2, - VectorRegs128B:$src3)>, - Requires<[UseHVXDbl]>; + def: Pat<(!cast(IntID#"_128B") HvxQR:$src1, HvxVR:$src2, + HvxVR:$src3), + (MI HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>; } multiclass T_VQR_pat { - def: Pat<(IntID VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3), - (MI VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxVR:$src1, HvxQR:$src2, IntRegs:$src3), + (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>; - def: Pat<(!cast(IntID#"_128B") VectorRegs128B:$src1, - VecPredRegs128B:$src2, + def: Pat<(!cast(IntID#"_128B") HvxVR:$src1, HvxQR:$src2, IntRegs:$src3), - (!cast(MI#"_128B") VectorRegs128B:$src1, - VecPredRegs128B:$src2, - IntRegs:$src3)>, - Requires<[UseHVXDbl]>; + (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>; } multiclass T_QVR_pat { - def: Pat<(IntID VecPredRegs:$src1, VectorRegs:$src2, IntRegs:$src3), - (MI VecPredRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxQR:$src1, HvxVR:$src2, IntRegs:$src3), + (MI HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>; - def: Pat<(!cast(IntID#"_128B") VecPredRegs128B:$src1, - VectorRegs128B:$src2, + def: Pat<(!cast(IntID#"_128B") HvxQR:$src1, HvxVR:$src2, IntRegs:$src3), - (!cast(MI#"_128B") VecPredRegs128B:$src1, - VectorRegs128B:$src2, - IntRegs:$src3)>, - Requires<[UseHVXDbl]>; + (MI HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>; } multiclass T_VVI_pat { - def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, imm:$src3), - (MI VectorRegs:$src1, VectorRegs:$src2, imm:$src3)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, imm:$src3), + (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>; - def: Pat<(!cast(IntID#"_128B") VectorRegs128B:$src1, - VectorRegs128B:$src2, imm:$src3), - (!cast(MI#"_128B") VectorRegs128B:$src1, - VectorRegs128B:$src2, imm:$src3)>, - Requires<[UseHVXDbl]>; + def: Pat<(!cast(IntID#"_128B") HvxVR:$src1, + HvxVR:$src2, imm:$src3), + (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>; } multiclass T_WRI_pat { - def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2, imm:$src3), - (MI VecDblRegs:$src1, IntRegs:$src2, imm:$src3)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxWR:$src1, IntRegs:$src2, imm:$src3), + (MI HvxWR:$src1, IntRegs:$src2, imm:$src3)>; - def: Pat<(!cast(IntID#"_128B") VecDblRegs128B:$src1, + def: Pat<(!cast(IntID#"_128B") HvxWR:$src1, IntRegs:$src2, imm:$src3), - (!cast(MI#"_128B") VecDblRegs128B:$src1, - IntRegs:$src2, imm:$src3)>, - Requires<[UseHVXDbl]>; + (MI HvxWR:$src1, IntRegs:$src2, imm:$src3)>; } multiclass T_WWRI_pat { - def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3, imm:$src4), - (MI VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3, imm:$src4)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4), + (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4)>; - def: Pat<(!cast(IntID#"_128B") VecDblRegs128B:$src1, - VecDblRegs128B:$src2, + def: Pat<(!cast(IntID#"_128B") HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4), - (!cast(MI#"_128B") VecDblRegs128B:$src1, - VecDblRegs128B:$src2, - IntRegs:$src3, imm:$src4)>, - Requires<[UseHVXDbl]>; + (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4)>; } multiclass T_VVVR_pat { - def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, - IntRegs:$src4), - (MI VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, - IntRegs:$src4)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4), + (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>; - def: Pat<(!cast(IntID#"_128B") VectorRegs128B:$src1, - VectorRegs128B:$src2, - VectorRegs128B:$src3, - IntRegs:$src4), - (!cast(MI#"_128B") VectorRegs128B:$src1, - VectorRegs128B:$src2, - VectorRegs128B:$src3, - IntRegs:$src4)>, - Requires<[UseHVXDbl]>; + def: Pat<(!cast(IntID#"_128B") HvxVR:$src1, HvxVR:$src2, + HvxVR:$src3, IntRegs:$src4), + (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>; } multiclass T_WVVR_pat { - def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, - IntRegs:$src4), - (MI VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, - IntRegs:$src4)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4), + (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>; - def: Pat<(!cast(IntID#"_128B") VecDblRegs128B:$src1, - VectorRegs128B:$src2, - VectorRegs128B:$src3, - IntRegs:$src4), - (!cast(MI#"_128B") VecDblRegs128B:$src1, - VectorRegs128B:$src2, - VectorRegs128B:$src3, - IntRegs:$src4)>, - Requires<[UseHVXDbl]>; + def: Pat<(!cast(IntID#"_128B") HvxWR:$src1, HvxVR:$src2, + HvxVR:$src3, IntRegs:$src4), + (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>; } defm : T_WR_pat ; @@ -793,11 +646,10 @@ defm : T_VR_pat ; //def : T_PPQ_pat ; def: Pat<(v64i16 (trunc v64i32:$Vdd)), - (v64i16 (V6_vpackwh_sat_128B - (v32i32 (V6_hi_128B VecDblRegs128B:$Vdd)), - (v32i32 (V6_lo_128B VecDblRegs128B:$Vdd))))>, - Requires<[UseHVXDbl]>; + (v64i16 (V6_vpackwh_sat + (v32i32 (V6_hi HvxWR:$Vdd)), + (v32i32 (V6_lo HvxWR:$Vdd))))>; def: Pat<(int_hexagon_V6_vd0), (V6_vd0)>; -def: Pat<(int_hexagon_V6_vd0_128B), (V6_vd0_128B)>; +def: Pat<(int_hexagon_V6_vd0_128B), (V6_vd0)>; diff --git a/llvm/lib/Target/Hexagon/HexagonMapAsm2IntrinV62.gen.td b/llvm/lib/Target/Hexagon/HexagonMapAsm2IntrinV62.gen.td index 0b4ac14c7a47..b7b0de0efaea 100644 --- a/llvm/lib/Target/Hexagon/HexagonMapAsm2IntrinV62.gen.td +++ b/llvm/lib/Target/Hexagon/HexagonMapAsm2IntrinV62.gen.td @@ -8,147 +8,123 @@ //===----------------------------------------------------------------------===// multiclass T_VR_HVX_gen_pat { - def: Pat<(IntID VectorRegs:$src1, IntRegs:$src2), - (MI VectorRegs:$src1, IntRegs:$src2)>, - Requires<[UseHVXSgl]>; - def: Pat<(!cast(IntID#"_128B") VectorRegs128B:$src1, IntRegs:$src2), - (!cast(MI#"_128B") VectorRegs128B:$src1, IntRegs:$src2)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxVR:$src1, IntRegs:$src2), + (MI HvxVR:$src1, IntRegs:$src2)>; + def: Pat<(!cast(IntID#"_128B") HvxVR:$src1, IntRegs:$src2), + (MI HvxVR:$src1, IntRegs:$src2)>; } multiclass T_VVL_HVX_gen_pat { - def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, IntRegsLow8:$src3), - (MI VectorRegs:$src1, VectorRegs:$src2, IntRegsLow8:$src3)>, - Requires<[UseHVXSgl]>; - def: Pat<(!cast(IntID#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, IntRegsLow8:$src3), - (!cast(MI#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, IntRegsLow8:$src3)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>; + def: Pat<(!cast(IntID#"_128B") HvxVR:$src1, HvxVR:$src2, + IntRegsLow8:$src3), + (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>; } multiclass T_VV_HVX_gen_pat { - def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2), - (MI VectorRegs:$src1, VectorRegs:$src2)>, - Requires<[UseHVXSgl]>; - def: Pat<(!cast(IntID#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2), - (!cast(MI#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxVR:$src1, HvxVR:$src2), + (MI HvxVR:$src1, HvxVR:$src2)>; + def: Pat<(!cast(IntID#"_128B") HvxVR:$src1, HvxVR:$src2), + (MI HvxVR:$src1, HvxVR:$src2)>; } multiclass T_WW_HVX_gen_pat { - def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2), - (MI VecDblRegs:$src1, VecDblRegs:$src2)>, - Requires<[UseHVXSgl]>; - def: Pat<(!cast(IntID#"_128B") VecDblRegs128B:$src1, VecDblRegs128B:$src2), - (!cast(MI#"_128B") VecDblRegs128B:$src1, VecDblRegs128B:$src2)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxWR:$src1, HvxWR:$src2), + (MI HvxWR:$src1, HvxWR:$src2)>; + def: Pat<(!cast(IntID#"_128B") HvxWR:$src1, HvxWR:$src2), + (MI HvxWR:$src1, HvxWR:$src2)>; } multiclass T_WVV_HVX_gen_pat { - def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3), - (MI VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>, - Requires<[UseHVXSgl]>; - def: Pat<(!cast(IntID#"_128B") VecDblRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3), - (!cast(MI#"_128B") VecDblRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>; + def: Pat<(!cast(IntID#"_128B") HvxWR:$src1, HvxVR:$src2, + HvxVR:$src3), + (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>; } multiclass T_WR_HVX_gen_pat { - def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2), - (MI VecDblRegs:$src1, IntRegs:$src2)>, - Requires<[UseHVXSgl]>; - def: Pat<(!cast(IntID#"_128B") VecDblRegs128B:$src1, IntRegs:$src2), - (!cast(MI#"_128B") VecDblRegs128B:$src1, IntRegs:$src2)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxWR:$src1, IntRegs:$src2), + (MI HvxWR:$src1, IntRegs:$src2)>; + def: Pat<(!cast(IntID#"_128B") HvxWR:$src1, IntRegs:$src2), + (MI HvxWR:$src1, IntRegs:$src2)>; } multiclass T_WWR_HVX_gen_pat { - def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3), - (MI VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3)>, - Requires<[UseHVXSgl]>; - def: Pat<(!cast(IntID#"_128B") VecDblRegs128B:$src1, VecDblRegs128B:$src2, IntRegs:$src3), - (!cast(MI#"_128B") VecDblRegs128B:$src1, VecDblRegs128B:$src2, IntRegs:$src3)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>; + def: Pat<(!cast(IntID#"_128B") HvxWR:$src1, HvxWR:$src2, + IntRegs:$src3), + (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>; } multiclass T_VVR_HVX_gen_pat { - def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3), - (MI VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>, - Requires<[UseHVXSgl]>; - def: Pat<(!cast(IntID#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, IntRegs:$src3), - (!cast(MI#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, IntRegs:$src3)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>; + def: Pat<(!cast(IntID#"_128B") HvxVR:$src1, HvxVR:$src2, + IntRegs:$src3), + (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>; } multiclass T_ZR_HVX_gen_pat { - def: Pat<(IntID VecPredRegs:$src1, IntRegs:$src2), - (MI VecPredRegs:$src1, IntRegs:$src2)>, - Requires<[UseHVXSgl]>; - def: Pat<(!cast(IntID#"_128B") VecPredRegs128B:$src1, IntRegs:$src2), - (!cast(MI#"_128B") VecPredRegs128B:$src1, IntRegs:$src2)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxQR:$src1, IntRegs:$src2), + (MI HvxQR:$src1, IntRegs:$src2)>; + def: Pat<(!cast(IntID#"_128B") HvxQR:$src1, IntRegs:$src2), + (MI HvxQR:$src1, IntRegs:$src2)>; } multiclass T_VZR_HVX_gen_pat { - def: Pat<(IntID VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3), - (MI VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3)>, - Requires<[UseHVXSgl]>; - def: Pat<(!cast(IntID#"_128B") VectorRegs128B:$src1, VecPredRegs128B:$src2, IntRegs:$src3), - (!cast(MI#"_128B") VectorRegs128B:$src1, VecPredRegs128B:$src2, IntRegs:$src3)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxVR:$src1, HvxQR:$src2, IntRegs:$src3), + (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>; + def: Pat<(!cast(IntID#"_128B") HvxVR:$src1, HvxQR:$src2, + IntRegs:$src3), + (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>; } multiclass T_ZV_HVX_gen_pat { - def: Pat<(IntID VecPredRegs:$src1, VectorRegs:$src2), - (MI VecPredRegs:$src1, VectorRegs:$src2)>, - Requires<[UseHVXSgl]>; - def: Pat<(!cast(IntID#"_128B") VecPredRegs128B:$src1, VectorRegs128B:$src2), - (!cast(MI#"_128B") VecPredRegs128B:$src1, VectorRegs128B:$src2)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxQR:$src1, HvxVR:$src2), + (MI HvxQR:$src1, HvxVR:$src2)>; + def: Pat<(!cast(IntID#"_128B") HvxQR:$src1, HvxVR:$src2), + (MI HvxQR:$src1, HvxVR:$src2)>; } multiclass T_R_HVX_gen_pat { def: Pat<(IntID IntRegs:$src1), - (MI IntRegs:$src1)>, - Requires<[UseHVXSgl]>; + (MI IntRegs:$src1)>; def: Pat<(!cast(IntID#"_128B") IntRegs:$src1), - (!cast(MI#"_128B") IntRegs:$src1)>, - Requires<[UseHVXDbl]>; + (MI IntRegs:$src1)>; } multiclass T_ZZ_HVX_gen_pat { - def: Pat<(IntID VecPredRegs:$src1, VecPredRegs:$src2), - (MI VecPredRegs:$src1, VecPredRegs:$src2)>, - Requires<[UseHVXSgl]>; - def: Pat<(!cast(IntID#"_128B") VecPredRegs128B:$src1, VecPredRegs128B:$src2), - (!cast(MI#"_128B") VecPredRegs128B:$src1, VecPredRegs128B:$src2)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxQR:$src1, HvxQR:$src2), + (MI HvxQR:$src1, HvxQR:$src2)>; + def: Pat<(!cast(IntID#"_128B") HvxQR:$src1, HvxQR:$src2), + (MI HvxQR:$src1, HvxQR:$src2)>; } multiclass T_VVI_HVX_gen_pat { - def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, imm:$src3), - (MI VectorRegs:$src1, VectorRegs:$src2, imm:$src3)>, - Requires<[UseHVXSgl]>; - def: Pat<(!cast(IntID#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, imm:$src3), - (!cast(MI#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, imm:$src3)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, imm:$src3), + (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>; + def: Pat<(!cast(IntID#"_128B") HvxVR:$src1, HvxVR:$src2, + imm:$src3), + (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>; } multiclass T_VVVI_HVX_gen_pat { - def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, imm:$src4), - (MI VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, imm:$src4)>, - Requires<[UseHVXSgl]>; - def: Pat<(!cast(IntID#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3, imm:$src4), - (!cast(MI#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3, imm:$src4)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4), + (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>; + def: Pat<(!cast(IntID#"_128B") HvxVR:$src1, HvxVR:$src2, + HvxVR:$src3, imm:$src4), + (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>; } multiclass T_WVVI_HVX_gen_pat { - def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, imm:$src4), - (MI VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, imm:$src4)>, - Requires<[UseHVXSgl]>; - def: Pat<(!cast(IntID#"_128B") VecDblRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3, imm:$src4), - (!cast(MI#"_128B") VecDblRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3, imm:$src4)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4), + (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>; + def: Pat<(!cast(IntID#"_128B") HvxWR:$src1, HvxVR:$src2, + HvxVR:$src3, imm:$src4), + (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>; } def : T_R_pat ; diff --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td index 804a547d5b33..f185c49b85d6 100644 --- a/llvm/lib/Target/Hexagon/HexagonPatterns.td +++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td @@ -18,14 +18,14 @@ def HiReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_hi)>; def IsOrAdd: PatFrag<(ops node:$Addr, node:$off), (or node:$Addr, node:$off), [{ return isOrEquivalentToAdd(N); }]>; -def Iss4_6 : PatLeaf<(i32 imm), [{ +def IsVecOff : PatLeaf<(i32 imm), [{ int32_t V = N->getSExtValue(); - return isShiftedInt<4,6>(V); -}]>; - -def Iss4_7 : PatLeaf<(i32 imm), [{ - int32_t V = N->getSExtValue(); - return isShiftedInt<4,7>(V); + int32_t VecSize = HRI->getSpillSize(Hexagon::HvxVRRegClass); + assert(isPowerOf2_32(VecSize)); + if ((uint32_t(V) & (uint32_t(VecSize)-1)) != 0) + return false; + int32_t L = Log2_32(VecSize); + return isInt<4>(V >> L); }]>; def IsPow2_32 : PatLeaf<(i32 imm), [{ @@ -2776,190 +2776,94 @@ def unalignedstore : PatFrag<(ops node:$val, node:$addr), (store $val, $addr), [ multiclass vS32b_ai_pats { // Aligned stores - def : Pat<(alignednontemporalstore (VTSgl VectorRegs:$src1), IntRegs:$addr), - (V6_vS32b_nt_ai IntRegs:$addr, 0, (VTSgl VectorRegs:$src1))>, - Requires<[UseHVXSgl]>; - def : Pat<(alignedstore (VTSgl VectorRegs:$src1), IntRegs:$addr), - (V6_vS32b_ai IntRegs:$addr, 0, (VTSgl VectorRegs:$src1))>, - Requires<[UseHVXSgl]>; - def : Pat<(unalignedstore (VTSgl VectorRegs:$src1), IntRegs:$addr), - (V6_vS32Ub_ai IntRegs:$addr, 0, (VTSgl VectorRegs:$src1))>, - Requires<[UseHVXSgl]>; - - // 128B Aligned stores - def : Pat<(alignednontemporalstore (VTDbl VectorRegs128B:$src1), IntRegs:$addr), - (V6_vS32b_nt_ai_128B IntRegs:$addr, 0, (VTDbl VectorRegs128B:$src1))>, - Requires<[UseHVXDbl]>; - def : Pat<(alignedstore (VTDbl VectorRegs128B:$src1), IntRegs:$addr), - (V6_vS32b_ai_128B IntRegs:$addr, 0, (VTDbl VectorRegs128B:$src1))>, - Requires<[UseHVXDbl]>; - def : Pat<(unalignedstore (VTDbl VectorRegs128B:$src1), IntRegs:$addr), - (V6_vS32Ub_ai_128B IntRegs:$addr, 0, (VTDbl VectorRegs128B:$src1))>, - Requires<[UseHVXDbl]>; + def : Pat<(alignednontemporalstore (VTSgl HvxVR:$src1), IntRegs:$addr), + (V6_vS32b_nt_ai IntRegs:$addr, 0, (VTSgl HvxVR:$src1))>; + def : Pat<(alignedstore (VTSgl HvxVR:$src1), IntRegs:$addr), + (V6_vS32b_ai IntRegs:$addr, 0, (VTSgl HvxVR:$src1))>; + def : Pat<(unalignedstore (VTSgl HvxVR:$src1), IntRegs:$addr), + (V6_vS32Ub_ai IntRegs:$addr, 0, (VTSgl HvxVR:$src1))>; // Fold Add R+OFF into vector store. let AddedComplexity = 10 in { - def : Pat<(alignednontemporalstore (VTSgl VectorRegs:$src1), - (add IntRegs:$src2, Iss4_6:$offset)), - (V6_vS32b_nt_ai IntRegs:$src2, Iss4_6:$offset, - (VTSgl VectorRegs:$src1))>, - Requires<[UseHVXSgl]>; - def : Pat<(alignedstore (VTSgl VectorRegs:$src1), - (add IntRegs:$src2, Iss4_6:$offset)), - (V6_vS32b_ai IntRegs:$src2, Iss4_6:$offset, - (VTSgl VectorRegs:$src1))>, - Requires<[UseHVXSgl]>; - def : Pat<(unalignedstore (VTSgl VectorRegs:$src1), - (add IntRegs:$src2, Iss4_6:$offset)), - (V6_vS32Ub_ai IntRegs:$src2, Iss4_6:$offset, - (VTSgl VectorRegs:$src1))>, - Requires<[UseHVXSgl]>; - - // Fold Add R+OFF into vector store 128B. - def : Pat<(alignednontemporalstore (VTDbl VectorRegs128B:$src1), - (add IntRegs:$src2, Iss4_7:$offset)), - (V6_vS32b_nt_ai_128B IntRegs:$src2, Iss4_7:$offset, - (VTDbl VectorRegs128B:$src1))>, - Requires<[UseHVXDbl]>; - def : Pat<(alignedstore (VTDbl VectorRegs128B:$src1), - (add IntRegs:$src2, Iss4_7:$offset)), - (V6_vS32b_ai_128B IntRegs:$src2, Iss4_7:$offset, - (VTDbl VectorRegs128B:$src1))>, - Requires<[UseHVXDbl]>; - def : Pat<(unalignedstore (VTDbl VectorRegs128B:$src1), - (add IntRegs:$src2, Iss4_7:$offset)), - (V6_vS32Ub_ai_128B IntRegs:$src2, Iss4_7:$offset, - (VTDbl VectorRegs128B:$src1))>, - Requires<[UseHVXDbl]>; + def : Pat<(alignednontemporalstore (VTSgl HvxVR:$src1), + (add IntRegs:$src2, IsVecOff:$offset)), + (V6_vS32b_nt_ai IntRegs:$src2, imm:$offset, + (VTSgl HvxVR:$src1))>; + def : Pat<(alignedstore (VTSgl HvxVR:$src1), + (add IntRegs:$src2, IsVecOff:$offset)), + (V6_vS32b_ai IntRegs:$src2, imm:$offset, + (VTSgl HvxVR:$src1))>; + def : Pat<(unalignedstore (VTSgl HvxVR:$src1), + (add IntRegs:$src2, IsVecOff:$offset)), + (V6_vS32Ub_ai IntRegs:$src2, imm:$offset, + (VTSgl HvxVR:$src1))>; } } -defm : vS32b_ai_pats ; -defm : vS32b_ai_pats ; -defm : vS32b_ai_pats ; -defm : vS32b_ai_pats ; +defm : vS32b_ai_pats ; +defm : vS32b_ai_pats ; +defm : vS32b_ai_pats ; +defm : vS32b_ai_pats ; multiclass vL32b_ai_pats { // Aligned loads def : Pat < (VTSgl (alignednontemporalload IntRegs:$addr)), - (V6_vL32b_nt_ai IntRegs:$addr, 0) >, - Requires<[UseHVXSgl]>; + (V6_vL32b_nt_ai IntRegs:$addr, 0) >; def : Pat < (VTSgl (alignedload IntRegs:$addr)), - (V6_vL32b_ai IntRegs:$addr, 0) >, - Requires<[UseHVXSgl]>; + (V6_vL32b_ai IntRegs:$addr, 0) >; def : Pat < (VTSgl (unalignedload IntRegs:$addr)), - (V6_vL32Ub_ai IntRegs:$addr, 0) >, - Requires<[UseHVXSgl]>; - - // 128B Load - def : Pat < (VTDbl (alignednontemporalload IntRegs:$addr)), - (V6_vL32b_nt_ai_128B IntRegs:$addr, 0) >, - Requires<[UseHVXDbl]>; - def : Pat < (VTDbl (alignedload IntRegs:$addr)), - (V6_vL32b_ai_128B IntRegs:$addr, 0) >, - Requires<[UseHVXDbl]>; - def : Pat < (VTDbl (unalignedload IntRegs:$addr)), - (V6_vL32Ub_ai_128B IntRegs:$addr, 0) >, - Requires<[UseHVXDbl]>; + (V6_vL32Ub_ai IntRegs:$addr, 0) >; // Fold Add R+OFF into vector load. let AddedComplexity = 10 in { - def : Pat<(VTDbl (alignednontemporalload (add IntRegs:$src2, Iss4_7:$offset))), - (V6_vL32b_nt_ai_128B IntRegs:$src2, Iss4_7:$offset)>, - Requires<[UseHVXDbl]>; - def : Pat<(VTDbl (alignedload (add IntRegs:$src2, Iss4_7:$offset))), - (V6_vL32b_ai_128B IntRegs:$src2, Iss4_7:$offset)>, - Requires<[UseHVXDbl]>; - def : Pat<(VTDbl (unalignedload (add IntRegs:$src2, Iss4_7:$offset))), - (V6_vL32Ub_ai_128B IntRegs:$src2, Iss4_7:$offset)>, - Requires<[UseHVXDbl]>; - - def : Pat<(VTSgl (alignednontemporalload (add IntRegs:$src2, Iss4_6:$offset))), - (V6_vL32b_nt_ai IntRegs:$src2, Iss4_6:$offset)>, - Requires<[UseHVXSgl]>; - def : Pat<(VTSgl (alignedload (add IntRegs:$src2, Iss4_6:$offset))), - (V6_vL32b_ai IntRegs:$src2, Iss4_6:$offset)>, - Requires<[UseHVXSgl]>; - def : Pat<(VTSgl (unalignedload (add IntRegs:$src2, Iss4_6:$offset))), - (V6_vL32Ub_ai IntRegs:$src2, Iss4_6:$offset)>, - Requires<[UseHVXSgl]>; + def : Pat<(VTSgl (alignednontemporalload (add IntRegs:$src2, IsVecOff:$offset))), + (V6_vL32b_nt_ai IntRegs:$src2, imm:$offset)>; + def : Pat<(VTSgl (alignedload (add IntRegs:$src2, IsVecOff:$offset))), + (V6_vL32b_ai IntRegs:$src2, imm:$offset)>; + def : Pat<(VTSgl (unalignedload (add IntRegs:$src2, IsVecOff:$offset))), + (V6_vL32Ub_ai IntRegs:$src2, imm:$offset)>; } } -defm : vL32b_ai_pats ; -defm : vL32b_ai_pats ; -defm : vL32b_ai_pats ; -defm : vL32b_ai_pats ; +defm : vL32b_ai_pats ; +defm : vL32b_ai_pats ; +defm : vL32b_ai_pats ; +defm : vL32b_ai_pats ; multiclass STrivv_pats { - def : Pat<(alignednontemporalstore (VTSgl VecDblRegs:$src1), IntRegs:$addr), - (PS_vstorerw_nt_ai IntRegs:$addr, 0, (VTSgl VecDblRegs:$src1))>, - Requires<[UseHVXSgl]>; - def : Pat<(alignedstore (VTSgl VecDblRegs:$src1), IntRegs:$addr), - (PS_vstorerw_ai IntRegs:$addr, 0, (VTSgl VecDblRegs:$src1))>, - Requires<[UseHVXSgl]>; - def : Pat<(unalignedstore (VTSgl VecDblRegs:$src1), IntRegs:$addr), - (PS_vstorerwu_ai IntRegs:$addr, 0, (VTSgl VecDblRegs:$src1))>, - Requires<[UseHVXSgl]>; - - def : Pat<(alignednontemporalstore (VTDbl VecDblRegs128B:$src1), IntRegs:$addr), - (PS_vstorerw_nt_ai_128B IntRegs:$addr, 0, - (VTDbl VecDblRegs128B:$src1))>, - Requires<[UseHVXDbl]>; - def : Pat<(alignedstore (VTDbl VecDblRegs128B:$src1), IntRegs:$addr), - (PS_vstorerw_ai_128B IntRegs:$addr, 0, - (VTDbl VecDblRegs128B:$src1))>, - Requires<[UseHVXDbl]>; - def : Pat<(unalignedstore (VTDbl VecDblRegs128B:$src1), IntRegs:$addr), - (PS_vstorerwu_ai_128B IntRegs:$addr, 0, - (VTDbl VecDblRegs128B:$src1))>, - Requires<[UseHVXDbl]>; + def : Pat<(alignednontemporalstore (VTSgl HvxWR:$src1), IntRegs:$addr), + (PS_vstorerw_nt_ai IntRegs:$addr, 0, (VTSgl HvxWR:$src1))>; + def : Pat<(alignedstore (VTSgl HvxWR:$src1), IntRegs:$addr), + (PS_vstorerw_ai IntRegs:$addr, 0, (VTSgl HvxWR:$src1))>; + def : Pat<(unalignedstore (VTSgl HvxWR:$src1), IntRegs:$addr), + (PS_vstorerwu_ai IntRegs:$addr, 0, (VTSgl HvxWR:$src1))>; } -defm : STrivv_pats ; -defm : STrivv_pats ; -defm : STrivv_pats ; -defm : STrivv_pats ; +defm : STrivv_pats ; +defm : STrivv_pats ; +defm : STrivv_pats ; +defm : STrivv_pats ; multiclass LDrivv_pats { def : Pat<(VTSgl (alignednontemporalload I32:$addr)), - (PS_vloadrw_nt_ai I32:$addr, 0)>, - Requires<[UseHVXSgl]>; + (PS_vloadrw_nt_ai I32:$addr, 0)>; def : Pat<(VTSgl (alignedload I32:$addr)), - (PS_vloadrw_ai I32:$addr, 0)>, - Requires<[UseHVXSgl]>; + (PS_vloadrw_ai I32:$addr, 0)>; def : Pat<(VTSgl (unalignedload I32:$addr)), - (PS_vloadrwu_ai I32:$addr, 0)>, - Requires<[UseHVXSgl]>; - - def : Pat<(VTDbl (alignednontemporalload I32:$addr)), - (PS_vloadrw_nt_ai_128B I32:$addr, 0)>, - Requires<[UseHVXDbl]>; - def : Pat<(VTDbl (alignedload I32:$addr)), - (PS_vloadrw_ai_128B I32:$addr, 0)>, - Requires<[UseHVXDbl]>; - def : Pat<(VTDbl (unalignedload I32:$addr)), - (PS_vloadrwu_ai_128B I32:$addr, 0)>, - Requires<[UseHVXDbl]>; + (PS_vloadrwu_ai I32:$addr, 0)>; } -defm : LDrivv_pats ; -defm : LDrivv_pats ; -defm : LDrivv_pats ; -defm : LDrivv_pats ; +defm : LDrivv_pats ; +defm : LDrivv_pats ; +defm : LDrivv_pats ; +defm : LDrivv_pats ; -let Predicates = [HasV60T,UseHVXSgl] in { - def: Pat<(select I1:$Pu, (v16i32 VectorRegs:$Vs), VectorRegs:$Vt), - (PS_vselect I1:$Pu, VectorRegs:$Vs, VectorRegs:$Vt)>; - def: Pat<(select I1:$Pu, (v32i32 VecDblRegs:$Vs), VecDblRegs:$Vt), - (PS_wselect I1:$Pu, VecDblRegs:$Vs, VecDblRegs:$Vt)>; -} -let Predicates = [HasV60T,UseHVXDbl] in { - def: Pat<(select I1:$Pu, (v32i32 VectorRegs128B:$Vs), VectorRegs128B:$Vt), - (PS_vselect_128B I1:$Pu, VectorRegs128B:$Vs, VectorRegs128B:$Vt)>; - def: Pat<(select I1:$Pu, (v64i32 VecDblRegs128B:$Vs), VecDblRegs128B:$Vt), - (PS_wselect_128B I1:$Pu, VecDblRegs128B:$Vs, VecDblRegs128B:$Vt)>; +let Predicates = [HasV60T] in { + def: Pat<(select I1:$Pu, (VecI32 HvxVR:$Vs), HvxVR:$Vt), + (PS_vselect I1:$Pu, HvxVR:$Vs, HvxVR:$Vt)>; + def: Pat<(select I1:$Pu, (VecPI32 HvxWR:$Vs), HvxWR:$Vt), + (PS_wselect I1:$Pu, HvxWR:$Vs, HvxWR:$Vt)>; } @@ -2968,49 +2872,22 @@ def SDTHexagonVCOMBINE: SDTypeProfile<1, 2, [SDTCisSameAs<1, 2>, def HexagonVCOMBINE: SDNode<"HexagonISD::VCOMBINE", SDTHexagonVCOMBINE>; -def: Pat<(v32i32 (HexagonVCOMBINE (v16i32 VectorRegs:$Vs), - (v16i32 VectorRegs:$Vt))), - (V6_vcombine VectorRegs:$Vs, VectorRegs:$Vt)>, - Requires<[UseHVXSgl]>; -def: Pat<(v64i32 (HexagonVCOMBINE (v32i32 VecDblRegs:$Vs), - (v32i32 VecDblRegs:$Vt))), - (V6_vcombine_128B VecDblRegs:$Vs, VecDblRegs:$Vt)>, - Requires<[UseHVXDbl]>; +def: Pat<(VecPI32 (HexagonVCOMBINE (VecI32 HvxVR:$Vs), (VecI32 HvxVR:$Vt))), + (V6_vcombine HvxVR:$Vs, HvxVR:$Vt)>; def SDTHexagonVPACK: SDTypeProfile<1, 2, [SDTCisSameAs<1, 2>, SDTCisVec<1>]>; def HexagonVPACKE: SDNode<"HexagonISD::VPACKE", SDTHexagonVPACK>; def HexagonVPACKO: SDNode<"HexagonISD::VPACKO", SDTHexagonVPACK>; -let Predicates = [UseHVXSgl] in { - def: Pat<(v64i8 (HexagonVPACKE (v64i8 VectorRegs:$Vs), - (v64i8 VectorRegs:$Vt))), - (V6_vpackeb VectorRegs:$Vs, VectorRegs:$Vt)>; - def: Pat<(v64i8 (HexagonVPACKO (v64i8 VectorRegs:$Vs), - (v64i8 VectorRegs:$Vt))), - (V6_vpackob VectorRegs:$Vs, VectorRegs:$Vt)>; - def: Pat<(v32i16 (HexagonVPACKE (v32i16 VectorRegs:$Vs), - (v32i16 VectorRegs:$Vt))), - (V6_vpackeh VectorRegs:$Vs, VectorRegs:$Vt)>; - def: Pat<(v32i16 (HexagonVPACKO (v32i16 VectorRegs:$Vs), - (v32i16 VectorRegs:$Vt))), - (V6_vpackoh VectorRegs:$Vs, VectorRegs:$Vt)>; -} - -let Predicates = [UseHVXDbl] in { - def: Pat<(v128i8 (HexagonVPACKE (v128i8 VecDblRegs:$Vs), - (v128i8 VecDblRegs:$Vt))), - (V6_vpackeb_128B VecDblRegs:$Vs, VecDblRegs:$Vt)>; - def: Pat<(v128i8 (HexagonVPACKO (v128i8 VecDblRegs:$Vs), - (v128i8 VecDblRegs:$Vt))), - (V6_vpackob_128B VecDblRegs:$Vs, VecDblRegs:$Vt)>; - def: Pat<(v64i16 (HexagonVPACKE (v64i16 VecDblRegs:$Vs), - (v64i16 VecDblRegs:$Vt))), - (V6_vpackeh_128B VecDblRegs:$Vs, VecDblRegs:$Vt)>; - def: Pat<(v64i16 (HexagonVPACKO (v64i16 VecDblRegs:$Vs), - (v64i16 VecDblRegs:$Vt))), - (V6_vpackoh_128B VecDblRegs:$Vs, VecDblRegs:$Vt)>; -} +def: Pat<(VecI8 (HexagonVPACKE (VecI8 HvxVR:$Vs), (VecI8 HvxVR:$Vt))), + (V6_vpackeb HvxVR:$Vs, HvxVR:$Vt)>; +def: Pat<(VecI8 (HexagonVPACKO (VecI8 HvxVR:$Vs), (VecI8 HvxVR:$Vt))), + (V6_vpackob HvxVR:$Vs, HvxVR:$Vt)>; +def: Pat<(VecI16 (HexagonVPACKE (VecI16 HvxVR:$Vs), (VecI16 HvxVR:$Vt))), + (V6_vpackeh HvxVR:$Vs, HvxVR:$Vt)>; +def: Pat<(VecI16 (HexagonVPACKO (VecI16 HvxVR:$Vs), (VecI16 HvxVR:$Vt))), + (V6_vpackoh HvxVR:$Vs, HvxVR:$Vt)>; def V2I1: PatLeaf<(v2i1 PredRegs:$R)>; def V4I1: PatLeaf<(v4i1 PredRegs:$R)>; diff --git a/llvm/lib/Target/Hexagon/HexagonPseudo.td b/llvm/lib/Target/Hexagon/HexagonPseudo.td index 16e950361317..094e0fbcac81 100644 --- a/llvm/lib/Target/Hexagon/HexagonPseudo.td +++ b/llvm/lib/Target/Hexagon/HexagonPseudo.td @@ -295,7 +295,7 @@ let isTerminator = 1, hasSideEffects = 0, isReturn = 1, isCodeGenOnly = 1, def PS_jmpretfnewpt : T_JMPr_c<1, 1, 1, J2_jumprfnewpt>, PredNewRel; } -//defm V6_vtran2x2_map : HexagonMapping<(outs VectorRegs:$Vy32, VectorRegs:$Vx32), (ins VectorRegs:$Vx32in, IntRegs:$Rt32), "vtrans2x2(${Vy32},${Vx32},${Rt32})", (V6_vshuff VectorRegs:$Vy32, VectorRegs:$Vx32, VectorRegs:$Vx32in, IntRegs:$Rt32)>; +//defm V6_vtran2x2_map : HexagonMapping<(outs HvxVR:$Vy32, HvxVR:$Vx32), (ins HvxVR:$Vx32in, IntRegs:$Rt32), "vtrans2x2(${Vy32},${Vx32},${Rt32})", (V6_vshuff HvxVR:$Vy32, HvxVR:$Vx32, HvxVR:$Vx32in, IntRegs:$Rt32)>; // The reason for the custom inserter is to record all ALLOCA instructions // in MachineFunctionInfo. @@ -397,84 +397,53 @@ let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in { // Vector store pseudos let Predicates = [HasV60T, UseHVX], isPseudo = 1, isCodeGenOnly = 1, - mayStore = 1, hasSideEffects = 0 in + mayStore = 1, accessSize = HVXVectorAccess, hasSideEffects = 0 in class STrivv_template : InstHexagon<(outs), (ins IntRegs:$addr, s32_0Imm:$off, RC:$src), "", [], "", rootInst.Itinerary, rootInst.Type>; -let accessSize = Vector64Access, Predicates = [HasV60T,UseHVXSgl] in { - def PS_vstorerw_ai: STrivv_template; - def PS_vstorerw_nt_ai: STrivv_template; - def PS_vstorerwu_ai: STrivv_template; -} +def PS_vstorerw_ai: STrivv_template, + Requires<[HasV60T,UseHVX]>; +def PS_vstorerw_nt_ai: STrivv_template, + Requires<[HasV60T,UseHVX]>; +def PS_vstorerwu_ai: STrivv_template, + Requires<[HasV60T,UseHVX]>; -let accessSize = Vector128Access, Predicates = [HasV60T,UseHVXDbl] in { - def PS_vstorerw_ai_128B: STrivv_template; - def PS_vstorerw_nt_ai_128B: STrivv_template; - def PS_vstorerwu_ai_128B: STrivv_template; -} - -let isPseudo = 1, isCodeGenOnly = 1, mayStore = 1, hasSideEffects = 0 in { - let accessSize = Vector64Access in - def PS_vstorerq_ai: Pseudo<(outs), - (ins IntRegs:$Rs, s32_0Imm:$Off, VecPredRegs:$Qt), "", []>, - Requires<[HasV60T,UseHVXSgl]>; - let accessSize = Vector128Access in - def PS_vstorerq_ai_128B: Pseudo<(outs), - (ins IntRegs:$Rs, s32_0Imm:$Off, VecPredRegs128B:$Qt), "", []>, - Requires<[HasV60T,UseHVXDbl]>; -} +let isPseudo = 1, isCodeGenOnly = 1, mayStore = 1, hasSideEffects = 0 in +def PS_vstorerq_ai: Pseudo<(outs), + (ins IntRegs:$Rs, s32_0Imm:$Off, HvxQR:$Qt), "", []>, + Requires<[HasV60T,UseHVX]>; // Vector load pseudos let Predicates = [HasV60T, UseHVX], isPseudo = 1, isCodeGenOnly = 1, - mayLoad = 1, hasSideEffects = 0 in + mayLoad = 1, accessSize = HVXVectorAccess, hasSideEffects = 0 in class LDrivv_template : InstHexagon<(outs RC:$dst), (ins IntRegs:$addr, s32_0Imm:$off), "", [], "", rootInst.Itinerary, rootInst.Type>; -let accessSize = Vector64Access, Predicates = [HasV60T,UseHVXSgl] in { - def PS_vloadrw_ai: LDrivv_template; - def PS_vloadrw_nt_ai: LDrivv_template; - def PS_vloadrwu_ai: LDrivv_template; -} +def PS_vloadrw_ai: LDrivv_template, + Requires<[HasV60T,UseHVX]>; +def PS_vloadrw_nt_ai: LDrivv_template, + Requires<[HasV60T,UseHVXSgl]>; +def PS_vloadrwu_ai: LDrivv_template, + Requires<[HasV60T,UseHVX]>; -let accessSize = Vector128Access, Predicates = [HasV60T,UseHVXDbl] in { - def PS_vloadrw_ai_128B: LDrivv_template; - def PS_vloadrw_nt_ai_128B: LDrivv_template; - def PS_vloadrwu_ai_128B: LDrivv_template; -} - -let isPseudo = 1, isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in { - let accessSize = Vector64Access in - def PS_vloadrq_ai: Pseudo<(outs VecPredRegs:$Qd), - (ins IntRegs:$Rs, s32_0Imm:$Off), "", []>, - Requires<[HasV60T,UseHVXSgl]>; - let accessSize = Vector128Access in - def PS_vloadrq_ai_128B: Pseudo<(outs VecPredRegs128B:$Qd), - (ins IntRegs:$Rs, s32_0Imm:$Off), "", []>, - Requires<[HasV60T,UseHVXDbl]>; -} +let isPseudo = 1, isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in +def PS_vloadrq_ai: Pseudo<(outs HvxQR:$Qd), + (ins IntRegs:$Rs, s32_0Imm:$Off), "", []>, + Requires<[HasV60T,UseHVX]>; let isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in class VSELInst : InstHexagon; -def PS_vselect: VSELInst<(outs VectorRegs:$dst), - (ins PredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3), - V6_vcmov>, Requires<[HasV60T,UseHVXSgl]>; -def PS_vselect_128B: VSELInst<(outs VectorRegs128B:$dst), - (ins PredRegs:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3), - V6_vcmov>, Requires<[HasV60T,UseHVXDbl]>; - -def PS_wselect: VSELInst<(outs VecDblRegs:$dst), - (ins PredRegs:$src1, VecDblRegs:$src2, VecDblRegs:$src3), - V6_vccombine>, Requires<[HasV60T,UseHVXSgl]>; -def PS_wselect_128B: VSELInst<(outs VecDblRegs128B:$dst), - (ins PredRegs:$src1, VecDblRegs128B:$src2, VecDblRegs128B:$src3), - V6_vccombine>, Requires<[HasV60T,UseHVXDbl]>; +def PS_vselect: VSELInst<(outs HvxVR:$dst), + (ins PredRegs:$src1, HvxVR:$src2, HvxVR:$src3), V6_vcmov>, + Requires<[HasV60T,UseHVX]>; +def PS_wselect: VSELInst<(outs HvxWR:$dst), + (ins PredRegs:$src1, HvxWR:$src2, HvxWR:$src3), V6_vccombine>, + Requires<[HasV60T,UseHVX]>; // Store predicate. let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13, diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp index 1fc157900ed5..cc85a995d402 100644 --- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp @@ -41,8 +41,9 @@ using namespace llvm; -HexagonRegisterInfo::HexagonRegisterInfo() - : HexagonGenRegisterInfo(Hexagon::R31) {} +HexagonRegisterInfo::HexagonRegisterInfo(unsigned HwMode) + : HexagonGenRegisterInfo(Hexagon::R31, 0/*DwarfFlavor*/, 0/*EHFlavor*/, + 0/*PC*/, HwMode) {} bool HexagonRegisterInfo::isEHReturnCalleeSaveReg(unsigned R) const { @@ -80,11 +81,9 @@ HexagonRegisterInfo::getCallerSavedRegs(const MachineFunction *MF, return Int64; case PredRegsRegClassID: return Pred; - case VectorRegsRegClassID: - case VectorRegs128BRegClassID: + case HvxVRRegClassID: return VecSgl; - case VecDblRegsRegClassID: - case VecDblRegs128BRegClassID: + case HvxWRRegClassID: return VecDbl; default: break; @@ -213,7 +212,7 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, break; } - if (!HII.isValidOffset(Opc, RealOffset)) { + if (!HII.isValidOffset(Opc, RealOffset, this)) { // If the offset is not valid, calculate the address in a temporary // register and use it with offset 0. auto &MRI = MF.getRegInfo(); @@ -267,8 +266,7 @@ unsigned HexagonRegisterInfo::getHexagonSubRegIndex( case Hexagon::CtrRegs64RegClassID: case Hexagon::DoubleRegsRegClassID: return ISub[GenIdx]; - case Hexagon::VecDblRegsRegClassID: - case Hexagon::VecDblRegs128BRegClassID: + case Hexagon::HvxWRRegClassID: return VSub[GenIdx]; } diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h index d23609ac93d2..02a107bd90eb 100644 --- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h @@ -29,7 +29,7 @@ namespace Hexagon { class HexagonRegisterInfo : public HexagonGenRegisterInfo { public: - HexagonRegisterInfo(); + HexagonRegisterInfo(unsigned HwMode); /// Code Generation virtual methods... const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td index 45dbb3a6d218..b2e952a76122 100644 --- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td @@ -164,7 +164,6 @@ let Namespace = "Hexagon" in { def PKTCOUNTHI: Rc<19, "pktcounthi", ["c19"]>, DwarfRegNum<[86]>; def UTIMERLO: Rc<30, "utimerlo", ["c30"]>, DwarfRegNum<[97]>; def UTIMERHI: Rc<31, "utimerhi", ["c31"]>, DwarfRegNum<[98]>; -} // Control registers pairs. let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in { @@ -213,6 +212,29 @@ let Namespace = "Hexagon" in { def Q1 : Rq<1, "q1">, DwarfRegNum<[132]>; def Q2 : Rq<2, "q2">, DwarfRegNum<[133]>; def Q3 : Rq<3, "q3">, DwarfRegNum<[134]>; +} + +// HVX types + +def VecI1 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], + [v512i1, v1024i1, v512i1]>; +def VecI8 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], + [v64i8, v128i8, v64i8]>; +def VecI16 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], + [v32i16, v64i16, v32i16]>; +def VecI32 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], + [v16i32, v32i32, v16i32]>; +def VecI64 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], + [v8i64, v16i64, v8i64]>; +def VecPI8 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], + [v128i8, v256i8, v128i8]>; +def VecPI16 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], + [v64i16, v128i16, v64i16]>; +def VecPI32 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], + [v32i32, v64i32, v32i32]>; +def VecPI64 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], + [v16i64, v32i64, v16i64]>; + // Register classes. // @@ -220,55 +242,44 @@ let Namespace = "Hexagon" in { // allocation order... // def IntRegs : RegisterClass<"Hexagon", [i32, f32, v4i8, v2i16], 32, - (add (sequence "R%u", 0, 9), - (sequence "R%u", 12, 28), - R10, R11, R29, R30, R31)> { -} + (add (sequence "R%u", 0, 9), (sequence "R%u", 12, 28), + R10, R11, R29, R30, R31)>; // Registers are listed in reverse order for allocation preference reasons. def GeneralSubRegs : RegisterClass<"Hexagon", [i32], 32, - (add R23, R22, R21, R20, R19, R18, R17, - R16, R7, R6, R5, R4, R3, R2, R1, R0)>; + (add R23, R22, R21, R20, R19, R18, R17, R16, + R7, R6, R5, R4, R3, R2, R1, R0)>; def IntRegsLow8 : RegisterClass<"Hexagon", [i32], 32, - (add R7, R6, R5, R4, R3, R2, R1, R0)> ; + (add R7, R6, R5, R4, R3, R2, R1, R0)> ; def DoubleRegs : RegisterClass<"Hexagon", [i64, f64, v8i8, v4i16, v2i32], 64, - (add (sequence "D%u", 0, 4), - (sequence "D%u", 6, 13), D5, D14, D15)>; + (add (sequence "D%u", 0, 4), (sequence "D%u", 6, 13), D5, D14, D15)>; def GeneralDoubleLow8Regs : RegisterClass<"Hexagon", [i64], 64, - (add D11, D10, D9, D8, D3, D2, D1, - D0)>; + (add D11, D10, D9, D8, D3, D2, D1, D0)>; -def VectorRegs : RegisterClass<"Hexagon", [v64i8, v32i16, v16i32, v8i64], 512, - (add (sequence "V%u", 0, 31))>; - -def VecDblRegs : RegisterClass<"Hexagon", - [v128i8, v64i16, v32i32, v16i64], 1024, - (add (sequence "W%u", 0, 15))>; - -def VectorRegs128B : RegisterClass<"Hexagon", - [v128i8, v64i16, v32i32, v16i64], 1024, - (add (sequence "V%u", 0, 31))>; - -def VecDblRegs128B : RegisterClass<"Hexagon", - [v256i8,v128i16,v64i32,v32i64], 2048, - (add (sequence "W%u", 0, 15))>; - -def VecPredRegs : RegisterClass<"Hexagon", [v512i1], 512, - (add (sequence "Q%u", 0, 3))>; - -def VecPredRegs128B : RegisterClass<"Hexagon", [v1024i1], 1024, - (add (sequence "Q%u", 0, 3))>; - -def PredRegs : RegisterClass<"Hexagon", - [i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32, - (add (sequence "P%u", 0, 3))> -{ - let Size = 32; +def HvxVR : RegisterClass<"Hexagon", [VecI8, VecI16, VecI32, VecI64], 512, + (add (sequence "V%u", 0, 31))> { + let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode], + [RegInfo<512,512,512>, RegInfo<1024,1024,1024>, RegInfo<512,512,512>]>; } +def HvxWR : RegisterClass<"Hexagon", [VecPI8, VecPI16, VecPI32, VecPI64], 1024, + (add (sequence "W%u", 0, 15))> { + let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode], + [RegInfo<1024,1024,1024>, RegInfo<2048,2048,2048>, RegInfo<1024,1024,1024>]>; +} + +def HvxQR : RegisterClass<"Hexagon", [VecI1], 512, (add Q0, Q1, Q2, Q3)> { + let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode], + [RegInfo<512,512,512>, RegInfo<1024,1024,1024>, RegInfo<512,512,512>]>; +} + +let Size = 32 in +def PredRegs : RegisterClass<"Hexagon", + [i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32, (add P0, P1, P2, P3)>; + let Size = 32 in def ModRegs : RegisterClass<"Hexagon", [i32], 32, (add M0, M1)>; @@ -291,9 +302,8 @@ def CtrRegs64 : RegisterClass<"Hexagon", [i64], 64, // The function RegisterMatchesArch() uses this list for validation. let isAllocatable = 0 in def V62Regs : RegisterClass<"Hexagon", [i32], 32, - (add FRAMELIMIT, FRAMEKEY, C17_16, - PKTCOUNTLO, PKTCOUNTHI, PKTCOUNT, - UTIMERLO, UTIMERHI, UTIMER)>; + (add FRAMELIMIT, FRAMEKEY, C17_16, PKTCOUNTLO, PKTCOUNTHI, PKTCOUNT, + UTIMERLO, UTIMERHI, UTIMER)>; def HexagonCSR diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp index 5803886f8b0a..d99799ecff9d 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp @@ -301,7 +301,8 @@ void HexagonSubtarget::BankConflictMutation::apply(ScheduleDAGInstrs *DAG) { HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM) : HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU), - InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this) { + InstrInfo(initializeSubtargetDependencies(CPU, FS)), + RegInfo(getHwMode()), TLInfo(TM, *this) { initializeEnvironment(); // Initialize scheduling itinerary for the specified CPU. diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.h b/llvm/lib/Target/Hexagon/HexagonSubtarget.h index bdaf12e17d97..ccb16d2564ed 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.h +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.h @@ -17,6 +17,7 @@ #include "HexagonFrameLowering.h" #include "HexagonInstrInfo.h" #include "HexagonISelLowering.h" +#include "HexagonRegisterInfo.h" #include "HexagonSelectionDAGInfo.h" #include "llvm/ADT/SmallSet.h" #include "llvm/ADT/StringRef.h" @@ -75,6 +76,7 @@ public: private: std::string CPUString; HexagonInstrInfo InstrInfo; + HexagonRegisterInfo RegInfo; HexagonTargetLowering TLInfo; HexagonSelectionDAGInfo TSInfo; HexagonFrameLowering FrameLowering; @@ -93,7 +95,7 @@ public: } const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; } const HexagonRegisterInfo *getRegisterInfo() const override { - return &InstrInfo.getRegisterInfo(); + return &RegInfo; } const HexagonTargetLowering *getTargetLowering() const override { return &TLInfo; diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index 9b4530f22973..a6df6afae787 100644 --- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -453,7 +453,7 @@ bool HexagonPacketizerList::useCallersSP(MachineInstr &MI) { unsigned FrameSize = MF.getFrameInfo().getStackSize(); MachineOperand &Off = MI.getOperand(1); int64_t NewOff = Off.getImm() - (FrameSize + HEXAGON_LRFP_SIZE); - if (HII->isValidOffset(Opc, NewOff)) { + if (HII->isValidOffset(Opc, NewOff, HRI)) { Off.setImm(NewOff); return true; } @@ -801,7 +801,7 @@ bool HexagonPacketizerList::canPromoteToDotNew(const MachineInstr &MI, const MCInstrDesc& MCID = PI.getDesc(); const TargetRegisterClass *VecRC = HII->getRegClass(MCID, 0, HRI, MF); - if (DisableVecDblNVStores && VecRC == &Hexagon::VecDblRegsRegClass) + if (DisableVecDblNVStores && VecRC == &Hexagon::HvxWRRegClass) return false; // predicate .new diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h index 50cf12b109d2..d1a6d38797d7 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h @@ -51,8 +51,7 @@ namespace HexagonII { HalfWordAccess, WordAccess, DoubleWordAccess, - Vector64Access, - Vector128Access + HVXVectorAccess }; // MCInstrDesc TSFlags