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AMDGPU/GlobalISel: Mark 32-bit G_OR as legal 

Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D35127

llvm-svn: 309165
This commit is contained in:
Tom Stellard 2017-07-26 20:00:53 +00:00
parent 95b39da8ae
commit 55038cd1d3
2 changed files with 23 additions and 0 deletions
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2
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
View File

@ -66,6 +66,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo() {
setAction({G_LOAD, 1, P1}, Legal);
setAction({G_LOAD, 1, P2}, Legal);
setAction({G_OR, S32}, Legal);
setAction({G_SELECT, S32}, Legal);
setAction({G_SELECT, 1, S1}, Legal);

21
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir Normal file
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@ -0,0 +1,21 @@
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
define void @test_or() { ret void }
...
---
name: test_or
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.0:
liveins: %vgpr0, %vgpr1
; CHECK-LABEL: name: test_or
; CHECK: %2(s32) = G_OR %0, %1
%0(s32) = COPY %vgpr0
%1(s32) = COPY %vgpr1
%2(s32) = G_OR %0, %1
...