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[AMDGPU] Use v_fma_f16 on GFX10 

Teach convertToThreeAddress to use the V_FMA_F16_gfx9 pseudo (i.e. the
standard instruction in GFX9 onwards) instead of V_FMA_F16 (the legacy
pseudo for GFX8 compatibility, which is no longer supported in GFX10).
This follows the example of macToMad in SIFoldOperands.

Differential Revision: https://reviews.llvm.org/D115731
This commit is contained in:
Jay Foad 2021-12-14 15:47:44 +00:00
parent 4db7422771
commit 54fc9eb9b3
5 changed files with 14 additions and 21 deletions
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2
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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@ -3297,7 +3297,7 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
}
}
unsigned NewOpc = IsFMA ? (IsF16 ? AMDGPU::V_FMA_F16_e64
unsigned NewOpc = IsFMA ? (IsF16 ? AMDGPU::V_FMA_F16_gfx9_e64
: IsF64 ? AMDGPU::V_FMA_F64_e64
: AMDGPU::V_FMA_F32_e64)
: (IsF16 ? AMDGPU::V_MAD_F16_e64 : AMDGPU::V_MAD_F32_e64);

12
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
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@ -107,9 +107,9 @@ define half @test_half_add_mul(half %a, half %b, half %c, half %d, half %e) {
; GFX10-CONTRACT: ; %bb.0: ; %.entry
; GFX10-CONTRACT-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-CONTRACT-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-CONTRACT-NEXT: v_fmac_f16_e32 v4, v2, v3
; GFX10-CONTRACT-NEXT: v_fmac_f16_e32 v4, v0, v1
; GFX10-CONTRACT-NEXT: v_mov_b32_e32 v0, v4
; GFX10-CONTRACT-NEXT: v_fma_f16 v2, v2, v3, v4
; GFX10-CONTRACT-NEXT: v_fmac_f16_e32 v2, v0, v1
; GFX10-CONTRACT-NEXT: v_mov_b32_e32 v0, v2
; GFX10-CONTRACT-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-DENORM-LABEL: test_half_add_mul:
@ -148,9 +148,9 @@ define half @test_half_add_mul_rhs(half %a, half %b, half %c, half %d, half %e)
; GFX10-CONTRACT: ; %bb.0: ; %.entry
; GFX10-CONTRACT-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-CONTRACT-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-CONTRACT-NEXT: v_fmac_f16_e32 v4, v2, v3
; GFX10-CONTRACT-NEXT: v_fmac_f16_e32 v4, v0, v1
; GFX10-CONTRACT-NEXT: v_mov_b32_e32 v0, v4
; GFX10-CONTRACT-NEXT: v_fma_f16 v2, v2, v3, v4
; GFX10-CONTRACT-NEXT: v_fmac_f16_e32 v2, v0, v1
; GFX10-CONTRACT-NEXT: v_mov_b32_e32 v0, v2
; GFX10-CONTRACT-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-DENORM-LABEL: test_half_add_mul_rhs:

12
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll
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@ -166,8 +166,7 @@ define half @test_half_add_mul(half %x, half %y, half %z) {
; GFX10-CONTRACT: ; %bb.0: ; %.entry
; GFX10-CONTRACT-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-CONTRACT-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-CONTRACT-NEXT: v_fmac_f16_e32 v2, v0, v1
; GFX10-CONTRACT-NEXT: v_mov_b32_e32 v0, v2
; GFX10-CONTRACT-NEXT: v_fma_f16 v0, v0, v1, v2
; GFX10-CONTRACT-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-DENORM-LABEL: test_half_add_mul:
@ -182,8 +181,7 @@ define half @test_half_add_mul(half %x, half %y, half %z) {
; GFX10-UNSAFE: ; %bb.0: ; %.entry
; GFX10-UNSAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-UNSAFE-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-UNSAFE-NEXT: v_fmac_f16_e32 v2, v0, v1
; GFX10-UNSAFE-NEXT: v_mov_b32_e32 v0, v2
; GFX10-UNSAFE-NEXT: v_fma_f16 v0, v0, v1, v2
; GFX10-UNSAFE-NEXT: s_setpc_b64 s[30:31]
.entry:
%a = fmul half %x, %y
@ -229,8 +227,7 @@ define half @test_half_add_mul_rhs(half %x, half %y, half %z) {
; GFX10-CONTRACT: ; %bb.0: ; %.entry
; GFX10-CONTRACT-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-CONTRACT-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-CONTRACT-NEXT: v_fmac_f16_e32 v2, v0, v1
; GFX10-CONTRACT-NEXT: v_mov_b32_e32 v0, v2
; GFX10-CONTRACT-NEXT: v_fma_f16 v0, v0, v1, v2
; GFX10-CONTRACT-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-DENORM-LABEL: test_half_add_mul_rhs:
@ -245,8 +242,7 @@ define half @test_half_add_mul_rhs(half %x, half %y, half %z) {
; GFX10-UNSAFE: ; %bb.0: ; %.entry
; GFX10-UNSAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-UNSAFE-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-UNSAFE-NEXT: v_fmac_f16_e32 v2, v0, v1
; GFX10-UNSAFE-NEXT: v_mov_b32_e32 v0, v2
; GFX10-UNSAFE-NEXT: v_fma_f16 v0, v0, v1, v2
; GFX10-UNSAFE-NEXT: s_setpc_b64 s[30:31]
.entry:
%a = fmul half %x, %y

3
llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
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@ -93,8 +93,7 @@ define half @v_fma_f16(half %x, half %y, half %z) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_fmac_f16_e32 v2, v0, v1
; GFX10-NEXT: v_mov_b32_e32 v0, v2
; GFX10-NEXT: v_fma_f16 v0, v0, v1, v2
; GFX10-NEXT: s_setpc_b64 s[30:31]
%fma = call half @llvm.fma.f16(half %x, half %y, half %z)
ret half %fma

6
llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
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@ -14,8 +14,7 @@ define half @v_constained_fma_f16_fpexcept_strict(half %x, half %y, half %z) #0
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_fmac_f16_e32 v2, v0, v1
; GFX10-NEXT: v_mov_b32_e32 v0, v2
; GFX10-NEXT: v_fma_f16 v0, v0, v1, v2
; GFX10-NEXT: s_setpc_b64 s[30:31]
%val = call half @llvm.experimental.constrained.fma.f16(half %x, half %y, half %z, metadata !"round.tonearest", metadata !"fpexcept.strict")
ret half %val
@ -75,9 +74,8 @@ define <3 x half> @v_constained_fma_v3f16_fpexcept_strict(<3 x half> %x, <3 x ha
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_fmac_f16_e32 v5, v1, v3
; GFX10-NEXT: v_pk_fma_f16 v0, v0, v2, v4
; GFX10-NEXT: v_mov_b32_e32 v1, v5
; GFX10-NEXT: v_fma_f16 v1, v1, v3, v5
; GFX10-NEXT: s_setpc_b64 s[30:31]
%val = call <3 x half> @llvm.experimental.constrained.fma.v3f16(<3 x half> %x, <3 x half> %y, <3 x half> %z, metadata !"round.tonearest", metadata !"fpexcept.strict")
ret <3 x half> %val