forked from OSchip/llvm-project
ARM: v1i64 and v2i64 VBSL intrinsic support.
rdar://12502028 llvm-svn: 165981
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llvm
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@ -4504,12 +4504,21 @@ def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 DPR:$src1),
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(v2f32 DPR:$Vn), (v2f32 DPR:$Vm))),
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(VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
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Requires<[HasNEON]>;
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def : Pat<(v1i64 (int_arm_neon_vbsl (v1i64 DPR:$src1),
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(v1i64 DPR:$Vn), (v1i64 DPR:$Vm))),
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(VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
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Requires<[HasNEON]>;
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def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
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(and DPR:$Vm, (vnotd DPR:$Vd)))),
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(VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>,
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Requires<[HasNEON]>;
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def : Pat<(v1i64 (or (and DPR:$Vn, DPR:$Vd),
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(and DPR:$Vm, (vnotd DPR:$Vd)))),
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(VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>,
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Requires<[HasNEON]>;
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def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
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(ins QPR:$src1, QPR:$Vn, QPR:$Vm),
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N3RegFrm, IIC_VCNTiQ,
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@ -4533,11 +4542,19 @@ def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 QPR:$src1),
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(v4f32 QPR:$Vn), (v4f32 QPR:$Vm))),
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(VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
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Requires<[HasNEON]>;
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def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 QPR:$src1),
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(v2i64 QPR:$Vn), (v2i64 QPR:$Vm))),
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(VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
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Requires<[HasNEON]>;
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def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
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(and QPR:$Vm, (vnotq QPR:$Vd)))),
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(VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>,
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Requires<[HasNEON]>;
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def : Pat<(v2i64 (or (and QPR:$Vn, QPR:$Vd),
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(and QPR:$Vm, (vnotq QPR:$Vd)))),
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(VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>,
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Requires<[HasNEON]>;
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// VBIF : Vector Bitwise Insert if False
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// like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
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@ -162,6 +162,34 @@ define <4 x float> @g4(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind
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ret <4 x float> %vbsl4.i
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}
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define <1 x i64> @test_vbsl_s64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind readnone optsize ssp {
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; CHECK: test_vbsl_s64:
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; CHECK: vbsl d
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%vbsl3.i = tail call <1 x i64> @llvm.arm.neon.vbsl.v1i64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind
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ret <1 x i64> %vbsl3.i
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}
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define <1 x i64> @test_vbsl_u64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind readnone optsize ssp {
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; CHECK: test_vbsl_u64:
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; CHECK: vbsl d
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%vbsl3.i = tail call <1 x i64> @llvm.arm.neon.vbsl.v1i64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind
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ret <1 x i64> %vbsl3.i
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}
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define <2 x i64> @test_vbslq_s64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {
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; CHECK: test_vbslq_s64:
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; CHECK: vbsl q
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%vbsl3.i = tail call <2 x i64> @llvm.arm.neon.vbsl.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind
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ret <2 x i64> %vbsl3.i
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}
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define <2 x i64> @test_vbslq_u64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {
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; CHECK: test_vbslq_u64:
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; CHECK: vbsl q
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%vbsl3.i = tail call <2 x i64> @llvm.arm.neon.vbsl.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind
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ret <2 x i64> %vbsl3.i
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}
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declare <4 x i32> @llvm.arm.neon.vbsl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vbsl.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone
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declare <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
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@ -170,3 +198,5 @@ declare <4 x i16> @llvm.arm.neon.vbsl.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) nou
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declare <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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declare <2 x float> @llvm.arm.neon.vbsl.v2f32(<2 x float>, <2 x float>, <2 x float>) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vbsl.v4f32(<4 x float>, <4 x float>, <4 x float>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vbsl.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) nounwind readnone
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declare <1 x i64> @llvm.arm.neon.vbsl.v1i64(<1 x i64>, <1 x i64>, <1 x i64>) nounwind readnone
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