forked from OSchip/llvm-project
[X86][X87] Add test case for PR34080
Test with/without the sandybridge (default) model for SSE2, SSE3 and AVX targets. pre-SSE3 the issue is the order of the fpsw and fpcw load/stores (with SSE3 trunc-store FIST instructions avoid the sw/cw manipulations). llvm-svn: 310198
This commit is contained in:
Simon Pilgrim
parent
aabfbfa5fc
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5489781cc7
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse2 | FileCheck %s --check-prefix=SSE2
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse2 -mcpu=x86-64 | FileCheck %s --check-prefix=SSE2-BROKEN
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse3 | FileCheck %s --check-prefix=SSE3
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse3 -mcpu=prescott | FileCheck %s --check-prefix=SSE3
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx | FileCheck %s --check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx -mcpu=sandybridge | FileCheck %s --check-prefix=AVX
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define void @_Z1fe(x86_fp80 %z) local_unnamed_addr #0 {
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; SSE2-LABEL: _Z1fe:
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; SSE2: ## BB#0: ## %entry
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; SSE2-NEXT: pushq %rbp
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; SSE2-NEXT: Lcfi0:
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; SSE2-NEXT: .cfi_def_cfa_offset 16
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; SSE2-NEXT: Lcfi1:
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; SSE2-NEXT: .cfi_offset %rbp, -16
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; SSE2-NEXT: movq %rsp, %rbp
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; SSE2-NEXT: Lcfi2:
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; SSE2-NEXT: .cfi_def_cfa_register %rbp
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; SSE2-NEXT: fldt 16(%rbp)
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; SSE2-NEXT: fnstcw -4(%rbp)
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; SSE2-NEXT: movzwl -4(%rbp), %eax
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; SSE2-NEXT: movw $3199, -4(%rbp) ## imm = 0xC7F
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; SSE2-NEXT: fldcw -4(%rbp)
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; SSE2-NEXT: movw %ax, -4(%rbp)
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; SSE2-NEXT: fistl -8(%rbp)
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; SSE2-NEXT: fldcw -4(%rbp)
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; SSE2-NEXT: cvtsi2sdl -8(%rbp), %xmm0
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; SSE2-NEXT: movsd %xmm0, -64(%rbp)
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; SSE2-NEXT: movsd %xmm0, -32(%rbp)
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; SSE2-NEXT: fsubl -32(%rbp)
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; SSE2-NEXT: flds {{.*}}(%rip)
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; SSE2-NEXT: fmul %st(0), %st(1)
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; SSE2-NEXT: fnstcw -2(%rbp)
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; SSE2-NEXT: movzwl -2(%rbp), %eax
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; SSE2-NEXT: movw $3199, -2(%rbp) ## imm = 0xC7F
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; SSE2-NEXT: fldcw -2(%rbp)
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; SSE2-NEXT: movw %ax, -2(%rbp)
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; SSE2-NEXT: fxch %st(1)
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; SSE2-NEXT: fistl -12(%rbp)
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; SSE2-NEXT: fldcw -2(%rbp)
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; SSE2-NEXT: xorps %xmm0, %xmm0
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; SSE2-NEXT: cvtsi2sdl -12(%rbp), %xmm0
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; SSE2-NEXT: movsd %xmm0, -56(%rbp)
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; SSE2-NEXT: movsd %xmm0, -24(%rbp)
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; SSE2-NEXT: fsubl -24(%rbp)
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; SSE2-NEXT: fmulp %st(1)
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; SSE2-NEXT: fstpl -48(%rbp)
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; SSE2-NEXT: popq %rbp
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; SSE2-NEXT: retq
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;
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; SSE2-BROKEN-LABEL: _Z1fe:
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; SSE2-BROKEN: ## BB#0: ## %entry
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; SSE2-BROKEN-NEXT: pushq %rbp
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; SSE2-BROKEN-NEXT: Lcfi0:
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; SSE2-BROKEN-NEXT: .cfi_def_cfa_offset 16
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; SSE2-BROKEN-NEXT: Lcfi1:
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; SSE2-BROKEN-NEXT: .cfi_offset %rbp, -16
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; SSE2-BROKEN-NEXT: movq %rsp, %rbp
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; SSE2-BROKEN-NEXT: Lcfi2:
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; SSE2-BROKEN-NEXT: .cfi_def_cfa_register %rbp
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; SSE2-BROKEN-NEXT: fnstcw -4(%rbp)
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; SSE2-BROKEN-NEXT: movzwl -4(%rbp), %eax
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; SSE2-BROKEN-NEXT: movw $3199, -4(%rbp) ## imm = 0xC7F
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; SSE2-BROKEN-NEXT: fldcw -4(%rbp)
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; SSE2-BROKEN-NEXT: fldt 16(%rbp)
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; SSE2-BROKEN-NEXT: movw %ax, -4(%rbp)
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; SSE2-BROKEN-NEXT: fistl -8(%rbp)
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; SSE2-BROKEN-NEXT: fldcw -4(%rbp)
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; SSE2-BROKEN-NEXT: cvtsi2sdl -8(%rbp), %xmm0
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; SSE2-BROKEN-NEXT: movsd %xmm0, -64(%rbp)
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; SSE2-BROKEN-NEXT: movsd %xmm0, -32(%rbp)
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; SSE2-BROKEN-NEXT: fsubl -32(%rbp)
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; SSE2-BROKEN-NEXT: fnstcw -2(%rbp)
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; SSE2-BROKEN-NEXT: flds {{.*}}(%rip)
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; SSE2-BROKEN-NEXT: movzwl -2(%rbp), %eax
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; SSE2-BROKEN-NEXT: movw $3199, -2(%rbp) ## imm = 0xC7F
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; SSE2-BROKEN-NEXT: fldcw -2(%rbp)
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; SSE2-BROKEN-NEXT: fmul %st(0), %st(1)
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; SSE2-BROKEN-NEXT: movw %ax, -2(%rbp)
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; SSE2-BROKEN-NEXT: fxch %st(1)
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; SSE2-BROKEN-NEXT: fistl -12(%rbp)
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; SSE2-BROKEN-NEXT: fldcw -2(%rbp)
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; SSE2-BROKEN-NEXT: xorps %xmm0, %xmm0
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; SSE2-BROKEN-NEXT: cvtsi2sdl -12(%rbp), %xmm0
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; SSE2-BROKEN-NEXT: movsd %xmm0, -56(%rbp)
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; SSE2-BROKEN-NEXT: movsd %xmm0, -24(%rbp)
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; SSE2-BROKEN-NEXT: fsubl -24(%rbp)
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; SSE2-BROKEN-NEXT: fmulp %st(1)
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; SSE2-BROKEN-NEXT: fstpl -48(%rbp)
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; SSE2-BROKEN-NEXT: popq %rbp
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; SSE2-BROKEN-NEXT: retq
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;
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; SSE3-LABEL: _Z1fe:
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; SSE3: ## BB#0: ## %entry
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; SSE3-NEXT: pushq %rbp
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; SSE3-NEXT: Lcfi0:
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; SSE3-NEXT: .cfi_def_cfa_offset 16
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; SSE3-NEXT: Lcfi1:
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; SSE3-NEXT: .cfi_offset %rbp, -16
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; SSE3-NEXT: movq %rsp, %rbp
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; SSE3-NEXT: Lcfi2:
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; SSE3-NEXT: .cfi_def_cfa_register %rbp
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; SSE3-NEXT: fldt 16(%rbp)
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; SSE3-NEXT: fld %st(0)
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; SSE3-NEXT: fisttpl -4(%rbp)
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; SSE3-NEXT: cvtsi2sdl -4(%rbp), %xmm0
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; SSE3-NEXT: movsd %xmm0, -48(%rbp)
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; SSE3-NEXT: movsd %xmm0, -24(%rbp)
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; SSE3-NEXT: fsubl -24(%rbp)
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; SSE3-NEXT: flds {{.*}}(%rip)
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; SSE3-NEXT: fmul %st(0), %st(1)
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; SSE3-NEXT: fld %st(1)
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; SSE3-NEXT: fisttpl -8(%rbp)
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; SSE3-NEXT: xorps %xmm0, %xmm0
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; SSE3-NEXT: cvtsi2sdl -8(%rbp), %xmm0
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; SSE3-NEXT: movsd %xmm0, -40(%rbp)
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; SSE3-NEXT: movsd %xmm0, -16(%rbp)
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; SSE3-NEXT: fxch %st(1)
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; SSE3-NEXT: fsubl -16(%rbp)
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; SSE3-NEXT: fmulp %st(1)
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; SSE3-NEXT: fstpl -32(%rbp)
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; SSE3-NEXT: popq %rbp
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; SSE3-NEXT: retq
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;
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; AVX-LABEL: _Z1fe:
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; AVX: ## BB#0: ## %entry
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; AVX-NEXT: pushq %rbp
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; AVX-NEXT: Lcfi0:
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; AVX-NEXT: .cfi_def_cfa_offset 16
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; AVX-NEXT: Lcfi1:
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; AVX-NEXT: .cfi_offset %rbp, -16
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; AVX-NEXT: movq %rsp, %rbp
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; AVX-NEXT: Lcfi2:
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; AVX-NEXT: .cfi_def_cfa_register %rbp
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; AVX-NEXT: fldt 16(%rbp)
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; AVX-NEXT: fld %st(0)
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; AVX-NEXT: fisttpl -4(%rbp)
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; AVX-NEXT: vcvtsi2sdl -4(%rbp), %xmm0, %xmm0
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; AVX-NEXT: vmovsd %xmm0, -48(%rbp)
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; AVX-NEXT: vmovsd %xmm0, -24(%rbp)
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; AVX-NEXT: fsubl -24(%rbp)
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; AVX-NEXT: flds {{.*}}(%rip)
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; AVX-NEXT: fmul %st(0), %st(1)
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; AVX-NEXT: fld %st(1)
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; AVX-NEXT: fisttpl -8(%rbp)
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; AVX-NEXT: vcvtsi2sdl -8(%rbp), %xmm1, %xmm0
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; AVX-NEXT: vmovsd %xmm0, -40(%rbp)
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; AVX-NEXT: vmovsd %xmm0, -16(%rbp)
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; AVX-NEXT: fxch %st(1)
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; AVX-NEXT: fsubl -16(%rbp)
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; AVX-NEXT: fmulp %st(1)
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; AVX-NEXT: fstpl -32(%rbp)
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; AVX-NEXT: popq %rbp
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; AVX-NEXT: retq
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entry:
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%tx = alloca [3 x double], align 16
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%0 = bitcast [3 x double]* %tx to i8*
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%conv = fptosi x86_fp80 %z to i32
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%conv1 = sitofp i32 %conv to double
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%arrayidx = getelementptr inbounds [3 x double], [3 x double]* %tx, i64 0, i64 0
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store double %conv1, double* %arrayidx, align 16
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%conv4 = fpext double %conv1 to x86_fp80
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%sub = fsub x86_fp80 %z, %conv4
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%mul = fmul x86_fp80 %sub, 0xK40178000000000000000
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%conv.1 = fptosi x86_fp80 %mul to i32
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%conv1.1 = sitofp i32 %conv.1 to double
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%arrayidx.1 = getelementptr inbounds [3 x double], [3 x double]* %tx, i64 0, i64 1
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store double %conv1.1, double* %arrayidx.1, align 8
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%conv4.1 = fpext double %conv1.1 to x86_fp80
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%sub.1 = fsub x86_fp80 %mul, %conv4.1
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%mul.1 = fmul x86_fp80 %sub.1, 0xK40178000000000000000
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%conv5 = fptrunc x86_fp80 %mul.1 to double
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%arrayidx6 = getelementptr inbounds [3 x double], [3 x double]* %tx, i64 0, i64 2
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store double %conv5, double* %arrayidx6, align 16
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ret void
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}
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attributes #0 = { noinline uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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