forked from OSchip/llvm-project
Improve generated code for extending loads and some trunc stores on ARM.
Teach TargetSelectionDAG about lengthening loads for vector types and set v4i8 as legal. Allow FP_TO_UINT for v4i16 from v4i32. llvm-svn: 150956
This commit is contained in:
James Molloy
parent
be3df7b3ee
commit
547d4c0662
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@ -657,6 +657,51 @@ def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
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return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
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}]>;
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def extloadvi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
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return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1;
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}]>;
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def extloadvi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
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return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
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}]>;
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def extloadvi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
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return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
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}]>;
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def extloadvi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
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return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
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}]>;
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def extloadvf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
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return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::f32;
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}]>;
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def extloadvf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
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return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::f64;
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}]>;
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def sextloadvi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
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return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1;
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}]>;
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def sextloadvi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
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return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
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}]>;
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def sextloadvi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
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return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
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}]>;
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def sextloadvi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
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return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
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}]>;
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def zextloadvi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
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return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1;
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}]>;
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def zextloadvi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
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return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
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}]>;
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def zextloadvi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
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return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
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}]>;
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def zextloadvi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
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return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
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}]>;
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// store fragments.
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def unindexedstore : PatFrag<(ops node:$val, node:$ptr),
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(st node:$val, node:$ptr), [{
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@ -533,9 +533,13 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::SETCC, MVT::v1i64, Expand);
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setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
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// Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
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// a destination type that is wider than the source.
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// a destination type that is wider than the source, and nor does
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// it have a FP_TO_[SU]INT instruction with a narrower destination than
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// source.
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setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
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setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
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setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
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setTargetDAGCombine(ISD::INTRINSIC_VOID);
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setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
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@ -555,7 +559,15 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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setTargetDAGCombine(ISD::FP_TO_UINT);
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setTargetDAGCombine(ISD::FDIV);
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setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand);
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// It is legal to extload from v4i8 to v4i16 or v4i32.
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MVT Tys[6] = {MVT::v8i8, MVT::v4i8, MVT::v2i8,
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MVT::v4i16, MVT::v2i16,
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MVT::v2i32};
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for (unsigned i = 0; i < 6; ++i) {
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setLoadExtAction(ISD::EXTLOAD, Tys[i], Legal);
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setLoadExtAction(ISD::ZEXTLOAD, Tys[i], Legal);
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setLoadExtAction(ISD::SEXTLOAD, Tys[i], Legal);
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}
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}
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computeRegisterProperties();
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@ -3058,12 +3070,22 @@ SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
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}
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static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
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assert(Op.getValueType().getVectorElementType() == MVT::i32
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&& "Unexpected custom lowering");
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EVT VT = Op.getValueType();
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DebugLoc dl = Op.getDebugLoc();
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if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
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return Op;
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return DAG.UnrollVectorOp(Op.getNode());
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if (Op.getValueType().getVectorElementType() == MVT::i32) {
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if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
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return Op;
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return DAG.UnrollVectorOp(Op.getNode());
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}
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assert(Op.getOperand(0).getValueType() == MVT::v4f32 &&
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"Invalid type for custom lowering!");
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if (VT != MVT::v4i16)
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return DAG.UnrollVectorOp(Op.getNode());
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Op = DAG.getNode(Op.getOpcode(), dl, MVT::v4i32, Op.getOperand(0));
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return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
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}
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static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
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@ -5624,6 +5624,117 @@ def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
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def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
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def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
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// Vector lengthening move with load, matching extending loads.
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// extload, zextload and sextload for a standard lengthening load. Example:
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// Lengthen_Single<"8", "i16", "i8"> = Pat<(v8i16 (extloadvi8 addrmode5:$addr))
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// (VMOVLuv8i16 (VLDRD addrmode5:$addr))>;
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multiclass Lengthen_Single<string DestLanes, string DestTy, string SrcTy> {
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def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("extloadv" # SrcTy) addrmode5:$addr)),
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(!cast<Instruction>("VMOVLuv" # DestLanes # DestTy)
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(VLDRD addrmode5:$addr))>;
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def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("zextloadv" # SrcTy) addrmode5:$addr)),
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(!cast<Instruction>("VMOVLuv" # DestLanes # DestTy)
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(VLDRD addrmode5:$addr))>;
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def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("sextloadv" # SrcTy) addrmode5:$addr)),
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(!cast<Instruction>("VMOVLsv" # DestLanes # DestTy)
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(VLDRD addrmode5:$addr))>;
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}
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// extload, zextload and sextload for a lengthening load which only uses
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// half the lanes available. Example:
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// Lengthen_HalfSingle<"4", "i16", "8", "i16", "i8"> =
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// Pat<(v4i16 (extloadvi8 addrmode5:$addr))
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// (EXTRACT_SUBREG (VMOVLuv8i16 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
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// (VLDRS addrmode5:$addr),
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// ssub_0)),
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// dsub_0)>;
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multiclass Lengthen_HalfSingle<string DestLanes, string DestTy, string SrcTy,
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string InsnLanes, string InsnTy> {
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def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("extloadv" # SrcTy) addrmode5:$addr)),
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), ssub_0)),
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dsub_0)>;
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def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("zextloadv" # SrcTy) addrmode5:$addr)),
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), ssub_0)),
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dsub_0)>;
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def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("sextloadv" # SrcTy) addrmode5:$addr)),
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # InsnLanes # InsnTy)
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), ssub_0)),
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dsub_0)>;
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}
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// extload, zextload and sextload for a lengthening load followed by another
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// lengthening load, to quadruple the initial length.
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// Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32", qsub_0> =
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// Pat<(v4i32 (extloadvi8 addrmode5:$addr))
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// (EXTRACT_SUBREG (VMOVLuv4i32
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// (EXTRACT_SUBREG (VMOVLuv8i16 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
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// (VLDRS addrmode5:$addr),
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// ssub_0)),
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// dsub_0)),
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// qsub_0)>;
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multiclass Lengthen_Double<string DestLanes, string DestTy, string SrcTy,
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string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
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string Insn2Ty, SubRegIndex RegType> {
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def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("extloadv" # SrcTy) addrmode5:$addr)),
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
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ssub_0)), dsub_0)),
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RegType)>;
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def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("zextloadv" # SrcTy) addrmode5:$addr)),
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
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ssub_0)), dsub_0)),
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RegType)>;
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def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("sextloadv" # SrcTy) addrmode5:$addr)),
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
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ssub_0)), dsub_0)),
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RegType)>;
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}
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defm : Lengthen_Single<"8", "i16", "i8">; // v8i8 -> v8i16
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defm : Lengthen_Single<"4", "i32", "i16">; // v4i16 -> v4i32
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defm : Lengthen_Single<"2", "i64", "i32">; // v2i32 -> v2i64
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defm : Lengthen_HalfSingle<"4", "i16", "i8", "8", "i16">; // v4i8 -> v4i16
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defm : Lengthen_HalfSingle<"2", "i16", "i8", "8", "i16">; // v2i8 -> v2i16
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defm : Lengthen_HalfSingle<"2", "i32", "i16", "4", "i32">; // v2i16 -> v2i32
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// Double lengthening - v4i8 -> v4i16 -> v4i32
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defm : Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32", qsub_0>;
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// v2i8 -> v2i16 -> v2i32
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defm : Lengthen_Double<"2", "i32", "i8", "8", "i16", "4", "i32", dsub_0>;
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// v2i16 -> v2i32 -> v2i64
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defm : Lengthen_Double<"2", "i64", "i16", "4", "i32", "2", "i64", qsub_0>;
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// Triple lengthening - v2i8 -> v2i16 -> v2i32 -> v2i64
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def : Pat<(v2i64 (extloadvi8 addrmode5:$addr)),
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(VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), ssub_0)),
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dsub_0)), dsub_0))>;
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def : Pat<(v2i64 (zextloadvi8 addrmode5:$addr)),
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(VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), ssub_0)),
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dsub_0)), dsub_0))>;
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def : Pat<(v2i64 (sextloadvi8 addrmode5:$addr)),
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(VMOVLsv2i64 (EXTRACT_SUBREG (VMOVLsv4i32 (EXTRACT_SUBREG (VMOVLsv8i16
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), ssub_0)),
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dsub_0)), dsub_0))>;
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//===----------------------------------------------------------------------===//
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// Assembler aliases
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