maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[AMDGPU] Fix typo consecutive in GCNNSAReassign

This commit is contained in:
Joe Nash 2022-03-15 12:36:51 -04:00
parent 9a5f04e01d
commit 5464fd36ba
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp
View File

@ -184,7 +184,7 @@ GCNNSAReassign::CheckNSA(const MachineInstr &MI, bool Fast) const {
// logic to find free registers will be much more complicated with much // logic to find free registers will be much more complicated with much
// less chances for success. That seems reasonable to assume that in most // less chances for success. That seems reasonable to assume that in most
// cases a tuple is used because a vector variable contains different // cases a tuple is used because a vector variable contains different
// parts of an address and it is either already consequitive or cannot // parts of an address and it is either already consecutive or cannot
// be reassigned if not. If needed it is better to rely on register // be reassigned if not. If needed it is better to rely on register
// coalescer to process such address tuples. // coalescer to process such address tuples.
if (MRI->getRegClass(Reg) != &AMDGPU::VGPR_32RegClass || Op.getSubReg()) if (MRI->getRegClass(Reg) != &AMDGPU::VGPR_32RegClass || Op.getSubReg())