From 5464fd36bad57e703d276022bd27b858689b4f61 Mon Sep 17 00:00:00 2001 From: Joe Nash Date: Tue, 15 Mar 2022 12:36:51 -0400 Subject: [PATCH] [AMDGPU] Fix typo consecutive in GCNNSAReassign --- llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp b/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp index c39e47363d76..68e72bc00874 100644 --- a/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp +++ b/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp @@ -184,7 +184,7 @@ GCNNSAReassign::CheckNSA(const MachineInstr &MI, bool Fast) const { // logic to find free registers will be much more complicated with much // less chances for success. That seems reasonable to assume that in most // cases a tuple is used because a vector variable contains different - // parts of an address and it is either already consequitive or cannot + // parts of an address and it is either already consecutive or cannot // be reassigned if not. If needed it is better to rely on register // coalescer to process such address tuples. if (MRI->getRegClass(Reg) != &AMDGPU::VGPR_32RegClass || Op.getSubReg())