forked from OSchip/llvm-project
[RISCV][NFC] Refactor VL patterns for vnsrl and vnsra
Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D123274
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@ -861,7 +861,7 @@ multiclass VPatWidenMultiplyAddVL_VV_VX<PatFrag op1, string instruction_name> {
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foreach vtiTowti = AllWidenableIntVectors in {
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defvar vti = vtiTowti.Vti;
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defvar wti = vtiTowti.Wti;
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def : Pat<(wti.Vector
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def : Pat<(wti.Vector
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(riscv_add_vl wti.RegClass:$rd,
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(op1 vti.RegClass:$rs1,
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(vti.Vector vti.RegClass:$rs2),
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@ -882,6 +882,23 @@ multiclass VPatWidenMultiplyAddVL_VV_VX<PatFrag op1, string instruction_name> {
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}
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}
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multiclass VPatNarrowShiftSplat_WX_WI<SDNode op, string instruction_name> {
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foreach vtiTowti = AllWidenableIntVectors in {
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defvar vti = vtiTowti.Vti;
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defvar wti = vtiTowti.Wti;
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def : Pat<(vti.Vector (riscv_trunc_vector_vl
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(wti.Vector (op wti.RegClass:$rs1, (SplatPat XLenVT:$rs2),
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true_mask, VLOpFrag)), true_mask, VLOpFrag)),
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(!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX)
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wti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>;
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def : Pat<(vti.Vector (riscv_trunc_vector_vl
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(wti.Vector (op wti.RegClass:$rs1, (SplatPat_uimm5 uimm5:$rs2),
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true_mask, VLOpFrag)), true_mask, VLOpFrag)),
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(!cast<Instruction>(instruction_name#"_WI_"#vti.LMul.MX)
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wti.RegClass:$rs1, uimm5:$rs2, GPR:$vl, vti.Log2SEW)>;
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}
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}
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//===----------------------------------------------------------------------===//
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// Patterns.
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//===----------------------------------------------------------------------===//
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@ -952,6 +969,13 @@ foreach vti = AllIntegerVectors in {
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defm : VPatBinarySDNode_V_WV_WX_WI<srl, "PseudoVNSRL">;
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defm : VPatBinarySDNode_V_WV_WX_WI<sra, "PseudoVNSRA">;
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defm : VPatNarrowShiftSplat_WX_WI<riscv_sra_vl, "PseudoVNSRA">;
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defm : VPatNarrowShiftSplat_WX_WI<riscv_srl_vl, "PseudoVNSRL">;
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defm : VPatNarrowShiftSplatExt_WX<riscv_sra_vl, riscv_sext_vl_oneuse, "PseudoVNSRA">;
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defm : VPatNarrowShiftSplatExt_WX<riscv_sra_vl, riscv_zext_vl_oneuse, "PseudoVNSRA">;
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defm : VPatNarrowShiftSplatExt_WX<riscv_srl_vl, riscv_sext_vl_oneuse, "PseudoVNSRL">;
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defm : VPatNarrowShiftSplatExt_WX<riscv_srl_vl, riscv_zext_vl_oneuse, "PseudoVNSRL">;
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foreach vtiTowti = AllWidenableIntVectors in {
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defvar vti = vtiTowti.Vti;
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defvar wti = vtiTowti.Wti;
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@ -966,39 +990,6 @@ foreach vtiTowti = AllWidenableIntVectors in {
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(!cast<Instruction>("PseudoVNSRL_WX_"#vti.LMul.MX#"_MASK")
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(vti.Vector (IMPLICIT_DEF)), wti.RegClass:$rs1, X0,
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(vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
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def : Pat<(vti.Vector
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(riscv_trunc_vector_vl
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(wti.Vector
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(riscv_sra_vl wti.RegClass:$rs1, (SplatPat XLenVT:$rs2),
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true_mask, VLOpFrag)), true_mask, VLOpFrag)),
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(!cast<Instruction>("PseudoVNSRA_WX_"#vti.LMul.MX)
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wti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>;
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defm : VPatNarrowShiftSplatExt_WX<riscv_sra_vl, riscv_sext_vl_oneuse, "PseudoVNSRA">;
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defm : VPatNarrowShiftSplatExt_WX<riscv_sra_vl, riscv_zext_vl_oneuse, "PseudoVNSRA">;
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def : Pat<(vti.Vector
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(riscv_trunc_vector_vl
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(wti.Vector
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(riscv_sra_vl wti.RegClass:$rs1, (SplatPat_uimm5 uimm5:$rs2),
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true_mask, VLOpFrag)), true_mask, VLOpFrag)),
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(!cast<Instruction>("PseudoVNSRA_WI_"#vti.LMul.MX)
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wti.RegClass:$rs1, uimm5:$rs2, GPR:$vl, vti.Log2SEW)>;
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def : Pat<(vti.Vector
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(riscv_trunc_vector_vl
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(wti.Vector
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(riscv_srl_vl wti.RegClass:$rs1, (SplatPat XLenVT:$rs2),
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true_mask, VLOpFrag)), true_mask, VLOpFrag)),
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(!cast<Instruction>("PseudoVNSRL_WX_"#vti.LMul.MX)
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wti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>;
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defm : VPatNarrowShiftSplatExt_WX<riscv_srl_vl, riscv_sext_vl_oneuse, "PseudoVNSRL">;
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defm : VPatNarrowShiftSplatExt_WX<riscv_srl_vl, riscv_zext_vl_oneuse, "PseudoVNSRL">;
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def : Pat<(vti.Vector
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(riscv_trunc_vector_vl
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(wti.Vector
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(riscv_srl_vl wti.RegClass:$rs1, (SplatPat_uimm5 uimm5:$rs2),
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true_mask, VLOpFrag)), true_mask, VLOpFrag)),
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(!cast<Instruction>("PseudoVNSRL_WI_"#vti.LMul.MX)
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wti.RegClass:$rs1, uimm5:$rs2, GPR:$vl, vti.Log2SEW)>;
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}
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// 12.8. Vector Integer Comparison Instructions
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