forked from OSchip/llvm-project
[x86] auto-generate complete checks; NFC
llvm-svn: 312503
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4e10b61d8f
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543f3fda83
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@ -1,9 +1,21 @@
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 | FileCheck %s
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
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define void @merge_store(i32* nocapture %a) {
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; CHECK-LABEL: merge_store:
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; CHECK: movq
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; CHECK: movq
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: movabsq $4294967297, %rcx # imm = 0x100000001
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: .LBB0_1: # %for.body
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: movq %rcx, (%rdi,%rax,4)
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; CHECK-NEXT: movq %rcx, 8(%rdi,%rax,4)
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; CHECK-NEXT: addq $4, %rax
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; CHECK-NEXT: cmpl $1000, %eax # imm = 0x3E8
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; CHECK-NEXT: jl .LBB0_1
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; CHECK-NEXT: # BB#2: # %for.end
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; CHECK-NEXT: retq
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entry:
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br label %for.body
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@ -29,10 +41,12 @@ entry:
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ret void
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}
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;; CHECK-LABEL: indexed-store-merge
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;; CHECK: movl $0, 2(%rsi,%rdi)
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;; CHECK: movb $0, (%rsi)
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define void @indexed-store-merge(i64 %p, i8* %v) {
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define void @indexed_store_merge(i64 %p, i8* %v) {
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; CHECK-LABEL: indexed_store_merge:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: movl $0, 2(%rsi,%rdi)
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; CHECK-NEXT: movb $0, (%rsi)
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; CHECK-NEXT: retq
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entry:
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%p2 = add nsw i64 %p, 2
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%v2 = getelementptr i8, i8* %v, i64 %p2
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