forked from OSchip/llvm-project
[x86] fix formatting; NFC
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ed4a91300b
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5424fb164a
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@ -28846,7 +28846,7 @@ SDValue X86TargetLowering::LowerWin64_INT128_TO_FP(SDValue Op,
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// Return true if the required (according to Opcode) shift-imm form is natively
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// supported by the Subtarget
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static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget &Subtarget,
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static bool supportedVectorShiftWithImm(MVT VT, const X86Subtarget &Subtarget,
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unsigned Opcode) {
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if (VT.getScalarSizeInBits() < 16)
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return false;
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@ -28866,14 +28866,14 @@ static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget &Subtarget,
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// The shift amount is a variable, but it is the same for all vector lanes.
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// These instructions are defined together with shift-immediate.
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static
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bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget &Subtarget,
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bool supportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget &Subtarget,
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unsigned Opcode) {
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return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
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return supportedVectorShiftWithImm(VT, Subtarget, Opcode);
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}
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// Return true if the required (according to Opcode) variable-shift form is
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// natively supported by the Subtarget
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static bool SupportedVectorVarShift(MVT VT, const X86Subtarget &Subtarget,
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static bool supportedVectorVarShift(MVT VT, const X86Subtarget &Subtarget,
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unsigned Opcode) {
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if (!Subtarget.hasInt256() || VT.getScalarSizeInBits() < 16)
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@ -28949,7 +28949,7 @@ static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
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uint64_t ShiftAmt = APIntShiftAmt.getZExtValue();
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if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
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if (supportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
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return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
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// i64 SRA needs to be performed as partial shifts.
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@ -29033,7 +29033,7 @@ static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
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unsigned X86OpcV = getTargetVShiftUniformOpcode(Opcode, true);
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if (SDValue BaseShAmt = DAG.getSplatValue(Amt)) {
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if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Opcode)) {
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if (supportedVectorShiftWithBaseAmnt(VT, Subtarget, Opcode)) {
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MVT EltVT = VT.getVectorElementType();
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assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
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if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
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@ -29051,7 +29051,7 @@ static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
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!Subtarget.hasXOP()) {
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unsigned NumElts = VT.getVectorNumElements();
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MVT ExtVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
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if (SupportedVectorShiftWithBaseAmnt(ExtVT, Subtarget, Opcode)) {
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if (supportedVectorShiftWithBaseAmnt(ExtVT, Subtarget, Opcode)) {
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unsigned LogicalOp = (Opcode == ISD::SHL ? ISD::SHL : ISD::SRL);
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unsigned LogicalX86Op = getTargetVShiftUniformOpcode(LogicalOp, false);
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BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
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@ -29103,7 +29103,7 @@ static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
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return SDValue();
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}
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if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
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if (supportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
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return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
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}
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return SDValue();
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@ -29196,7 +29196,7 @@ static SDValue LowerShift(SDValue Op, const X86Subtarget &Subtarget,
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if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
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return V;
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if (SupportedVectorVarShift(VT, Subtarget, Opc))
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if (supportedVectorVarShift(VT, Subtarget, Opc))
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return Op;
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// XOP has 128-bit variable logical/arithmetic shifts.
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@ -29815,8 +29815,8 @@ static SDValue LowerRotate(SDValue Op, const X86Subtarget &Subtarget,
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}
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bool ConstantAmt = ISD::isBuildVectorOfConstantSDNodes(Amt.getNode());
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bool LegalVarShifts = SupportedVectorVarShift(VT, Subtarget, ISD::SHL) &&
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SupportedVectorVarShift(VT, Subtarget, ISD::SRL);
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bool LegalVarShifts = supportedVectorVarShift(VT, Subtarget, ISD::SHL) &&
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supportedVectorVarShift(VT, Subtarget, ISD::SRL);
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// Fallback for splats + all supported variable shifts.
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// Fallback for non-constants AVX2 vXi16 as well.
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@ -45816,7 +45816,7 @@ static SDValue combineAndMaskToShift(SDNode *N, SelectionDAG &DAG,
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if (isBitwiseNot(Op0))
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return SDValue();
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if (!SupportedVectorShiftWithImm(VT0.getSimpleVT(), Subtarget, ISD::SRL))
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if (!supportedVectorShiftWithImm(VT0.getSimpleVT(), Subtarget, ISD::SRL))
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return SDValue();
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unsigned EltBitWidth = VT0.getScalarSizeInBits();
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