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[mips] Guard 'nop' properly and add mips16's nop instruction 

Reviewers: smaksimovic, atanasyan, abeserminji

Differential Revision: https://reviews.llvm.org/D47583

llvm-svn: 333739
This commit is contained in:
Simon Dardis 2018-06-01 10:46:00 +00:00
parent d6ca063907
commit 54217598b6
5 changed files with 33 additions and 13 deletions
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4
llvm/lib/Target/Mips/MicroMipsInstrInfo.td
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@ -1278,8 +1278,8 @@ let Predicates = [InMicroMips] in {
II_DIVU, 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>, ISA_MICROMIPS;
def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>;
def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>;
def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>, ISA_MICROMIPS;
def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>, ISA_MICROMIPS;
def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MICROMIPS;
def : MipsInstAlias<"di", (DI_MM ZERO), 1>, ISA_MICROMIPS;
def : MipsInstAlias<"neg $rt, $rs",

4
llvm/lib/Target/Mips/Mips16InstrInfo.td
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@ -1914,3 +1914,7 @@ def CONSTPOOL_ENTRY :
MipsPseudo16<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
i32imm:$size), "foo", []>;
// Instruction Aliases
let EncodingPredicates = [InMips16Mode] in
def : MipsInstAlias<"nop", (Move32R16 ZERO, S0)>;

25
llvm/lib/Target/Mips/MipsInstrInfo.td
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@ -2308,18 +2308,20 @@ let AdditionalPredicates = [NotInMicroMips] in {
/// Word Swap Bytes Within Halfwords
def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>, SEB_FM<2, 0x20>,
ISA_MIPS32R2;
/// No operation.
def NOP : PseudoSE<(outs), (ins), []>,
PseudoInstExpansion<(SLL ZERO, ZERO, 0)>, ISA_MIPS1;
// FrameIndexes are legalized when they are operands from load/store
// instructions. The same not happens for stack address copies, so an
// add op with mem ComplexPattern is used and the stack address copy
// can be matched. It's similar to Sparc LEA_ADDRi
let AdditionalPredicates = [NotInMicroMips] in
def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>, ISA_MIPS1;
}
/// No operation.
def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
// FrameIndexes are legalized when they are operands from load/store
// instructions. The same not happens for stack address copies, so an
// add op with mem ComplexPattern is used and the stack address copy
// can be matched. It's similar to Sparc LEA_ADDRi
let AdditionalPredicates = [NotInMicroMips] in
def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>, ISA_MIPS1;
// MADD*/MSUB*
def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
ISA_MIPS32_NOT_32R6_64R6;
@ -2636,7 +2638,8 @@ let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<
"not $rt",
(NOR GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>;
def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>, ISA_MIPS1;
defm : OneOrTwoOperandMacroImmediateAlias<"add", ADDi>, ISA_MIPS1_NOT_32R6_64R6;

10
llvm/test/MC/Mips/mips16/invalid.s Normal file
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@ -0,0 +1,10 @@
# RUN: not llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mips16 < %s 2> %t
# RUN: FileCheck %s < %t
# Instructions which are invalid.
$label:
nop 4 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
nop $4 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
nop $label # CHECK: :[[@LINE]]:7: error: invalid operand for instruction

3
llvm/test/MC/Mips/mips16/valid.s Normal file
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@ -0,0 +1,3 @@
# RUN: llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mips16 -show-encoding -show-inst < %s
nop