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[AArch64][SVE] Asm: Support for TBL instruction. 

Support for SVE's TBL instruction for programmable table
lookup/permute using vector of element indices, e.g.

  tbl  z0.d, { z1.d }, z2.d

stores elements from z1, indexed by elements from z2, into z0.

llvm-svn: 336544
This commit is contained in:
Sander de Smalen 2018-07-09 12:32:56 +00:00
parent 8834779644
commit 54077dcfcb
4 changed files with 102 additions and 0 deletions
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2
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
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@ -539,6 +539,8 @@ let Predicates = [HasSVE] in {
defm ADR_LSL_ZZZ_S : sve_int_bin_cons_misc_0_a_32_lsl<0b10, "adr">;
defm ADR_LSL_ZZZ_D : sve_int_bin_cons_misc_0_a_64_lsl<0b11, "adr">;
defm TBL_ZZZ : sve_int_perm_tbl<"tbl">;
defm ZIP1_ZZZ : sve_int_perm_bin_perm_zz<0b000, "zip1">;
defm ZIP2_ZZZ : sve_int_perm_bin_perm_zz<0b001, "zip2">;
defm UZP1_ZZZ : sve_int_perm_bin_perm_zz<0b010, "uzp1">;

33
llvm/lib/Target/AArch64/SVEInstrFormats.td
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@ -571,6 +571,39 @@ multiclass sve_int_perm_dup_i<string asm> {
(!cast<Instruction>(NAME # _Q) ZPR128:$Zd, FPR128asZPR:$Qn, 0), 2>;
}
class sve_int_perm_tbl<bits<2> sz8_64, string asm, ZPRRegOp zprty,
RegisterOperand VecList>
: I<(outs zprty:$Zd), (ins VecList:$Zn, zprty:$Zm),
asm, "\t$Zd, $Zn, $Zm",
"",
[]>, Sched<[]> {
bits<5> Zd;
bits<5> Zm;
bits<5> Zn;
let Inst{31-24} = 0b00000101;
let Inst{23-22} = sz8_64;
let Inst{21} = 0b1;
let Inst{20-16} = Zm;
let Inst{15-10} = 0b001100;
let Inst{9-5} = Zn;
let Inst{4-0} = Zd;
}
multiclass sve_int_perm_tbl<string asm> {
def _B : sve_int_perm_tbl<0b00, asm, ZPR8, Z_b>;
def _H : sve_int_perm_tbl<0b01, asm, ZPR16, Z_h>;
def _S : sve_int_perm_tbl<0b10, asm, ZPR32, Z_s>;
def _D : sve_int_perm_tbl<0b11, asm, ZPR64, Z_d>;
def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
(!cast<Instruction>(NAME # _B) ZPR8:$Zd, ZPR8:$Zn, ZPR8:$Zm), 0>;
def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
(!cast<Instruction>(NAME # _H) ZPR16:$Zd, ZPR16:$Zn, ZPR16:$Zm), 0>;
def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
(!cast<Instruction>(NAME # _S) ZPR32:$Zd, ZPR32:$Zn, ZPR32:$Zm), 0>;
def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
(!cast<Instruction>(NAME # _D) ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zm), 0>;
}
//===----------------------------------------------------------------------===//
// SVE Vector Select Group

11
llvm/test/MC/AArch64/SVE/tbl-diagnostics.s Normal file
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@ -0,0 +1,11 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
tbl z0.h, z0.h, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: tbl z0.h, z0.h, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
tbl { z0.h }, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
// CHECK-NEXT: tbl { z0.h }, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

56
llvm/test/MC/AArch64/SVE/tbl.s Normal file
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@ -0,0 +1,56 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
tbl z31.b, z31.b, z31.b
// CHECK-INST: tbl z31.b, { z31.b }, z31.b
// CHECK-ENCODING: [0xff,0x33,0x3f,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 33 3f 05 <unknown>
tbl z31.h, z31.h, z31.h
// CHECK-INST: tbl z31.h, { z31.h }, z31.h
// CHECK-ENCODING: [0xff,0x33,0x7f,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 33 7f 05 <unknown>
tbl z31.s, z31.s, z31.s
// CHECK-INST: tbl z31.s, { z31.s }, z31.s
// CHECK-ENCODING: [0xff,0x33,0xbf,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 33 bf 05 <unknown>
tbl z31.d, z31.d, z31.d
// CHECK-INST: tbl z31.d, { z31.d }, z31.d
// CHECK-ENCODING: [0xff,0x33,0xff,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 33 ff 05 <unknown>
tbl z31.b, { z31.b }, z31.b
// CHECK-INST: tbl z31.b, { z31.b }, z31.b
// CHECK-ENCODING: [0xff,0x33,0x3f,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 33 3f 05 <unknown>
tbl z31.h, { z31.h }, z31.h
// CHECK-INST: tbl z31.h, { z31.h }, z31.h
// CHECK-ENCODING: [0xff,0x33,0x7f,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 33 7f 05 <unknown>
tbl z31.s, { z31.s }, z31.s
// CHECK-INST: tbl z31.s, { z31.s }, z31.s
// CHECK-ENCODING: [0xff,0x33,0xbf,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 33 bf 05 <unknown>
tbl z31.d, { z31.d }, z31.d
// CHECK-INST: tbl z31.d, { z31.d }, z31.d
// CHECK-ENCODING: [0xff,0x33,0xff,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 33 ff 05 <unknown>