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R600: Expand SELECT nodes rather than custom lowering them 

llvm-svn: 190079
This commit is contained in:
Tom Stellard 2013-09-05 18:38:03 +00:00
parent de60e25278
commit 53f2f90eb4
3 changed files with 52 additions and 15 deletions
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20
llvm/lib/Target/R600/R600ISelLowering.cpp
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@ -60,8 +60,12 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
setOperationAction(ISD::SETCC, MVT::f32, Expand);
setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
setOperationAction(ISD::SELECT, MVT::i32, Custom);
setOperationAction(ISD::SELECT, MVT::f32, Custom);
setOperationAction(ISD::SELECT, MVT::i32, Expand);
setOperationAction(ISD::SELECT, MVT::f32, Expand);
setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
setOperationAction(ISD::SELECT, MVT::v2f32, Expand);
setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
// Legalize loads and stores to the private address space.
setOperationAction(ISD::LOAD, MVT::i32, Custom);
@ -480,7 +484,6 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
case ISD::FCOS:
case ISD::FSIN: return LowerTrig(Op, DAG);
case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
case ISD::SELECT: return LowerSELECT(Op, DAG);
case ISD::STORE: return LowerSTORE(Op, DAG);
case ISD::LOAD: return LowerLOAD(Op, DAG);
case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
@ -930,17 +933,6 @@ SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
DAG.getCondCode(ISD::SETNE));
}
SDValue R600TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
return DAG.getNode(ISD::SELECT_CC,
SDLoc(Op),
Op.getValueType(),
Op.getOperand(0),
DAG.getConstant(0, MVT::i32),
Op.getOperand(1),
Op.getOperand(2),
DAG.getCondCode(ISD::SETNE));
}
/// LLVM generates byte-addresed pointers. For indirect addressing, we need to
/// convert these pointers to a register index. Each register holds
/// 16 bytes, (4 x 32bit sub-register), but we need to take into account the

1
llvm/lib/Target/R600/R600ISelLowering.h
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@ -56,7 +56,6 @@ private:
SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;

46
llvm/test/CodeGen/R600/select.ll Normal file
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@ -0,0 +1,46 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
; Normally icmp + select is optimized to select_cc, when this happens the
; DAGLegalizer never sees the select and doesn't have a chance to leaglize it.
;
; In order to avoid the select_cc optimization, this test case calculates the
; condition for the select in a separate basic block.
; CHECK-LABEL: @select
; CHECK-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.X
; CHECK-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.X
; CHECK-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY
; CHECK-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY
; CHECK-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XYZW
; CHECK-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XYZW
define void @select (i32 addrspace(1)* %i32out, float addrspace(1)* %f32out,
<2 x i32> addrspace(1)* %v2i32out, <2 x float> addrspace(1)* %v2f32out,
<4 x i32> addrspace(1)* %v4i32out, <4 x float> addrspace(1)* %v4f32out,
i32 %cond) {
entry:
br label %for
body:
%inc = add i32 %i, 1
%br_cmp.i = icmp eq i1 %br_cmp, 0
br label %for
for:
%i = phi i32 [ %inc, %body], [ 0, %entry ]
%br_cmp = phi i1 [ %br_cmp.i, %body ], [ 0, %entry ]
%0 = icmp eq i32 %cond, %i
%1 = select i1 %br_cmp, i32 2, i32 3
%2 = select i1 %br_cmp, float 2.0 , float 5.0
%3 = select i1 %br_cmp, <2 x i32> <i32 2, i32 3>, <2 x i32> <i32 4, i32 5>
%4 = select i1 %br_cmp, <2 x float> <float 2.0, float 3.0>, <2 x float> <float 4.0, float 5.0>
%5 = select i1 %br_cmp, <4 x i32> <i32 2 , i32 3, i32 4, i32 5>, <4 x i32> <i32 6, i32 7, i32 8, i32 9>
%6 = select i1 %br_cmp, <4 x float> <float 2.0, float 3.0, float 4.0, float 5.0>, <4 x float> <float 6.0, float 7.0, float 8.0, float 9.0>
br i1 %0, label %body, label %done
done:
store i32 %1, i32 addrspace(1)* %i32out
store float %2, float addrspace(1)* %f32out
store <2 x i32> %3, <2 x i32> addrspace(1)* %v2i32out
store <2 x float> %4, <2 x float> addrspace(1)* %v2f32out
store <4 x i32> %5, <4 x i32> addrspace(1)* %v4i32out
store <4 x float> %6, <4 x float> addrspace(1)* %v4f32out
ret void
}