forked from OSchip/llvm-project
AMDGPU: Fold fneg into round instructions
llvm-svn: 293127
This commit is contained in:
Matt Arsenault
parent
c38a74d886
commit
53f0cc238c
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@ -492,6 +492,9 @@ static bool fnegFoldsIntoOp(unsigned Opc) {
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case ISD::FMA:
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case ISD::FMAD:
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case ISD::FSIN:
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case ISD::FTRUNC:
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case ISD::FRINT:
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case ISD::FNEARBYINT:
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case AMDGPUISD::RCP:
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case AMDGPUISD::RCP_LEGACY:
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case AMDGPUISD::SIN_HW:
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@ -2924,9 +2927,12 @@ SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N,
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return Res;
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}
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case ISD::FP_EXTEND:
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case ISD::FTRUNC:
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case ISD::FRINT:
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case ISD::FNEARBYINT: // XXX - Should fround be handled?
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case ISD::FSIN:
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case AMDGPUISD::RCP:
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case AMDGPUISD::RCP_LEGACY:
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case ISD::FSIN:
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case AMDGPUISD::SIN_HW: {
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SDValue CvtSrc = N0.getOperand(0);
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if (CvtSrc.getOpcode() == ISD::FNEG) {
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@ -1327,7 +1327,91 @@ define void @v_fneg_amdgcn_sin_f32(float addrspace(1)* %out, float addrspace(1)*
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%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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%a = load volatile float, float addrspace(1)* %a.gep
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%sin = call float @llvm.amdgcn.sin.f32(float %a)
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%fneg = fsub float -0.000000e+00, %sin
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%fneg = fsub float -0.0, %sin
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store float %fneg, float addrspace(1)* %out.gep
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ret void
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}
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; --------------------------------------------------------------------------------
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; ftrunc tests
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; --------------------------------------------------------------------------------
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; GCN-LABEL: {{^}}v_fneg_trunc_f32:
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; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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; GCN: v_trunc_f32_e64 [[RESULT:v[0-9]+]], -[[A]]
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; GCN: buffer_store_dword [[RESULT]]
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define void @v_fneg_trunc_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
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%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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%a = load volatile float, float addrspace(1)* %a.gep
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%trunc = call float @llvm.trunc.f32(float %a)
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%fneg = fsub float -0.0, %trunc
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store float %fneg, float addrspace(1)* %out.gep
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ret void
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}
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; --------------------------------------------------------------------------------
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; fround tests
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; --------------------------------------------------------------------------------
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; GCN-LABEL: {{^}}v_fneg_round_f32:
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; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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; GCN: v_trunc_f32_e32
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; GCN: v_subrev_f32_e32
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; GCN: v_cndmask_b32
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; GCN-NSZ: v_sub_f32_e64 [[RESULT:v[0-9]+]], -v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-SAFE: v_xor_b32_e32 [[RESULT:v[0-9]+]], 0x80000000, v{{[0-9]+}}
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; GCN: buffer_store_dword [[RESULT]]
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define void @v_fneg_round_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
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%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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%a = load volatile float, float addrspace(1)* %a.gep
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%round = call float @llvm.round.f32(float %a)
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%fneg = fsub float -0.0, %round
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store float %fneg, float addrspace(1)* %out.gep
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ret void
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}
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; --------------------------------------------------------------------------------
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; rint tests
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; --------------------------------------------------------------------------------
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; GCN-LABEL: {{^}}v_fneg_rint_f32:
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; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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; GCN: v_rndne_f32_e64 [[RESULT:v[0-9]+]], -[[A]]
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; GCN: buffer_store_dword [[RESULT]]
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define void @v_fneg_rint_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
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%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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%a = load volatile float, float addrspace(1)* %a.gep
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%rint = call float @llvm.rint.f32(float %a)
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%fneg = fsub float -0.0, %rint
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store float %fneg, float addrspace(1)* %out.gep
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ret void
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}
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; --------------------------------------------------------------------------------
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; nearbyint tests
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; --------------------------------------------------------------------------------
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; GCN-LABEL: {{^}}v_fneg_nearbyint_f32:
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; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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; GCN: v_rndne_f32_e64 [[RESULT:v[0-9]+]], -[[A]]
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; GCN: buffer_store_dword [[RESULT]]
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define void @v_fneg_nearbyint_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
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%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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%a = load volatile float, float addrspace(1)* %a.gep
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%nearbyint = call float @llvm.nearbyint.f32(float %a)
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%fneg = fsub float -0.0, %nearbyint
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store float %fneg, float addrspace(1)* %out.gep
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ret void
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}
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@ -1336,6 +1420,10 @@ declare i32 @llvm.amdgcn.workitem.id.x() #1
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declare float @llvm.fma.f32(float, float, float) #1
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declare float @llvm.fmuladd.f32(float, float, float) #1
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declare float @llvm.sin.f32(float) #1
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declare float @llvm.trunc.f32(float) #1
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declare float @llvm.round.f32(float) #1
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declare float @llvm.rint.f32(float) #1
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declare float @llvm.nearbyint.f32(float) #1
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declare float @llvm.amdgcn.sin.f32(float) #1
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declare float @llvm.amdgcn.rcp.f32(float) #1
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@ -1,6 +1,6 @@
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; RUN: llc -march=amdgcn -enable-misched < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -enable-misched < %s | FileCheck -check-prefix=CI -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -enable-misched < %s | FileCheck -check-prefix=CI -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=GCN -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}frem_f32:
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; GCN-DAG: buffer_load_dword [[X:v[0-9]+]], {{.*$}}
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@ -12,8 +12,8 @@
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; GCN: v_mul_f32_e32
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; GCN: v_div_fmas_f32
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; GCN: v_div_fixup_f32
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; GCN: v_trunc_f32_e32
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; GCN: v_mad_f32
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; GCN: v_trunc_f32_e64 v{{[0-9]+}}, -v{{[0-9]+}}
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; GCN: v_mac_f32_e32
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; GCN: s_endpgm
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define void @frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
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float addrspace(1)* %in2) #0 {
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@ -28,11 +28,11 @@ define void @frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
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; FUNC-LABEL: {{^}}unsafe_frem_f32:
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; GCN: buffer_load_dword [[Y:v[0-9]+]], {{.*}} offset:16
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; GCN: buffer_load_dword [[X:v[0-9]+]], {{.*}}
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; GCN: v_rcp_f32_e32 [[INVY:v[0-9]+]], [[Y]]
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; GCN: v_rcp_f32_e64 [[INVY:v[0-9]+]], -[[Y]]
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; GCN: v_mul_f32_e32 [[DIV:v[0-9]+]], [[INVY]], [[X]]
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; GCN: v_trunc_f32_e32 [[TRUNC:v[0-9]+]], [[DIV]]
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; GCN: v_mad_f32 [[RESULT:v[0-9]+]], -[[TRUNC]], [[Y]], [[X]]
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; GCN: buffer_store_dword [[RESULT]]
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; GCN: v_mac_f32_e32 [[X]], [[Y]], [[TRUNC]]
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; GCN: buffer_store_dword [[X]]
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; GCN: s_endpgm
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define void @unsafe_frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
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float addrspace(1)* %in2) #1 {
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@ -46,8 +46,8 @@ entry:
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; GCN-LABEL: {{^}}class_f16_fneg
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; GCN: s_load_dword s[[SA_F16:[0-9]+]]
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; GCN: s_load_dword s[[SB_I32:[0-9]+]]
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; VI: v_trunc_f16_e32 v[[VA_F16:[0-9]+]], s[[SA_F16]]
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; VI: v_cmp_class_f16_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], -v[[VA_F16]], s[[SB_I32]]
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; VI: v_trunc_f16_e64 v[[VA_F16:[0-9]+]], -s[[SA_F16]]
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; VI: v_cmp_class_f16_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], v[[VA_F16]], s[[SB_I32]]
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; VI: v_cndmask_b32_e64 v[[VR_I32:[0-9]+]], 0, -1, [[CMP]]
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; GCN: buffer_store_dword v[[VR_I32]]
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; GCN: s_endpgm
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