forked from OSchip/llvm-project
[CostModel][X86] Add realistic vXi64 uitofp vXf64 costs
Match codegen improvements from D53649/rL345256 llvm-svn: 345263
This commit is contained in:
Simon Pilgrim
parent
74d4931da2
commit
53e8e145e9
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@ -1264,8 +1264,6 @@ int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
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{ ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 },
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{ ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 },
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{ ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 },
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{ ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 },
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{ ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 26 },
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{ ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 },
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{ ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 },
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@ -1287,9 +1285,10 @@ int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
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{ ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 },
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{ ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 },
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{ ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 },
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{ ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 },
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 },
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{ ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 12 },
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{ ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 26 },
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{ ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 },
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{ ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 },
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{ ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 },
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@ -1387,13 +1386,13 @@ int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
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{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 },
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{ ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 },
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{ ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 },
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 },
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{ ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 },
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// The generic code to compute the scalar overhead is currently broken.
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// Workaround this limitation by estimating the scalarization overhead
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// here. We have roughly 10 instructions per scalar element.
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// Multiply that by the vector width.
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// FIXME: remove that when PR19268 is fixed.
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 10 },
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{ ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 20 },
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{ ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 },
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{ ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 },
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@ -1468,7 +1467,7 @@ int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
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{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 },
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 6 },
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{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
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{ ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 3 },
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@ -13,7 +13,7 @@
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define i32 @uitofp_i8_double() {
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; SSE-LABEL: 'uitofp_i8_double'
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; SSE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %cvt_i8_f64 = uitofp i8 undef to double
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; SSE-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %cvt_v2i8_v2f64 = uitofp <2 x i8> undef to <2 x double>
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; SSE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %cvt_v2i8_v2f64 = uitofp <2 x i8> undef to <2 x double>
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; SSE-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %cvt_v4i8_v4f64 = uitofp <4 x i8> undef to <4 x double>
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; SSE-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %cvt_v8i8_v8f64 = uitofp <8 x i8> undef to <8 x double>
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; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
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@ -49,7 +49,7 @@ define i32 @uitofp_i8_double() {
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define i32 @uitofp_i16_double() {
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; SSE-LABEL: 'uitofp_i16_double'
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; SSE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %cvt_i16_f64 = uitofp i16 undef to double
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; SSE-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %cvt_v2i16_v2f64 = uitofp <2 x i16> undef to <2 x double>
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; SSE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %cvt_v2i16_v2f64 = uitofp <2 x i16> undef to <2 x double>
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; SSE-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %cvt_v4i16_v4f64 = uitofp <4 x i16> undef to <4 x double>
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; SSE-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %cvt_v8i16_v8f64 = uitofp <8 x i16> undef to <8 x double>
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; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
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@ -85,7 +85,7 @@ define i32 @uitofp_i16_double() {
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define i32 @uitofp_i32_double() {
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; SSE-LABEL: 'uitofp_i32_double'
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; SSE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %cvt_i32_f64 = uitofp i32 undef to double
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; SSE-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %cvt_v2i32_v2f64 = uitofp <2 x i32> undef to <2 x double>
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; SSE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %cvt_v2i32_v2f64 = uitofp <2 x i32> undef to <2 x double>
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; SSE-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %cvt_v4i32_v4f64 = uitofp <4 x i32> undef to <4 x double>
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; SSE-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %cvt_v8i32_v8f64 = uitofp <8 x i32> undef to <8 x double>
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; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
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@ -121,23 +121,23 @@ define i32 @uitofp_i32_double() {
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define i32 @uitofp_i64_double() {
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; SSE-LABEL: 'uitofp_i64_double'
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; SSE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %cvt_i64_f64 = uitofp i64 undef to double
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; SSE-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %cvt_v2i64_v2f64 = uitofp <2 x i64> undef to <2 x double>
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; SSE-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %cvt_v4i64_v4f64 = uitofp <4 x i64> undef to <4 x double>
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; SSE-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %cvt_v8i64_v8f64 = uitofp <8 x i64> undef to <8 x double>
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; SSE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %cvt_v2i64_v2f64 = uitofp <2 x i64> undef to <2 x double>
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; SSE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %cvt_v4i64_v4f64 = uitofp <4 x i64> undef to <4 x double>
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; SSE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %cvt_v8i64_v8f64 = uitofp <8 x i64> undef to <8 x double>
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; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
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;
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; AVX-LABEL: 'uitofp_i64_double'
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; AVX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %cvt_i64_f64 = uitofp i64 undef to double
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; AVX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %cvt_v2i64_v2f64 = uitofp <2 x i64> undef to <2 x double>
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; AVX-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %cvt_v4i64_v4f64 = uitofp <4 x i64> undef to <4 x double>
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; AVX-NEXT: Cost Model: Found an estimated cost of 41 for instruction: %cvt_v8i64_v8f64 = uitofp <8 x i64> undef to <8 x double>
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; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %cvt_v2i64_v2f64 = uitofp <2 x i64> undef to <2 x double>
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; AVX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %cvt_v4i64_v4f64 = uitofp <4 x i64> undef to <4 x double>
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; AVX-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %cvt_v8i64_v8f64 = uitofp <8 x i64> undef to <8 x double>
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; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
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;
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; AVX512F-LABEL: 'uitofp_i64_double'
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; AVX512F-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %cvt_i64_f64 = uitofp i64 undef to double
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; AVX512F-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %cvt_v2i64_v2f64 = uitofp <2 x i64> undef to <2 x double>
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; AVX512F-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %cvt_v4i64_v4f64 = uitofp <4 x i64> undef to <4 x double>
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; AVX512F-NEXT: Cost Model: Found an estimated cost of 26 for instruction: %cvt_v8i64_v8f64 = uitofp <8 x i64> undef to <8 x double>
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; AVX512F-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %cvt_v4i64_v4f64 = uitofp <4 x i64> undef to <4 x double>
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; AVX512F-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %cvt_v8i64_v8f64 = uitofp <8 x i64> undef to <8 x double>
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; AVX512F-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
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;
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; AVX512DQ-LABEL: 'uitofp_i64_double'
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@ -149,9 +149,9 @@ define i32 @uitofp_i64_double() {
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;
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; BTVER2-LABEL: 'uitofp_i64_double'
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; BTVER2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %cvt_i64_f64 = uitofp i64 undef to double
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; BTVER2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %cvt_v2i64_v2f64 = uitofp <2 x i64> undef to <2 x double>
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; BTVER2-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %cvt_v4i64_v4f64 = uitofp <4 x i64> undef to <4 x double>
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; BTVER2-NEXT: Cost Model: Found an estimated cost of 41 for instruction: %cvt_v8i64_v8f64 = uitofp <8 x i64> undef to <8 x double>
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; BTVER2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %cvt_v2i64_v2f64 = uitofp <2 x i64> undef to <2 x double>
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; BTVER2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %cvt_v4i64_v4f64 = uitofp <4 x i64> undef to <4 x double>
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; BTVER2-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %cvt_v8i64_v8f64 = uitofp <8 x i64> undef to <8 x double>
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; BTVER2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
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;
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%cvt_i64_f64 = uitofp i64 undef to double
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@ -5,8 +5,9 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
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target triple = "x86_64-apple-macosx10.8.0"
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; CHECK: cost of 10 for VF 2 For instruction: %conv = uitofp i64 %tmp to double
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; CHECK: cost of 20 for VF 4 For instruction: %conv = uitofp i64 %tmp to double
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; CHECK: cost of 4 for VF 1 For instruction: %conv = uitofp i64 %tmp to double
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; CHECK: cost of 5 for VF 2 For instruction: %conv = uitofp i64 %tmp to double
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; CHECK: cost of 6 for VF 4 For instruction: %conv = uitofp i64 %tmp to double
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define void @uint64_to_double_cost(i64* noalias nocapture %a, double* noalias nocapture readonly %b) nounwind {
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entry:
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br label %for.body
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@ -1,8 +1,8 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -mtriple=x86_64-unknown -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
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; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256 --check-prefix=AVX1
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; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256 --check-prefix=XOP
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; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256 --check-prefix=AVX2
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; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
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; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
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; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
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; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX512
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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@ -20,29 +20,11 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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;
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define void @uitofp_2i64_2f64() #0 {
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; SSE-LABEL: @uitofp_2i64_2f64(
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; SSE-NEXT: [[LD0:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 0), align 64
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; SSE-NEXT: [[LD1:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 1), align 8
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; SSE-NEXT: [[CVT0:%.*]] = uitofp i64 [[LD0]] to double
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; SSE-NEXT: [[CVT1:%.*]] = uitofp i64 [[LD1]] to double
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; SSE-NEXT: store double [[CVT0]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
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; SSE-NEXT: store double [[CVT1]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
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; SSE-NEXT: ret void
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;
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; AVX256-LABEL: @uitofp_2i64_2f64(
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; AVX256-NEXT: [[LD0:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 0), align 64
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; AVX256-NEXT: [[LD1:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 1), align 8
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; AVX256-NEXT: [[CVT0:%.*]] = uitofp i64 [[LD0]] to double
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; AVX256-NEXT: [[CVT1:%.*]] = uitofp i64 [[LD1]] to double
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; AVX256-NEXT: store double [[CVT0]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
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; AVX256-NEXT: store double [[CVT1]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
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; AVX256-NEXT: ret void
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;
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; AVX512-LABEL: @uitofp_2i64_2f64(
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; AVX512-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([8 x i64]* @src64 to <2 x i64>*), align 64
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; AVX512-NEXT: [[TMP2:%.*]] = uitofp <2 x i64> [[TMP1]] to <2 x double>
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; AVX512-NEXT: store <2 x double> [[TMP2]], <2 x double>* bitcast ([8 x double]* @dst64 to <2 x double>*), align 64
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; AVX512-NEXT: ret void
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; CHECK-LABEL: @uitofp_2i64_2f64(
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; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([8 x i64]* @src64 to <2 x i64>*), align 64
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; CHECK-NEXT: [[TMP2:%.*]] = uitofp <2 x i64> [[TMP1]] to <2 x double>
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; CHECK-NEXT: store <2 x double> [[TMP2]], <2 x double>* bitcast ([8 x double]* @dst64 to <2 x double>*), align 64
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; CHECK-NEXT: ret void
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;
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%ld0 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 0), align 64
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%ld1 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 1), align 8
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@ -55,52 +37,19 @@ define void @uitofp_2i64_2f64() #0 {
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define void @uitofp_4i64_4f64() #0 {
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; SSE-LABEL: @uitofp_4i64_4f64(
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; SSE-NEXT: [[LD0:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 0), align 64
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; SSE-NEXT: [[LD1:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 1), align 8
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; SSE-NEXT: [[LD2:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 2), align 16
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; SSE-NEXT: [[LD3:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 3), align 8
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; SSE-NEXT: [[CVT0:%.*]] = uitofp i64 [[LD0]] to double
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; SSE-NEXT: [[CVT1:%.*]] = uitofp i64 [[LD1]] to double
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; SSE-NEXT: [[CVT2:%.*]] = uitofp i64 [[LD2]] to double
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; SSE-NEXT: [[CVT3:%.*]] = uitofp i64 [[LD3]] to double
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; SSE-NEXT: store double [[CVT0]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
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; SSE-NEXT: store double [[CVT1]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
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; SSE-NEXT: store double [[CVT2]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 2), align 16
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; SSE-NEXT: store double [[CVT3]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 3), align 8
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; SSE-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([8 x i64]* @src64 to <2 x i64>*), align 64
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; SSE-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 2) to <2 x i64>*), align 16
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; SSE-NEXT: [[TMP3:%.*]] = uitofp <2 x i64> [[TMP1]] to <2 x double>
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; SSE-NEXT: [[TMP4:%.*]] = uitofp <2 x i64> [[TMP2]] to <2 x double>
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; SSE-NEXT: store <2 x double> [[TMP3]], <2 x double>* bitcast ([8 x double]* @dst64 to <2 x double>*), align 64
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; SSE-NEXT: store <2 x double> [[TMP4]], <2 x double>* bitcast (double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 2) to <2 x double>*), align 16
|
||||
; SSE-NEXT: ret void
|
||||
;
|
||||
; AVX1-LABEL: @uitofp_4i64_4f64(
|
||||
; AVX1-NEXT: [[LD0:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 0), align 64
|
||||
; AVX1-NEXT: [[LD1:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 1), align 8
|
||||
; AVX1-NEXT: [[LD2:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 2), align 16
|
||||
; AVX1-NEXT: [[LD3:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 3), align 8
|
||||
; AVX1-NEXT: [[CVT0:%.*]] = uitofp i64 [[LD0]] to double
|
||||
; AVX1-NEXT: [[CVT1:%.*]] = uitofp i64 [[LD1]] to double
|
||||
; AVX1-NEXT: [[CVT2:%.*]] = uitofp i64 [[LD2]] to double
|
||||
; AVX1-NEXT: [[CVT3:%.*]] = uitofp i64 [[LD3]] to double
|
||||
; AVX1-NEXT: store double [[CVT0]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
|
||||
; AVX1-NEXT: store double [[CVT1]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
|
||||
; AVX1-NEXT: store double [[CVT2]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 2), align 16
|
||||
; AVX1-NEXT: store double [[CVT3]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 3), align 8
|
||||
; AVX1-NEXT: ret void
|
||||
;
|
||||
; XOP-LABEL: @uitofp_4i64_4f64(
|
||||
; XOP-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([8 x i64]* @src64 to <4 x i64>*), align 64
|
||||
; XOP-NEXT: [[TMP2:%.*]] = uitofp <4 x i64> [[TMP1]] to <4 x double>
|
||||
; XOP-NEXT: store <4 x double> [[TMP2]], <4 x double>* bitcast ([8 x double]* @dst64 to <4 x double>*), align 64
|
||||
; XOP-NEXT: ret void
|
||||
;
|
||||
; AVX2-LABEL: @uitofp_4i64_4f64(
|
||||
; AVX2-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([8 x i64]* @src64 to <4 x i64>*), align 64
|
||||
; AVX2-NEXT: [[TMP2:%.*]] = uitofp <4 x i64> [[TMP1]] to <4 x double>
|
||||
; AVX2-NEXT: store <4 x double> [[TMP2]], <4 x double>* bitcast ([8 x double]* @dst64 to <4 x double>*), align 64
|
||||
; AVX2-NEXT: ret void
|
||||
;
|
||||
; AVX512-LABEL: @uitofp_4i64_4f64(
|
||||
; AVX512-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([8 x i64]* @src64 to <4 x i64>*), align 64
|
||||
; AVX512-NEXT: [[TMP2:%.*]] = uitofp <4 x i64> [[TMP1]] to <4 x double>
|
||||
; AVX512-NEXT: store <4 x double> [[TMP2]], <4 x double>* bitcast ([8 x double]* @dst64 to <4 x double>*), align 64
|
||||
; AVX512-NEXT: ret void
|
||||
; AVX-LABEL: @uitofp_4i64_4f64(
|
||||
; AVX-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([8 x i64]* @src64 to <4 x i64>*), align 64
|
||||
; AVX-NEXT: [[TMP2:%.*]] = uitofp <4 x i64> [[TMP1]] to <4 x double>
|
||||
; AVX-NEXT: store <4 x double> [[TMP2]], <4 x double>* bitcast ([8 x double]* @dst64 to <4 x double>*), align 64
|
||||
; AVX-NEXT: ret void
|
||||
;
|
||||
%ld0 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 0), align 64
|
||||
%ld1 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 1), align 8
|
||||
|
|
@ -119,76 +68,28 @@ define void @uitofp_4i64_4f64() #0 {
|
|||
|
||||
define void @uitofp_8i64_8f64() #0 {
|
||||
; SSE-LABEL: @uitofp_8i64_8f64(
|
||||
; SSE-NEXT: [[LD0:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 0), align 64
|
||||
; SSE-NEXT: [[LD1:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 1), align 8
|
||||
; SSE-NEXT: [[LD2:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 2), align 16
|
||||
; SSE-NEXT: [[LD3:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 3), align 8
|
||||
; SSE-NEXT: [[LD4:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 4), align 32
|
||||
; SSE-NEXT: [[LD5:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 5), align 8
|
||||
; SSE-NEXT: [[LD6:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 6), align 16
|
||||
; SSE-NEXT: [[LD7:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 7), align 8
|
||||
; SSE-NEXT: [[CVT0:%.*]] = uitofp i64 [[LD0]] to double
|
||||
; SSE-NEXT: [[CVT1:%.*]] = uitofp i64 [[LD1]] to double
|
||||
; SSE-NEXT: [[CVT2:%.*]] = uitofp i64 [[LD2]] to double
|
||||
; SSE-NEXT: [[CVT3:%.*]] = uitofp i64 [[LD3]] to double
|
||||
; SSE-NEXT: [[CVT4:%.*]] = uitofp i64 [[LD4]] to double
|
||||
; SSE-NEXT: [[CVT5:%.*]] = uitofp i64 [[LD5]] to double
|
||||
; SSE-NEXT: [[CVT6:%.*]] = uitofp i64 [[LD6]] to double
|
||||
; SSE-NEXT: [[CVT7:%.*]] = uitofp i64 [[LD7]] to double
|
||||
; SSE-NEXT: store double [[CVT0]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
|
||||
; SSE-NEXT: store double [[CVT1]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
|
||||
; SSE-NEXT: store double [[CVT2]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 2), align 16
|
||||
; SSE-NEXT: store double [[CVT3]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 3), align 8
|
||||
; SSE-NEXT: store double [[CVT4]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 4), align 32
|
||||
; SSE-NEXT: store double [[CVT5]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 5), align 8
|
||||
; SSE-NEXT: store double [[CVT6]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 6), align 16
|
||||
; SSE-NEXT: store double [[CVT7]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 7), align 8
|
||||
; SSE-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([8 x i64]* @src64 to <2 x i64>*), align 64
|
||||
; SSE-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 2) to <2 x i64>*), align 16
|
||||
; SSE-NEXT: [[TMP3:%.*]] = load <2 x i64>, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 4) to <2 x i64>*), align 32
|
||||
; SSE-NEXT: [[TMP4:%.*]] = load <2 x i64>, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 6) to <2 x i64>*), align 16
|
||||
; SSE-NEXT: [[TMP5:%.*]] = uitofp <2 x i64> [[TMP1]] to <2 x double>
|
||||
; SSE-NEXT: [[TMP6:%.*]] = uitofp <2 x i64> [[TMP2]] to <2 x double>
|
||||
; SSE-NEXT: [[TMP7:%.*]] = uitofp <2 x i64> [[TMP3]] to <2 x double>
|
||||
; SSE-NEXT: [[TMP8:%.*]] = uitofp <2 x i64> [[TMP4]] to <2 x double>
|
||||
; SSE-NEXT: store <2 x double> [[TMP5]], <2 x double>* bitcast ([8 x double]* @dst64 to <2 x double>*), align 64
|
||||
; SSE-NEXT: store <2 x double> [[TMP6]], <2 x double>* bitcast (double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 2) to <2 x double>*), align 16
|
||||
; SSE-NEXT: store <2 x double> [[TMP7]], <2 x double>* bitcast (double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 4) to <2 x double>*), align 32
|
||||
; SSE-NEXT: store <2 x double> [[TMP8]], <2 x double>* bitcast (double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 6) to <2 x double>*), align 16
|
||||
; SSE-NEXT: ret void
|
||||
;
|
||||
; AVX1-LABEL: @uitofp_8i64_8f64(
|
||||
; AVX1-NEXT: [[LD0:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 0), align 64
|
||||
; AVX1-NEXT: [[LD1:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 1), align 8
|
||||
; AVX1-NEXT: [[LD2:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 2), align 16
|
||||
; AVX1-NEXT: [[LD3:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 3), align 8
|
||||
; AVX1-NEXT: [[LD4:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 4), align 32
|
||||
; AVX1-NEXT: [[LD5:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 5), align 8
|
||||
; AVX1-NEXT: [[LD6:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 6), align 16
|
||||
; AVX1-NEXT: [[LD7:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 7), align 8
|
||||
; AVX1-NEXT: [[CVT0:%.*]] = uitofp i64 [[LD0]] to double
|
||||
; AVX1-NEXT: [[CVT1:%.*]] = uitofp i64 [[LD1]] to double
|
||||
; AVX1-NEXT: [[CVT2:%.*]] = uitofp i64 [[LD2]] to double
|
||||
; AVX1-NEXT: [[CVT3:%.*]] = uitofp i64 [[LD3]] to double
|
||||
; AVX1-NEXT: [[CVT4:%.*]] = uitofp i64 [[LD4]] to double
|
||||
; AVX1-NEXT: [[CVT5:%.*]] = uitofp i64 [[LD5]] to double
|
||||
; AVX1-NEXT: [[CVT6:%.*]] = uitofp i64 [[LD6]] to double
|
||||
; AVX1-NEXT: [[CVT7:%.*]] = uitofp i64 [[LD7]] to double
|
||||
; AVX1-NEXT: store double [[CVT0]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
|
||||
; AVX1-NEXT: store double [[CVT1]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
|
||||
; AVX1-NEXT: store double [[CVT2]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 2), align 16
|
||||
; AVX1-NEXT: store double [[CVT3]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 3), align 8
|
||||
; AVX1-NEXT: store double [[CVT4]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 4), align 32
|
||||
; AVX1-NEXT: store double [[CVT5]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 5), align 8
|
||||
; AVX1-NEXT: store double [[CVT6]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 6), align 16
|
||||
; AVX1-NEXT: store double [[CVT7]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 7), align 8
|
||||
; AVX1-NEXT: ret void
|
||||
;
|
||||
; XOP-LABEL: @uitofp_8i64_8f64(
|
||||
; XOP-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([8 x i64]* @src64 to <4 x i64>*), align 64
|
||||
; XOP-NEXT: [[TMP2:%.*]] = load <4 x i64>, <4 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 4) to <4 x i64>*), align 32
|
||||
; XOP-NEXT: [[TMP3:%.*]] = uitofp <4 x i64> [[TMP1]] to <4 x double>
|
||||
; XOP-NEXT: [[TMP4:%.*]] = uitofp <4 x i64> [[TMP2]] to <4 x double>
|
||||
; XOP-NEXT: store <4 x double> [[TMP3]], <4 x double>* bitcast ([8 x double]* @dst64 to <4 x double>*), align 64
|
||||
; XOP-NEXT: store <4 x double> [[TMP4]], <4 x double>* bitcast (double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 4) to <4 x double>*), align 32
|
||||
; XOP-NEXT: ret void
|
||||
;
|
||||
; AVX2-LABEL: @uitofp_8i64_8f64(
|
||||
; AVX2-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([8 x i64]* @src64 to <4 x i64>*), align 64
|
||||
; AVX2-NEXT: [[TMP2:%.*]] = load <4 x i64>, <4 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 4) to <4 x i64>*), align 32
|
||||
; AVX2-NEXT: [[TMP3:%.*]] = uitofp <4 x i64> [[TMP1]] to <4 x double>
|
||||
; AVX2-NEXT: [[TMP4:%.*]] = uitofp <4 x i64> [[TMP2]] to <4 x double>
|
||||
; AVX2-NEXT: store <4 x double> [[TMP3]], <4 x double>* bitcast ([8 x double]* @dst64 to <4 x double>*), align 64
|
||||
; AVX2-NEXT: store <4 x double> [[TMP4]], <4 x double>* bitcast (double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 4) to <4 x double>*), align 32
|
||||
; AVX2-NEXT: ret void
|
||||
; AVX256-LABEL: @uitofp_8i64_8f64(
|
||||
; AVX256-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([8 x i64]* @src64 to <4 x i64>*), align 64
|
||||
; AVX256-NEXT: [[TMP2:%.*]] = load <4 x i64>, <4 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 4) to <4 x i64>*), align 32
|
||||
; AVX256-NEXT: [[TMP3:%.*]] = uitofp <4 x i64> [[TMP1]] to <4 x double>
|
||||
; AVX256-NEXT: [[TMP4:%.*]] = uitofp <4 x i64> [[TMP2]] to <4 x double>
|
||||
; AVX256-NEXT: store <4 x double> [[TMP3]], <4 x double>* bitcast ([8 x double]* @dst64 to <4 x double>*), align 64
|
||||
; AVX256-NEXT: store <4 x double> [[TMP4]], <4 x double>* bitcast (double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 4) to <4 x double>*), align 32
|
||||
; AVX256-NEXT: ret void
|
||||
;
|
||||
; AVX512-LABEL: @uitofp_8i64_8f64(
|
||||
; AVX512-NEXT: [[TMP1:%.*]] = load <8 x i64>, <8 x i64>* bitcast ([8 x i64]* @src64 to <8 x i64>*), align 64
|
||||
|
|
|
|||
Loading…
Reference in New Issue