forked from OSchip/llvm-project
[AArch64] Create proper memoperand for multi-vector stores
Include all of the store's source vector operands when creating the MachineMemOperand. Previously, we were missing the first operand, making the store size seem smaller than it really is. Differential Revision: https://reviews.llvm.org/D52816 llvm-svn: 345315
This commit is contained in:
David Greene
parent
117b1fa19a
commit
53e869da7d
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@ -7972,7 +7972,7 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
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Info.opc = ISD::INTRINSIC_VOID;
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// Conservatively set memVT to the entire set of vectors stored.
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unsigned NumElts = 0;
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for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
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for (unsigned ArgI = 0, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
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Type *ArgTy = I.getArgOperand(ArgI)->getType();
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if (!ArgTy->isVectorTy())
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break;
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@ -0,0 +1,164 @@
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; RUN: llc -mtriple=aarch64-linux-gnu -stop-after=isel < %s | FileCheck %s
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declare void @llvm.aarch64.neon.st2.v4f32.p0f32(<4 x float>, <4 x float>, float*)
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declare void @llvm.aarch64.neon.st3.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, float*)
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declare void @llvm.aarch64.neon.st4.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, <4 x float>, float*)
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declare void @llvm.aarch64.neon.st1x2.v4f32.p0f32(<4 x float>, <4 x float>, float*)
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declare void @llvm.aarch64.neon.st1x3.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, float*)
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declare void @llvm.aarch64.neon.st1x4.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, <4 x float>, float*)
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declare void @llvm.aarch64.neon.st2lane.v4f32.p0f32(<4 x float>, <4 x float>, i64, float*)
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declare void @llvm.aarch64.neon.st3lane.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, i64, float*)
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declare void @llvm.aarch64.neon.st4lane.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, <4 x float>, i64, float*)
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define void @addstx(float* %res, <4 x float>* %a, <4 x float>* %b, <4 x float>* %c, <4 x float>* %d) {
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%al = load <4 x float>, <4 x float>* %a
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%bl = load <4 x float>, <4 x float>* %b
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%cl = load <4 x float>, <4 x float>* %c
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%dl = load <4 x float>, <4 x float>* %d
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%ar = fadd <4 x float> %al, %bl
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%br = fadd <4 x float> %bl, %cl
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%cr = fadd <4 x float> %cl, %dl
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%dr = fadd <4 x float> %dl, %al
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; The sizes below are conservative. AArch64TargetLowering
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; conservatively assumes the entire vector is stored.
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tail call void @llvm.aarch64.neon.st2.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, float* %res)
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; CHECK: ST2Twov4s {{.*}} :: (store 32 {{.*}})
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tail call void @llvm.aarch64.neon.st3.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, float* %res)
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; CHECK: ST3Threev4s {{.*}} :: (store 48 {{.*}})
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tail call void @llvm.aarch64.neon.st4.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, <4 x float> %dr, float* %res)
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; CHECK: ST4Fourv4s {{.*}} :: (store 64 {{.*}})
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ret void
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}
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define void @addst1x(float* %res, <4 x float>* %a, <4 x float>* %b, <4 x float>* %c, <4 x float>* %d) {
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%al = load <4 x float>, <4 x float>* %a
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%bl = load <4 x float>, <4 x float>* %b
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%cl = load <4 x float>, <4 x float>* %c
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%dl = load <4 x float>, <4 x float>* %d
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%ar = fadd <4 x float> %al, %bl
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%br = fadd <4 x float> %bl, %cl
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%cr = fadd <4 x float> %cl, %dl
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%dr = fadd <4 x float> %dl, %al
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; The sizes below are conservative. AArch64TargetLowering
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; conservatively assumes the entire vector is stored.
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tail call void @llvm.aarch64.neon.st1x2.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, float* %res)
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; CHECK: ST1Twov4s {{.*}} :: (store 32 {{.*}})
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tail call void @llvm.aarch64.neon.st1x3.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, float* %res)
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; CHECK: ST1Threev4s {{.*}} :: (store 48 {{.*}})
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tail call void @llvm.aarch64.neon.st1x4.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, <4 x float> %dr, float* %res)
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; CHECK: ST1Fourv4s {{.*}} :: (store 64 {{.*}})
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ret void
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}
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define void @addstxlane(float* %res, <4 x float>* %a, <4 x float>* %b, <4 x float>* %c, <4 x float>* %d) {
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%al = load <4 x float>, <4 x float>* %a
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%bl = load <4 x float>, <4 x float>* %b
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%cl = load <4 x float>, <4 x float>* %c
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%dl = load <4 x float>, <4 x float>* %d
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%ar = fadd <4 x float> %al, %bl
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%br = fadd <4 x float> %bl, %cl
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%cr = fadd <4 x float> %cl, %dl
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%dr = fadd <4 x float> %dl, %al
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; The sizes below are conservative. AArch64TargetLowering
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; conservatively assumes the entire vector is stored.
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tail call void @llvm.aarch64.neon.st2lane.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, i64 1, float* %res)
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; CHECK: ST2i32 {{.*}} :: (store 32 {{.*}})
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tail call void @llvm.aarch64.neon.st3lane.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, i64 1, float* %res)
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; CHECK: ST3i32 {{.*}} :: (store 48 {{.*}})
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tail call void @llvm.aarch64.neon.st4lane.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, <4 x float> %dr, i64 1, float* %res)
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; CHECK: ST4i32 {{.*}} :: (store 64 {{.*}})
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ret void
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}
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; RUN: llc -mtriple=aarch64-linux-gnu -stop-after=isel < %s | FileCheck %s
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declare void @llvm.aarch64.neon.st2.v4f32.p0f32(<4 x float>, <4 x float>, float*)
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declare void @llvm.aarch64.neon.st3.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, float*)
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declare void @llvm.aarch64.neon.st4.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, <4 x float>, float*)
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declare void @llvm.aarch64.neon.st1x2.v4f32.p0f32(<4 x float>, <4 x float>, float*)
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declare void @llvm.aarch64.neon.st1x3.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, float*)
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declare void @llvm.aarch64.neon.st1x4.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, <4 x float>, float*)
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declare void @llvm.aarch64.neon.st2lane.v4f32.p0f32(<4 x float>, <4 x float>, i64, float*)
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declare void @llvm.aarch64.neon.st3lane.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, i64, float*)
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declare void @llvm.aarch64.neon.st4lane.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, <4 x float>, i64, float*)
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define void @addstx(float* %res, <4 x float>* %a, <4 x float>* %b, <4 x float>* %c, <4 x float>* %d) {
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%al = load <4 x float>, <4 x float>* %a
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%bl = load <4 x float>, <4 x float>* %b
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%cl = load <4 x float>, <4 x float>* %c
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%dl = load <4 x float>, <4 x float>* %d
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%ar = fadd <4 x float> %al, %bl
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%br = fadd <4 x float> %bl, %cl
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%cr = fadd <4 x float> %cl, %dl
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%dr = fadd <4 x float> %dl, %al
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; The sizes below are conservative. AArch64TargetLowering
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; conservatively assumes the entiew vector is stored.
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tail call void @llvm.aarch64.neon.st2.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, float* %res)
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; CHECK: ST2Twov4s {{.*}} :: (store 32 {{.*}})
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tail call void @llvm.aarch64.neon.st3.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, float* %res)
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; CHECK: ST3Threev4s {{.*}} :: (store 48 {{.*}})
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tail call void @llvm.aarch64.neon.st4.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, <4 x float> %dr, float* %res)
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; CHECK: ST4Fourv4s {{.*}} :: (store 64 {{.*}})
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ret void
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}
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define void @addst1x(float* %res, <4 x float>* %a, <4 x float>* %b, <4 x float>* %c, <4 x float>* %d) {
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%al = load <4 x float>, <4 x float>* %a
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%bl = load <4 x float>, <4 x float>* %b
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%cl = load <4 x float>, <4 x float>* %c
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%dl = load <4 x float>, <4 x float>* %d
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%ar = fadd <4 x float> %al, %bl
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%br = fadd <4 x float> %bl, %cl
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%cr = fadd <4 x float> %cl, %dl
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%dr = fadd <4 x float> %dl, %al
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; The sizes below are conservative. AArch64TargetLowering
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; conservatively assumes the entiew vector is stored.
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tail call void @llvm.aarch64.neon.st1x2.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, float* %res)
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; CHECK: ST1Twov4s {{.*}} :: (store 32 {{.*}})
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tail call void @llvm.aarch64.neon.st1x3.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, float* %res)
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; CHECK: ST1Threev4s {{.*}} :: (store 48 {{.*}})
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tail call void @llvm.aarch64.neon.st1x4.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, <4 x float> %dr, float* %res)
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; CHECK: ST1Fourv4s {{.*}} :: (store 64 {{.*}})
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ret void
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}
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define void @addstxlane(float* %res, <4 x float>* %a, <4 x float>* %b, <4 x float>* %c, <4 x float>* %d) {
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%al = load <4 x float>, <4 x float>* %a
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%bl = load <4 x float>, <4 x float>* %b
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%cl = load <4 x float>, <4 x float>* %c
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%dl = load <4 x float>, <4 x float>* %d
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%ar = fadd <4 x float> %al, %bl
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%br = fadd <4 x float> %bl, %cl
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%cr = fadd <4 x float> %cl, %dl
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%dr = fadd <4 x float> %dl, %al
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; The sizes below are conservative. AArch64TargetLowering
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; conservatively assumes the entiew vector is stored.
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tail call void @llvm.aarch64.neon.st2lane.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, i64 1, float* %res)
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; CHECK: ST2i32 {{.*}} :: (store 32 {{.*}})
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tail call void @llvm.aarch64.neon.st3lane.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, i64 1, float* %res)
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; CHECK: ST3i32 {{.*}} :: (store 48 {{.*}})
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tail call void @llvm.aarch64.neon.st4lane.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, <4 x float> %dr, i64 1, float* %res)
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; CHECK: ST4i32 {{.*}} :: (store 64 {{.*}})
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ret void
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}
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