forked from OSchip/llvm-project
[RISCV] Remove unneeded !eq comparing a single bit value to 0/1 in RISCVInstrInfoVPseudos.td. NFC
Instead we can either use the bit directly. If it was checking for 0 we need to swap the operands or use !not.
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@ -543,7 +543,7 @@ class VPseudoBinaryCarryIn<VReg RetClass,
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bit CarryIn,
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string Constraint> :
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Pseudo<(outs RetClass:$rd),
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!if(!eq(CarryIn, 1),
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!if(CarryIn,
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(ins Op1Class:$rs2, Op2Class:$rs1, VMV0:$carry, GPR:$vl,
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ixlenimm:$sew),
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(ins Op1Class:$rs2, Op2Class:$rs1, GPR:$vl, ixlenimm:$sew)), []>,
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@ -554,8 +554,8 @@ class VPseudoBinaryCarryIn<VReg RetClass,
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let usesCustomInserter = 1;
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let Constraints = Constraint;
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let Uses = [VL, VTYPE];
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let VLIndex = !if(!eq(CarryIn, 1), 4, 3);
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let SEWIndex = !if(!eq(CarryIn, 1), 5, 4);
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let VLIndex = !if(CarryIn, 4, 3);
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let SEWIndex = !if(CarryIn, 5, 4);
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let MergeOpIndex = InvalidIndex.V;
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let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
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let VLMul = MInfo.value;
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@ -675,8 +675,8 @@ multiclass VPseudoBinaryV_VV {
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multiclass VPseudoBinaryV_VX<bit IsFloat> {
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foreach m = MxList.m in
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defm !if(!eq(IsFloat, 0), "_VX", "_VF") : VPseudoBinary<m.vrclass, m.vrclass,
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!if(!eq(IsFloat, 0), GPR, FPR32), m>;
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defm !if(IsFloat, "_VF", "_VX") : VPseudoBinary<m.vrclass, m.vrclass,
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!if(IsFloat, FPR32, GPR), m>;
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}
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multiclass VPseudoBinaryV_VI<Operand ImmType = simm5> {
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@ -699,8 +699,8 @@ multiclass VPseudoBinaryW_VV {
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multiclass VPseudoBinaryW_VX<bit IsFloat> {
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foreach m = MxList.m[0-5] in
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defm !if(!eq(IsFloat, 0), "_VX", "_VF") : VPseudoBinary<m.wvrclass, m.vrclass,
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!if(!eq(IsFloat, 0), GPR, FPR32), m,
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defm !if(IsFloat, "_VF", "_VX") : VPseudoBinary<m.wvrclass, m.vrclass,
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!if(IsFloat, FPR32, GPR), m,
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"@earlyclobber $rd">;
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}
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@ -712,8 +712,8 @@ multiclass VPseudoBinaryW_WV {
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multiclass VPseudoBinaryW_WX<bit IsFloat> {
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foreach m = MxList.m[0-5] in
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defm !if(!eq(IsFloat, 0), "_WX", "_WF") : VPseudoBinary<m.wvrclass, m.wvrclass,
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!if(!eq(IsFloat, 0), GPR, FPR32), m,
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defm !if(IsFloat, "_WF", "_WX") : VPseudoBinary<m.wvrclass, m.wvrclass,
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!if(IsFloat, FPR32, GPR), m,
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"@earlyclobber $rd">;
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}
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@ -741,9 +741,9 @@ multiclass VPseudoBinaryV_WI {
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multiclass VPseudoBinaryV_VM<bit CarryOut = 0, bit CarryIn = 1,
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string Constraint = ""> {
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foreach m = MxList.m in
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def "_VV" # !if(!eq(CarryIn, 1), "M", "") # "_" # m.MX :
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VPseudoBinaryCarryIn<!if(!eq(CarryOut, 1), VR,
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!if(!and(!eq(CarryIn, 1), !eq(CarryOut, 0)),
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def "_VV" # !if(CarryIn, "M", "") # "_" # m.MX :
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VPseudoBinaryCarryIn<!if(CarryOut, VR,
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!if(!and(CarryIn, !not(CarryOut)),
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GetVRegNoV0<m.vrclass>.R, m.vrclass)),
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m.vrclass, m.vrclass, m, CarryIn, Constraint>;
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}
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@ -751,9 +751,9 @@ multiclass VPseudoBinaryV_VM<bit CarryOut = 0, bit CarryIn = 1,
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multiclass VPseudoBinaryV_XM<bit CarryOut = 0, bit CarryIn = 1,
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string Constraint = ""> {
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foreach m = MxList.m in
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def "_VX" # !if(!eq(CarryIn, 1), "M", "") # "_" # m.MX :
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VPseudoBinaryCarryIn<!if(!eq(CarryOut, 1), VR,
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!if(!and(!eq(CarryIn, 1), !eq(CarryOut, 0)),
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def "_VX" # !if(CarryIn, "M", "") # "_" # m.MX :
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VPseudoBinaryCarryIn<!if(CarryOut, VR,
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!if(!and(CarryIn, !not(CarryOut)),
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GetVRegNoV0<m.vrclass>.R, m.vrclass)),
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m.vrclass, GPR, m, CarryIn, Constraint>;
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}
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@ -761,9 +761,9 @@ multiclass VPseudoBinaryV_XM<bit CarryOut = 0, bit CarryIn = 1,
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multiclass VPseudoBinaryV_IM<bit CarryOut = 0, bit CarryIn = 1,
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string Constraint = ""> {
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foreach m = MxList.m in
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def "_VI" # !if(!eq(CarryIn, 1), "M", "") # "_" # m.MX :
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VPseudoBinaryCarryIn<!if(!eq(CarryOut, 1), VR,
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!if(!and(!eq(CarryIn, 1), !eq(CarryOut, 0)),
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def "_VI" # !if(CarryIn, "M", "") # "_" # m.MX :
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VPseudoBinaryCarryIn<!if(CarryOut, VR,
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!if(!and(CarryIn, !not(CarryOut)),
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GetVRegNoV0<m.vrclass>.R, m.vrclass)),
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m.vrclass, simm5, m, CarryIn, Constraint>;
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}
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@ -789,8 +789,8 @@ multiclass VPseudoBinaryM_VV {
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multiclass VPseudoBinaryM_VX<bit IsFloat> {
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foreach m = MxList.m in
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defm !if(!eq(IsFloat, 0), "_VX", "_VF") :
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VPseudoBinary<VR, m.vrclass, !if(!eq(IsFloat, 0), GPR, FPR32), m,
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defm !if(IsFloat, "_VF", "_VX") :
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VPseudoBinary<VR, m.vrclass, !if(IsFloat, FPR32, GPR), m,
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"@earlyclobber $rd">;
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}
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@ -1374,7 +1374,7 @@ multiclass VPatBinaryV_VM<string intrinsic, string instruction,
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bit CarryOut = 0> {
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foreach vti = AllIntegerVectors in
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defm : VPatBinaryCarryIn<intrinsic, instruction, "VVM",
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!if(!eq(CarryOut, 1), vti.Mask, vti.Vector),
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!if(CarryOut, vti.Mask, vti.Vector),
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vti.Vector, vti.Vector, vti.Mask,
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vti.SEW, vti.LMul,
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vti.RegClass, vti.RegClass>;
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@ -1384,7 +1384,7 @@ multiclass VPatBinaryV_XM<string intrinsic, string instruction,
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bit CarryOut = 0> {
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foreach vti = AllIntegerVectors in
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defm : VPatBinaryCarryIn<intrinsic, instruction, "VXM",
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!if(!eq(CarryOut, 1), vti.Mask, vti.Vector),
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!if(CarryOut, vti.Mask, vti.Vector),
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vti.Vector, XLenVT, vti.Mask,
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vti.SEW, vti.LMul,
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vti.RegClass, GPR>;
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@ -1394,7 +1394,7 @@ multiclass VPatBinaryV_IM<string intrinsic, string instruction,
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bit CarryOut = 0> {
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foreach vti = AllIntegerVectors in
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defm : VPatBinaryCarryIn<intrinsic, instruction, "VIM",
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!if(!eq(CarryOut, 1), vti.Mask, vti.Vector),
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!if(CarryOut, vti.Mask, vti.Vector),
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vti.Vector, XLenVT, vti.Mask,
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vti.SEW, vti.LMul,
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vti.RegClass, simm5>;
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