[WebAssembly] Fix comments to say "LIFO" instead of "FIFO" when describing a stack.

llvm-svn: 254523

llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp

@@ -341,7 +341,7 @@ bool WebAssemblyCFGStackify::runOnMachineFunction(MachineFunction &MF) {
   PlaceMarkers(MF, MLI, TII, MDT);
 
 #ifndef NDEBUG
-  // Verify that block and loop beginnings and endings are in FIFO order, and
+  // Verify that block and loop beginnings and endings are in LIFO order, and
   // that all references to blocks are to blocks on the stack at the point of
   // the reference.
   SmallVector<std::pair<MachineBasicBlock *, bool>, 0> Stack;

llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h

@@ -37,7 +37,7 @@ class WebAssemblyFunctionInfo final : public MachineFunctionInfo {
   /// determined or made to meet the stack requirements:
   ///   - single use (per path)
   ///   - single def (per path)
-  ///   - defined and used in FIFO order with other stack registers
+  ///   - defined and used in LIFO order with other stack registers
   BitVector VRegStackified;
 
 public:

llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

@@ -117,7 +117,7 @@ bool WebAssemblyRegStackify::runOnMachineFunction(MachineFunction &MF) {
         break;
 
       // Iterate through the inputs in reverse order, since we'll be pulling
-      // operands off the stack in FIFO order.
+      // operands off the stack in LIFO order.
       bool AnyStackified = false;
       for (MachineOperand &Op : reverse(Insert->uses())) {
         // We're only interested in explicit virtual register operands.

llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td

@@ -40,7 +40,7 @@ def F32_0 : WebAssemblyReg<"%f32.0">;
 def F64_0 : WebAssemblyReg<"%f64.0">;
 
 // The expression stack "register". This is an opaque entity which serves to
-// order uses and defs that must remain in FIFO order.
+// order uses and defs that must remain in LIFO order.
 def EXPR_STACK : WebAssemblyReg<"STACK">;
 
 // The incoming arguments "register". This is an opaque entity which serves to