forked from OSchip/llvm-project
AMDGPU/GlobalISel: Handle more G_INSERT cases
Start manually writing a table to get the subreg index. TableGen should probably generate this, but I'm not sure what it looks like in the arbitrary case where subregisters are allowed to not fully cover the super-registers. llvm-svn: 373947
This commit is contained in:
Matt Arsenault
parent
4bcdcad91b
commit
538b73b797
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@ -555,48 +555,6 @@ bool AMDGPUInstructionSelector::selectG_IMPLICIT_DEF(MachineInstr &I) const {
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return false;
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}
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// FIXME: TableGen should generate something to make this manageable for all
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// register classes. At a minimum we could use the opposite of
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// composeSubRegIndices and go up from the base 32-bit subreg.
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static unsigned getSubRegForSizeAndOffset(const SIRegisterInfo &TRI,
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unsigned Size, unsigned Offset) {
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switch (Size) {
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case 32:
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return TRI.getSubRegFromChannel(Offset / 32);
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case 64: {
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switch (Offset) {
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case 0:
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return AMDGPU::sub0_sub1;
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case 32:
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return AMDGPU::sub1_sub2;
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case 64:
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return AMDGPU::sub2_sub3;
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case 96:
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return AMDGPU::sub4_sub5;
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case 128:
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return AMDGPU::sub5_sub6;
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case 160:
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return AMDGPU::sub7_sub8;
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// FIXME: Missing cases up to 1024 bits
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default:
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return AMDGPU::NoSubRegister;
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}
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}
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case 96: {
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switch (Offset) {
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case 0:
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return AMDGPU::sub0_sub1_sub2;
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case 32:
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return AMDGPU::sub1_sub2_sub3;
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case 64:
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return AMDGPU::sub2_sub3_sub4;
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}
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}
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default:
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return AMDGPU::NoSubRegister;
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}
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}
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bool AMDGPUInstructionSelector::selectG_INSERT(MachineInstr &I) const {
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MachineBasicBlock *BB = I.getParent();
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@ -612,7 +570,7 @@ bool AMDGPUInstructionSelector::selectG_INSERT(MachineInstr &I) const {
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if (Offset % 32 != 0)
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return false;
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unsigned SubReg = getSubRegForSizeAndOffset(TRI, InsSize, Offset);
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unsigned SubReg = TRI.getSubRegFromChannel(Offset / 32, InsSize / 32);
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if (SubReg == AMDGPU::NoSubRegister)
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return false;
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@ -26,19 +26,59 @@ AMDGPURegisterInfo::AMDGPURegisterInfo() : AMDGPUGenRegisterInfo(0) {}
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// they are not supported at this time.
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//===----------------------------------------------------------------------===//
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unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel) {
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static const unsigned SubRegs[] = {
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AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4,
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AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9,
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AMDGPU::sub10, AMDGPU::sub11, AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14,
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AMDGPU::sub15, AMDGPU::sub16, AMDGPU::sub17, AMDGPU::sub18, AMDGPU::sub19,
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AMDGPU::sub20, AMDGPU::sub21, AMDGPU::sub22, AMDGPU::sub23, AMDGPU::sub24,
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AMDGPU::sub25, AMDGPU::sub26, AMDGPU::sub27, AMDGPU::sub28, AMDGPU::sub29,
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AMDGPU::sub30, AMDGPU::sub31
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};
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// Table of NumRegs sized pieces at every 32-bit offset.
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static const uint16_t SubRegFromChannelTable[][32] = {
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{ AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
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AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
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AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
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AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15,
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AMDGPU::sub16, AMDGPU::sub17, AMDGPU::sub18, AMDGPU::sub19,
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AMDGPU::sub20, AMDGPU::sub21, AMDGPU::sub22, AMDGPU::sub23,
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AMDGPU::sub24, AMDGPU::sub25, AMDGPU::sub26, AMDGPU::sub27,
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AMDGPU::sub28, AMDGPU::sub29, AMDGPU::sub30, AMDGPU::sub31
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},
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{
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AMDGPU::sub0_sub1, AMDGPU::sub1_sub2, AMDGPU::sub2_sub3, AMDGPU::sub3_sub4,
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AMDGPU::sub4_sub5, AMDGPU::sub5_sub6, AMDGPU::sub6_sub7, AMDGPU::sub7_sub8,
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AMDGPU::sub8_sub9, AMDGPU::sub9_sub10, AMDGPU::sub10_sub11, AMDGPU::sub11_sub12,
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AMDGPU::sub12_sub13, AMDGPU::sub13_sub14, AMDGPU::sub14_sub15, AMDGPU::sub15_sub16,
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AMDGPU::sub16_sub17, AMDGPU::sub17_sub18, AMDGPU::sub18_sub19, AMDGPU::sub19_sub20,
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AMDGPU::sub20_sub21, AMDGPU::sub21_sub22, AMDGPU::sub22_sub23, AMDGPU::sub23_sub24,
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AMDGPU::sub24_sub25, AMDGPU::sub25_sub26, AMDGPU::sub26_sub27, AMDGPU::sub27_sub28,
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AMDGPU::sub28_sub29, AMDGPU::sub29_sub30, AMDGPU::sub30_sub31, AMDGPU::NoSubRegister
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},
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{
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AMDGPU::sub0_sub1_sub2, AMDGPU::sub1_sub2_sub3, AMDGPU::sub2_sub3_sub4, AMDGPU::sub3_sub4_sub5,
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AMDGPU::sub4_sub5_sub6, AMDGPU::sub5_sub6_sub7, AMDGPU::sub6_sub7_sub8, AMDGPU::sub7_sub8_sub9,
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AMDGPU::sub8_sub9_sub10, AMDGPU::sub9_sub10_sub11, AMDGPU::sub10_sub11_sub12, AMDGPU::sub11_sub12_sub13,
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AMDGPU::sub12_sub13_sub14, AMDGPU::sub13_sub14_sub15, AMDGPU::sub14_sub15_sub16, AMDGPU::sub15_sub16_sub17,
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AMDGPU::sub16_sub17_sub18, AMDGPU::sub17_sub18_sub19, AMDGPU::sub18_sub19_sub20, AMDGPU::sub19_sub20_sub21,
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AMDGPU::sub20_sub21_sub22, AMDGPU::sub21_sub22_sub23, AMDGPU::sub22_sub23_sub24, AMDGPU::sub23_sub24_sub25,
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AMDGPU::sub24_sub25_sub26, AMDGPU::sub25_sub26_sub27, AMDGPU::sub26_sub27_sub28, AMDGPU::sub27_sub28_sub29,
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AMDGPU::sub28_sub29_sub30, AMDGPU::sub29_sub30_sub31, AMDGPU::NoSubRegister, AMDGPU::NoSubRegister
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},
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{
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AMDGPU::sub0_sub1_sub2_sub3, AMDGPU::sub1_sub2_sub3_sub4, AMDGPU::sub2_sub3_sub4_sub5, AMDGPU::sub3_sub4_sub5_sub6,
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AMDGPU::sub4_sub5_sub6_sub7, AMDGPU::sub5_sub6_sub7_sub8, AMDGPU::sub6_sub7_sub8_sub9, AMDGPU::sub7_sub8_sub9_sub10,
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AMDGPU::sub8_sub9_sub10_sub11, AMDGPU::sub9_sub10_sub11_sub12, AMDGPU::sub10_sub11_sub12_sub13, AMDGPU::sub11_sub12_sub13_sub14,
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AMDGPU::sub12_sub13_sub14_sub15, AMDGPU::sub13_sub14_sub15_sub16, AMDGPU::sub14_sub15_sub16_sub17, AMDGPU::sub15_sub16_sub17_sub18,
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AMDGPU::sub16_sub17_sub18_sub19, AMDGPU::sub17_sub18_sub19_sub20, AMDGPU::sub18_sub19_sub20_sub21, AMDGPU::sub19_sub20_sub21_sub22,
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AMDGPU::sub20_sub21_sub22_sub23, AMDGPU::sub21_sub22_sub23_sub24, AMDGPU::sub22_sub23_sub24_sub25, AMDGPU::sub23_sub24_sub25_sub26,
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AMDGPU::sub24_sub25_sub26_sub27, AMDGPU::sub25_sub26_sub27_sub28, AMDGPU::sub26_sub27_sub28_sub29, AMDGPU::sub27_sub28_sub29_sub30,
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AMDGPU::sub28_sub29_sub30_sub31, AMDGPU::NoSubRegister, AMDGPU::NoSubRegister, AMDGPU::NoSubRegister
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}
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};
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assert(Channel < array_lengthof(SubRegs));
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return SubRegs[Channel];
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// FIXME: TableGen should generate something to make this manageable for all
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// register classes. At a minimum we could use the opposite of
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// composeSubRegIndices and go up from the base 32-bit subreg.
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unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel, unsigned NumRegs) {
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const unsigned NumRegIndex = NumRegs - 1;
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assert(NumRegIndex < array_lengthof(SubRegFromChannelTable) &&
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"Not implemented");
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assert(Channel < array_lengthof(SubRegFromChannelTable[0]));
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return SubRegFromChannelTable[NumRegIndex][Channel];
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}
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void AMDGPURegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
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@ -28,7 +28,7 @@ struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {
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/// \returns the sub reg enum value for the given \p Channel
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/// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0)
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static unsigned getSubRegFromChannel(unsigned Channel);
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static unsigned getSubRegFromChannel(unsigned Channel, unsigned NumRegs = 1);
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void reserveRegisterTuples(BitVector &, unsigned Reg) const;
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};
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@ -303,41 +303,46 @@ body: |
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---
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name: insert_s_s256_s_s64_96
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name: insert_s_v256_v_s64_96
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9
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; CHECK-LABEL: name: insert_s_v256_v_s64_96
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; CHECK: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
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; CHECK: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr8_vgpr9
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub3_sub4
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; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
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%0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
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%1:vgpr(s64) = COPY $vgpr8_vgpr9
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%2:vgpr(s256) = G_INSERT %0, %1, 96
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S_ENDPGM 0, implicit %2
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...
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---
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name: insert_s_s256_s_s64_128
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9
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; CHECK-LABEL: name: insert_s_s256_s_s64_96
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; CHECK-LABEL: name: insert_s_s256_s_s64_128
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; CHECK: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
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; CHECK: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr8_sgpr9
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; CHECK: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr4_sgpr5
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub4_sub5
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; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
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%0:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
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%1:sgpr(s64) = COPY $sgpr8_sgpr9
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%2:sgpr(s256) = G_INSERT %0, %1, 96
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%1:sgpr(s64) = COPY $sgpr4_sgpr5
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%2:sgpr(s256) = G_INSERT %0, %1, 128
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S_ENDPGM 0, implicit %2
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...
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# ---
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# name: insert_s_s256_s_s64_128
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# legalized: true
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# regBankSelected: true
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# body: |
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# bb.0:
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# liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9
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# %0:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
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# %1:sgpr(s64) = COPY $sgpr4_sgpr5
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# %2:sgpr(s256) = G_INSERT %0, %1, 128
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# S_ENDPGM 0, implicit %2
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# ...
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# ---
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# name: insert_s_s256_s_s64_160
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# legalized: true
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# regBankSelected: true
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@ -450,3 +455,108 @@ body: |
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%2:sgpr(s160) = G_INSERT %0, %1, 64
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S_ENDPGM 0, implicit %2
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...
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---
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name: insert_s_s256_s_s128_0
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11
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; CHECK-LABEL: name: insert_s_s256_s_s128_0
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; CHECK: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
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; CHECK: [[COPY1:%[0-9]+]]:sreg_128 = COPY $sgpr8_sgpr9_sgpr10_sgpr11
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1_sub2_sub3
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; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
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%0:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
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%1:sgpr(s128) = COPY $sgpr8_sgpr9_sgpr10_sgpr11
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%2:sgpr(s256) = G_INSERT %0, %1, 0
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S_ENDPGM 0, implicit %2
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...
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---
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name: insert_v_s256_v_s128_32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
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; CHECK-LABEL: name: insert_v_s256_v_s128_32
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; CHECK: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
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; CHECK: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr8_vgpr9_vgpr10_vgpr11
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1_sub2_sub3_sub4
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; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
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%0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
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%1:vgpr(s128) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
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%2:vgpr(s256) = G_INSERT %0, %1, 32
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S_ENDPGM 0, implicit %2
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...
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---
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name: insert_v_s256_v_s128_64
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
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; CHECK-LABEL: name: insert_v_s256_v_s128_64
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; CHECK: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
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; CHECK: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr8_vgpr9_vgpr10_vgpr11
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub2_sub3_sub4_sub5
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; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
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%0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
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%1:vgpr(s128) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
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%2:vgpr(s256) = G_INSERT %0, %1, 64
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S_ENDPGM 0, implicit %2
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...
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---
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name: insert_v_s256_v_s128_96
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
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; CHECK-LABEL: name: insert_v_s256_v_s128_96
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; CHECK: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
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; CHECK: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr8_vgpr9_vgpr10_vgpr11
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub3_sub4_sub5_sub6
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; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
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%0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
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%1:vgpr(s128) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
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%2:vgpr(s256) = G_INSERT %0, %1, 96
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S_ENDPGM 0, implicit %2
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...
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---
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name: insert_v_s256_v_s128_128
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
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; CHECK-LABEL: name: insert_v_s256_v_s128_128
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; CHECK: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
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; CHECK: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr8_vgpr9_vgpr10_vgpr11
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub4_sub5_sub6_sub7
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; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
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%0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
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%1:vgpr(s128) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
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%2:vgpr(s256) = G_INSERT %0, %1, 128
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S_ENDPGM 0, implicit %2
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...
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