forked from OSchip/llvm-project
AMDGPU: Add support for R_AMDGPU_REL32 relocations
Reviewers: arsenm, kzhuravl, rafael Subscribers: arsenm, llvm-commits, kzhuravl Differential Revision: http://reviews.llvm.org/D21401 llvm-svn: 273168
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@ -45,6 +45,12 @@ unsigned AMDGPUELFObjectWriter::getRelocType(MCContext &Ctx,
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if (Target.getSymA()->getSymbol().getName() == "SCRATCH_RSRC_DWORD1")
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return ELF::R_AMDGPU_ABS32_HI;
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switch (Fixup.getKind()) {
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default: break;
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case FK_PCRel_4:
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return ELF::R_AMDGPU_REL32;
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}
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llvm_unreachable("unhandled relocation type");
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}
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@ -1420,7 +1420,8 @@ SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
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SelectionDAG &DAG) const {
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GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Op);
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if (GSD->getAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
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if (GSD->getAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS &&
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GSD->getAddressSpace() != AMDGPUAS::GLOBAL_ADDRESS)
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return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
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SDLoc DL(GSD);
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@ -1,12 +1,17 @@
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; RUN: not llc -march=amdgcn -mcpu=SI < %s 2>&1 | FileCheck %s
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; RUN: not llc -march=amdgcn -mcpu=tonga < %s 2>&1 | FileCheck %s
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; RUN: llc -march=amdgcn -mcpu=SI < %s 2>&1 | FileCheck %s
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; RUN: llc -march=amdgcn -mcpu=tonga < %s 2>&1 | FileCheck %s
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; CHECK: in function load_init_global_global{{.*}}: unsupported initializer for address space
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@lds = addrspace(1) global [256 x i32] zeroinitializer
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; CHECK: {{^}}load_init_global_global:
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; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
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; CHECK: s_add_u32 s[[ADDR_LO:[0-9]+]], s[[PC_LO]], global+4
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; CHECK: s_addc_u32 s5, s[[PC_HI]], 0
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; CHECK: buffer_load_dword v{{[0-9]+}}, off, s{{\[}}[[ADDR_LO]]:7], 0 offset:40
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; CHECK: global:
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; CHECK: .zero 1024
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@global = addrspace(1) global [256 x i32] zeroinitializer
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define void @load_init_global_global(i32 addrspace(1)* %out, i1 %p) {
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%gep = getelementptr [256 x i32], [256 x i32] addrspace(1)* @lds, i32 0, i32 10
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%gep = getelementptr [256 x i32], [256 x i32] addrspace(1)* @global, i32 0, i32 10
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%ld = load i32, i32 addrspace(1)* %gep
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store i32 %ld, i32 addrspace(1)* %out
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ret void
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@ -40,6 +40,7 @@ main_body:
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;CHECK: s_and_b64 exec, exec, [[ORIG]]
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;CHECK: store
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;CHECK-NOT: exec
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;CHECK: .size test3
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define amdgpu_ps <4 x float> @test3(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <4 x i32> %c) {
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main_body:
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%tex = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %c, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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