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[Hexagon] Handle HVX registers in bit simplification 

llvm-svn: 257811
This commit is contained in:
Krzysztof Parzyszek 2016-01-14 21:45:43 +00:00
parent e8c3609d3a
commit 5337a3e965
1 changed files with 6 additions and 0 deletions
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6
llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
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@ -876,6 +876,12 @@ const TargetRegisterClass *HexagonBitSimplify::getFinalVRegClass(
case Hexagon::DoubleRegsRegClassID:
VerifySR(RR.Sub);
return &Hexagon::IntRegsRegClass;
case Hexagon::VecDblRegsRegClassID:
VerifySR(RR.Sub);
return &Hexagon::VectorRegsRegClass;
case Hexagon::VecDblRegs128BRegClassID:
VerifySR(RR.Sub);
return &Hexagon::VectorRegs128BRegClass;
}
return nullptr;
}