forked from OSchip/llvm-project
Added isDef field to MachineOperand class - Ruchira
llvm-svn: 349
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@ -84,6 +84,8 @@ private:
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int64_t immedVal; // constant value for an explicit constant
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};
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public:
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/*ctor*/ MachineOperand ();
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@ -111,6 +113,9 @@ public:
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return immedVal;
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}
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bool isDef; // is this a defition for the value
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// made public for faster access
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public:
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friend ostream& operator<<(ostream& os, const MachineOperand& mop);
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@ -134,7 +139,8 @@ MachineOperand::MachineOperand()
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: opType(MO_VirtualRegister),
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value(NULL),
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regNum(0),
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immedVal(0)
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immedVal(0),
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isDef(false)
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{}
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inline
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@ -143,12 +149,14 @@ MachineOperand::MachineOperand(MachineOperandType operandType,
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: opType(operandType),
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value(_val),
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regNum(0),
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immedVal(0)
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immedVal(0),
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isDef(false)
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{}
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inline
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MachineOperand::MachineOperand(const MachineOperand& mo)
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: opType(mo.opType)
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: opType(mo.opType),
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isDef(false)
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{
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switch(opType) {
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case MO_VirtualRegister:
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@ -240,12 +248,13 @@ public:
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// Access to set the operands when building the machine instruction
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void SetMachineOperand(unsigned int i,
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MachineOperand::MachineOperandType operandType,
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Value* _val);
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Value* _val, bool isDef=false);
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void SetMachineOperand(unsigned int i,
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MachineOperand::MachineOperandType operandType,
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int64_t intValue);
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int64_t intValue, bool isDef=false);
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void SetMachineOperand(unsigned int i,
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unsigned int regNum);
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unsigned int regNum,
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bool isDef=false);
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};
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inline const MachineOpCode
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@ -299,7 +308,9 @@ public:
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inline _V* operator*() const { return minstr->getOperand(i).getVRegValue();}
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inline _V* operator->() const { return operator*(); }
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inline bool isDef () const { return (((int) i) == resultPos); }
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// inline bool isDef () const { return (((int) i) == resultPos); }
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inline bool isDef () const { return minstr->getOperand(i).isDef; }
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inline bool done () const { return (i == minstr->getNumOperands()); }
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inline _Self& operator++() { i++; skipToNextVal(); return *this; }
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