From 52dacca9773bd0a7df02b005dc56cf4caca02323 Mon Sep 17 00:00:00 2001 From: Preston Gurd Date: Mon, 29 Oct 2012 15:01:23 +0000 Subject: [PATCH] This patch addresses a problem with the Post RA scheduler generating an incorrect instruction sequence due to it not being aware that an inline assembly instruction may reference memory. This patch fixes the problem by causing the scheduler to always assume that any inline assembly code instruction could access memory. This is necessary because the internal representation of the inline instruction does not include any information about memory accesses. This should fix PR13504. llvm-svn: 166929 --- llvm/lib/CodeGen/ScheduleDAGInstrs.cpp | 5 +++++ llvm/test/CodeGen/X86/inlineasm-sched-bug.ll | 13 +++++++++++++ 2 files changed, 18 insertions(+) create mode 100644 llvm/test/CodeGen/X86/inlineasm-sched-bug.ll diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp index 496473d3a4b2..8ea0f8a3eacc 100644 --- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -420,6 +420,11 @@ void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) { /// Return true if MI is an instruction we are unable to reason about /// (like a call or something with unmodeled side effects). static inline bool isGlobalMemoryObject(AliasAnalysis *AA, MachineInstr *MI) { + if (MI->isInlineAsm()) { + // Until we can tell if an inline assembly instruction accesses + // memory, we must assume all such instructions do so. + return true; + } if (MI->isCall() || MI->hasUnmodeledSideEffects() || (MI->hasOrderedMemoryRef() && (!MI->mayLoad() || !MI->isInvariantLoad(AA)))) diff --git a/llvm/test/CodeGen/X86/inlineasm-sched-bug.ll b/llvm/test/CodeGen/X86/inlineasm-sched-bug.ll new file mode 100644 index 000000000000..08de0c02d293 --- /dev/null +++ b/llvm/test/CodeGen/X86/inlineasm-sched-bug.ll @@ -0,0 +1,13 @@ +; PR13504 +; RUN: llc -march=x86 -mcpu=atom <%s | FileCheck %s +; CHECK: bsfl +; CHECK-NOT: movl + +define i32 @foo(i32 %treemap) nounwind uwtable { +entry: + %sub = sub i32 0, %treemap + %and = and i32 %treemap, %sub + %0 = tail call i32 asm "bsfl $1,$0\0A\09", "=r,rm,~{dirflag},~{fpsr},~{flags}"(i32 %and) nounwind + ret i32 %0 +} +