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[DAG] Update expandFunnelShift/expandROT to return the expansion directly. NFCI. 

Don't return a bool to indicate if the expansion was successful, just return the SDValue result directly, like we do for most other basic expansions.
This commit is contained in:
Simon Pilgrim 2021-12-07 17:57:32 +00:00
parent 5c7e783ebe
commit 52d2f35323
5 changed files with 23 additions and 31 deletions
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11
llvm/include/llvm/CodeGen/TargetLowering.h
View File

@ -4460,18 +4460,15 @@ public:
/// Expand funnel shift.
/// \param N Node to expand
/// \param Result output after conversion
/// \returns True, if the expansion was successful, false otherwise
bool expandFunnelShift(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
/// \returns The expansion if successful, SDValue() otherwise
SDValue expandFunnelShift(SDNode *N, SelectionDAG &DAG) const;
/// Expand rotations.
/// \param N Node to expand
/// \param AllowVectorOps expand vector rotate, this should only be performed
/// if the legalization is happening outside of LegalizeVectorOps
/// \param Result output after conversion
/// \returns True, if the expansion was successful, false otherwise
bool expandROT(SDNode *N, bool AllowVectorOps, SDValue &Result,
SelectionDAG &DAG) const;
/// \returns The expansion if successful, SDValue() otherwise
SDValue expandROT(SDNode *N, bool AllowVectorOps, SelectionDAG &DAG) const;
/// Expand shift-by-parts.
/// \param N Node to expand

8
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -3367,13 +3367,13 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
}
case ISD::FSHL:
case ISD::FSHR:
if (TLI.expandFunnelShift(Node, Tmp1, DAG))
Results.push_back(Tmp1);
if (SDValue Expanded = TLI.expandFunnelShift(Node, DAG))
Results.push_back(Expanded);
break;
case ISD::ROTL:
case ISD::ROTR:
if (TLI.expandROT(Node, true /*AllowVectorOps*/, Tmp1, DAG))
Results.push_back(Tmp1);
if (SDValue Expanded = TLI.expandROT(Node, true /*AllowVectorOps*/, DAG))
Results.push_back(Expanded);
break;
case ISD::SADDSAT:
case ISD::UADDSAT:

3
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -1277,8 +1277,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N, bool IsVP) {
SDValue DAGTypeLegalizer::PromoteIntRes_Rotate(SDNode *N) {
// Lower the rotate to shifts and ORs which can be promoted.
SDValue Res;
TLI.expandROT(N, true /*AllowVectorOps*/, Res, DAG);
SDValue Res = TLI.expandROT(N, true /*AllowVectorOps*/, DAG);
ReplaceValueWith(SDValue(N, 0), Res);
return SDValue();
}

8
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
View File

@ -804,15 +804,15 @@ void VectorLegalizer::Expand(SDNode *Node, SmallVectorImpl<SDValue> &Results) {
break;
case ISD::FSHL:
case ISD::FSHR:
if (TLI.expandFunnelShift(Node, Tmp, DAG)) {
Results.push_back(Tmp);
if (SDValue Expanded = TLI.expandFunnelShift(Node, DAG)) {
Results.push_back(Expanded);
return;
}
break;
case ISD::ROTL:
case ISD::ROTR:
if (TLI.expandROT(Node, false /*AllowVectorOps*/, Tmp, DAG)) {
Results.push_back(Tmp);
if (SDValue Expanded = TLI.expandROT(Node, false /*AllowVectorOps*/, DAG)) {
Results.push_back(Expanded);
return;
}
break;

24
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -6546,15 +6546,15 @@ static bool isNonZeroModBitWidthOrUndef(SDValue Z, unsigned BW) {
true);
}
bool TargetLowering::expandFunnelShift(SDNode *Node, SDValue &Result,
SelectionDAG &DAG) const {
SDValue TargetLowering::expandFunnelShift(SDNode *Node,
SelectionDAG &DAG) const {
EVT VT = Node->getValueType(0);
if (VT.isVector() && (!isOperationLegalOrCustom(ISD::SHL, VT) ||
!isOperationLegalOrCustom(ISD::SRL, VT) ||
!isOperationLegalOrCustom(ISD::SUB, VT) ||
!isOperationLegalOrCustomOrPromote(ISD::OR, VT)))
return false;
return SDValue();
SDValue X = Node->getOperand(0);
SDValue Y = Node->getOperand(1);
@ -6588,8 +6588,7 @@ bool TargetLowering::expandFunnelShift(SDNode *Node, SDValue &Result,
}
Z = DAG.getNOT(DL, Z, ShVT);
}
Result = DAG.getNode(RevOpcode, DL, VT, X, Y, Z);
return true;
return DAG.getNode(RevOpcode, DL, VT, X, Y, Z);
}
SDValue ShX, ShY;
@ -6629,13 +6628,12 @@ bool TargetLowering::expandFunnelShift(SDNode *Node, SDValue &Result,
ShY = DAG.getNode(ISD::SRL, DL, VT, Y, ShAmt);
}
}
Result = DAG.getNode(ISD::OR, DL, VT, ShX, ShY);
return true;
return DAG.getNode(ISD::OR, DL, VT, ShX, ShY);
}
// TODO: Merge with expandFunnelShift.
bool TargetLowering::expandROT(SDNode *Node, bool AllowVectorOps,
SDValue &Result, SelectionDAG &DAG) const {
SDValue TargetLowering::expandROT(SDNode *Node, bool AllowVectorOps,
SelectionDAG &DAG) const {
EVT VT = Node->getValueType(0);
unsigned EltSizeInBits = VT.getScalarSizeInBits();
bool IsLeft = Node->getOpcode() == ISD::ROTL;
@ -6650,8 +6648,7 @@ bool TargetLowering::expandROT(SDNode *Node, bool AllowVectorOps,
unsigned RevRot = IsLeft ? ISD::ROTR : ISD::ROTL;
if (isOperationLegalOrCustom(RevRot, VT) && isPowerOf2_32(EltSizeInBits)) {
SDValue Sub = DAG.getNode(ISD::SUB, DL, ShVT, Zero, Op1);
Result = DAG.getNode(RevRot, DL, VT, Op0, Sub);
return true;
return DAG.getNode(RevRot, DL, VT, Op0, Sub);
}
if (!AllowVectorOps && VT.isVector() &&
@ -6660,7 +6657,7 @@ bool TargetLowering::expandROT(SDNode *Node, bool AllowVectorOps,
!isOperationLegalOrCustom(ISD::SUB, VT) ||
!isOperationLegalOrCustomOrPromote(ISD::OR, VT) ||
!isOperationLegalOrCustomOrPromote(ISD::AND, VT)))
return false;
return SDValue();
unsigned ShOpc = IsLeft ? ISD::SHL : ISD::SRL;
unsigned HsOpc = IsLeft ? ISD::SRL : ISD::SHL;
@ -6686,8 +6683,7 @@ bool TargetLowering::expandROT(SDNode *Node, bool AllowVectorOps,
HsVal =
DAG.getNode(HsOpc, DL, VT, DAG.getNode(HsOpc, DL, VT, Op0, One), HsAmt);
}
Result = DAG.getNode(ISD::OR, DL, VT, ShVal, HsVal);
return true;
return DAG.getNode(ISD::OR, DL, VT, ShVal, HsVal);
}
void TargetLowering::expandShiftParts(SDNode *Node, SDValue &Lo, SDValue &Hi,