forked from OSchip/llvm-project
[PowerPC] Fix the incorrect 'RM' flag set on load/store instr
The 'RM' flag model the "Rounding Mode" and it has nothing to do with the load/store instructions. Differential Revision: https://reviews.llvm.org/D69551
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@ -152,7 +152,6 @@ def HasOnlySwappingMemOps : Predicate<"!PPCSubTarget->hasP9Vector()">;
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let Predicates = [HasVSX] in {
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let Predicates = [HasVSX] in {
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let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
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let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
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let hasSideEffects = 0 in { // VSX instructions don't have side effects.
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let hasSideEffects = 0 in { // VSX instructions don't have side effects.
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let Uses = [RM] in {
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// Load indexed instructions
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// Load indexed instructions
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let mayLoad = 1, mayStore = 0 in {
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let mayLoad = 1, mayStore = 0 in {
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@ -214,6 +213,7 @@ let Uses = [RM] in {
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}
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}
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} // mayStore
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} // mayStore
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let Uses = [RM] in {
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// Add/Mul Instructions
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// Add/Mul Instructions
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let isCommutable = 1 in {
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let isCommutable = 1 in {
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def XSADDDP : XX3Form<60, 32,
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def XSADDDP : XX3Form<60, 32,
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@ -0,0 +1,9 @@
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; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -verify-misched -stop-after=machine-scheduler -o - | FileCheck %s --check-prefix=CHECK-P8
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; Verify XFLOADf64 didn't implict def 'rm'.
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define double @rm() {
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; CHECK-P8-LABEL: bb.0.entry
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; CHECK-P8: %{{[0-9]+}}:vsfrc = XFLOADf64 $zero8, %{{[0-9]+}} ::
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entry:
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ret double 2.300000e+00
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}
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