forked from OSchip/llvm-project
[mips][microMIPS] Implement ADDQ.PH, ADDQ_S.W, ADDQH.PH, ADDQH.W, ADDSC, ADDU.PH, ADDU_S.QB, ADDWC and ADDUH.QB instructions
Differential Revision: http://reviews.llvm.org/D13130 llvm-svn: 250685
This commit is contained in:
Zlatko Buljan
parent
1d97d2a3d2
commit
5292083584
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@ -64,3 +64,16 @@ class POOL32A_2RAC_FMT<string opstr, bits<8> op> : MMDSPInst<opstr> {
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let Inst{13-6} = op;
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let Inst{5-0} = 0b111100;
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}
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class POOL32A_3RB0_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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let Inst{31-26} = 0b000000;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-11} = rd;
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let Inst{10} = 0b0;
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let Inst{9-0} = op;
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}
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@ -12,7 +12,21 @@
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//===----------------------------------------------------------------------===//
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// Instruction encoding.
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class ADDQ_PH_MM_ENC : POOL32A_3R_FMT<"addq.ph", 0b00000001101>;
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class ADDQ_S_PH_MM_ENC : POOL32A_3R_FMT<"addq_s.ph", 0b10000001101>;
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class ADDQ_S_W_MM_ENC : POOL32A_3RB0_FMT<"addq_s.w", 0b1100000101>;
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class ADDQH_PH_MMR2_ENC : POOL32A_3R_FMT<"addqh.ph", 0b00001001101>;
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class ADDQH_R_PH_MMR2_ENC : POOL32A_3R_FMT<"addqh_r.ph", 0b10001001101>;
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class ADDQH_W_MMR2_ENC: POOL32A_3R_FMT<"addqh.w", 0b00010001101>;
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class ADDQH_R_W_MMR2_ENC : POOL32A_3R_FMT<"addqh_r.w", 0b10010001101>;
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class ADDU_PH_MMR2_ENC : POOL32A_3R_FMT<"addu.ph", 0b00100001101>;
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class ADDU_S_PH_MMR2_ENC : POOL32A_3R_FMT<"addu_s.ph", 0b10100001101>;
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class ADDU_QB_MM_ENC : POOL32A_3R_FMT<"addu.qb", 0b00011001101>;
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class ADDU_S_QB_MM_ENC : POOL32A_3R_FMT<"addu_s.qb", 0b10011001101>;
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class ADDUH_QB_MMR2_ENC : POOL32A_3R_FMT<"adduh.qb", 0b00101001101>;
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class ADDUH_R_QB_MMR2_ENC : POOL32A_3R_FMT<"adduh_r.qb", 0b10101001101>;
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class ADDSC_MM_ENC : POOL32A_3RB0_FMT<"addsc", 0b1110000101>;
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class ADDWC_MM_ENC : POOL32A_3RB0_FMT<"addwc", 0b1111000101>;
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class DPA_W_PH_MMR2_ENC : POOL32A_AC2R_FMT<"dpa.w.ph", 0b00000010>;
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class DPAQ_S_W_PH_MM_ENC : POOL32A_AC2R_FMT<"dpaq_s.w.ph", 0b00001010>;
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class DPAQ_SA_L_W_MM_ENC : POOL32A_AC2R_FMT<"dpaq_sa.l.w", 0b01001010>;
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@ -50,18 +64,17 @@ class ABSQ_S_QB_MMR2_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
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"absq_s.qb", int_mips_absq_s_qb, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>;
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// microMIPS DSP Rev 1
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def ADDQ_PH_MM : DspMMRel, ADDQ_PH_MM_ENC, ADDQ_PH_DESC;
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def ADDQ_S_PH_MM : DspMMRel, ADDQ_S_PH_MM_ENC, ADDQ_S_PH_DESC;
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def ADDQ_S_W_MM : DspMMRel, ADDQ_S_W_MM_ENC, ADDQ_S_W_DESC;
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def ADDU_QB_MM : DspMMRel, ADDU_QB_MM_ENC, ADDU_QB_DESC;
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def ADDU_S_QB_MM : DspMMRel, ADDU_S_QB_MM_ENC, ADDU_S_QB_DESC;
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def ADDSC_MM : DspMMRel, ADDSC_MM_ENC, ADDSC_DESC;
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def ADDWC_MM : DspMMRel, ADDWC_MM_ENC, ADDWC_DESC;
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def DPAQ_S_W_PH_MM : DspMMRel, DPAQ_S_W_PH_MM_ENC, DPAQ_S_W_PH_DESC;
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def DPAQ_SA_L_W_MM : DspMMRel, DPAQ_SA_L_W_MM_ENC, DPAQ_SA_L_W_DESC;
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def DPAU_H_QBL_MM : DspMMRel, DPAU_H_QBL_MM_ENC, DPAU_H_QBL_DESC;
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def DPAU_H_QBR_MM : DspMMRel, DPAU_H_QBR_MM_ENC, DPAU_H_QBR_DESC;
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// microMIPS DSP Rev 2
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def DPA_W_PH_MMR2 : DspMMRel, DPA_W_PH_MMR2_ENC, DPA_W_PH_DESC, ISA_DSPR2;
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def DPAQX_S_W_PH_MMR2 : DspMMRel, DPAQX_S_W_PH_MMR2_ENC, DPAQX_S_W_PH_DESC,
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ISA_DSPR2;
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def DPAQX_SA_W_PH_MMR2 : DspMMRel, DPAQX_SA_W_PH_MMR2_ENC, DPAQX_SA_W_PH_DESC,
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ISA_DSPR2;
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def DPAX_W_PH_MMR2 : DspMMRel, DPAX_W_PH_MMR2_ENC, DPAX_W_PH_DESC, ISA_DSPR2;
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def ABSQ_S_PH_MM : DspMMRel, ABSQ_S_PH_MM_ENC, ABSQ_S_PH_MM_DESC;
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def ABSQ_S_W_MM : DspMMRel, ABSQ_S_W_MM_ENC, ABSQ_S_W_MM_DESC;
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def INSV_MM : DspMMRel, INSV_MM_ENC, INSV_DESC;
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@ -74,3 +87,17 @@ def MULTU_DSP_MM : DspMMRel, MULTU_DSP_MM_ENC, MULTU_DSP_DESC;
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// microMIPS DSP Rev 2
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def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC,
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ISA_DSPR2;
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def ADDQH_PH_MMR2 : DspMMRel, ADDQH_PH_MMR2_ENC, ADDQH_PH_DESC, ISA_DSPR2;
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def ADDQH_R_PH_MMR2 : DspMMRel, ADDQH_R_PH_MMR2_ENC, ADDQH_R_PH_DESC, ISA_DSPR2;
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def ADDQH_W_MMR2 : DspMMRel, ADDQH_W_MMR2_ENC, ADDQH_W_DESC, ISA_DSPR2;
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def ADDQH_R_W_MMR2 : DspMMRel, ADDQH_R_W_MMR2_ENC, ADDQH_R_W_DESC, ISA_DSPR2;
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def ADDU_PH_MMR2 : DspMMRel, ADDU_PH_MMR2_ENC, ADDU_PH_DESC, ISA_DSPR2;
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def ADDU_S_PH_MMR2 : DspMMRel, ADDU_S_PH_MMR2_ENC, ADDU_S_PH_DESC, ISA_DSPR2;
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def ADDUH_QB_MMR2 : DspMMRel, ADDUH_QB_MMR2_ENC, ADDUH_QB_DESC, ISA_DSPR2;
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def ADDUH_R_QB_MMR2 : DspMMRel, ADDUH_R_QB_MMR2_ENC, ADDUH_R_QB_DESC, ISA_DSPR2;
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def DPA_W_PH_MMR2 : DspMMRel, DPA_W_PH_MMR2_ENC, DPA_W_PH_DESC, ISA_DSPR2;
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def DPAQX_S_W_PH_MMR2 : DspMMRel, DPAQX_S_W_PH_MMR2_ENC, DPAQX_S_W_PH_DESC,
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ISA_DSPR2;
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def DPAQX_SA_W_PH_MMR2 : DspMMRel, DPAQX_SA_W_PH_MMR2_ENC, DPAQX_SA_W_PH_DESC,
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ISA_DSPR2;
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def DPAX_W_PH_MMR2 : DspMMRel, DPAX_W_PH_MMR2_ENC, DPAX_W_PH_DESC, ISA_DSPR2;
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@ -365,6 +365,7 @@ class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
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list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
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InstrItinClass Itinerary = itin;
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string BaseOpcode = instr_asm;
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}
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class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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@ -1079,17 +1080,17 @@ def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32,
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// Instruction defs.
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// MIPS DSP Rev 1
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def ADDU_QB : DspMMRel, ADDU_QB_ENC, ADDU_QB_DESC;
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def ADDU_S_QB : ADDU_S_QB_ENC, ADDU_S_QB_DESC;
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def ADDU_S_QB : DspMMRel, ADDU_S_QB_ENC, ADDU_S_QB_DESC;
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def SUBU_QB : SUBU_QB_ENC, SUBU_QB_DESC;
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def SUBU_S_QB : SUBU_S_QB_ENC, SUBU_S_QB_DESC;
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def ADDQ_PH : ADDQ_PH_ENC, ADDQ_PH_DESC;
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def ADDQ_S_PH : ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
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def ADDQ_PH : DspMMRel, ADDQ_PH_ENC, ADDQ_PH_DESC;
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def ADDQ_S_PH : DspMMRel, ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
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def SUBQ_PH : SUBQ_PH_ENC, SUBQ_PH_DESC;
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def SUBQ_S_PH : SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
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def ADDQ_S_W : ADDQ_S_W_ENC, ADDQ_S_W_DESC;
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def ADDQ_S_W : DspMMRel, ADDQ_S_W_ENC, ADDQ_S_W_DESC;
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def SUBQ_S_W : SUBQ_S_W_ENC, SUBQ_S_W_DESC;
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def ADDSC : ADDSC_ENC, ADDSC_DESC;
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def ADDWC : ADDWC_ENC, ADDWC_DESC;
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def ADDSC : DspMMRel, ADDSC_ENC, ADDSC_DESC;
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def ADDWC : DspMMRel, ADDWC_ENC, ADDWC_DESC;
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def MODSUB : MODSUB_ENC, MODSUB_DESC;
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def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC;
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def ABSQ_S_PH : DspMMRel, ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
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@ -1195,24 +1196,24 @@ def WRDSP : WRDSP_ENC, WRDSP_DESC;
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// MIPS DSP Rev 2
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let Predicates = [HasDSPR2] in {
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def ADDU_PH : ADDU_PH_ENC, ADDU_PH_DESC;
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def ADDU_S_PH : ADDU_S_PH_ENC, ADDU_S_PH_DESC;
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def ADDU_PH : DspMMRel, ADDU_PH_ENC, ADDU_PH_DESC;
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def ADDU_S_PH : DspMMRel, ADDU_S_PH_ENC, ADDU_S_PH_DESC;
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def SUBU_PH : SUBU_PH_ENC, SUBU_PH_DESC;
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def SUBU_S_PH : SUBU_S_PH_ENC, SUBU_S_PH_DESC;
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def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC;
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def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC;
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def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC;
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def ABSQ_S_QB : DspMMRel, ABSQ_S_QB_ENC, ABSQ_S_QB_DESC;
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def ADDUH_QB : ADDUH_QB_ENC, ADDUH_QB_DESC;
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def ADDUH_R_QB : ADDUH_R_QB_ENC, ADDUH_R_QB_DESC;
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def ADDUH_QB : DspMMRel, ADDUH_QB_ENC, ADDUH_QB_DESC;
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def ADDUH_R_QB : DspMMRel, ADDUH_R_QB_ENC, ADDUH_R_QB_DESC;
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def SUBUH_QB : SUBUH_QB_ENC, SUBUH_QB_DESC;
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def SUBUH_R_QB : SUBUH_R_QB_ENC, SUBUH_R_QB_DESC;
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def ADDQH_PH : ADDQH_PH_ENC, ADDQH_PH_DESC;
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def ADDQH_R_PH : ADDQH_R_PH_ENC, ADDQH_R_PH_DESC;
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def ADDQH_PH : DspMMRel, ADDQH_PH_ENC, ADDQH_PH_DESC;
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def ADDQH_R_PH : DspMMRel, ADDQH_R_PH_ENC, ADDQH_R_PH_DESC;
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def SUBQH_PH : SUBQH_PH_ENC, SUBQH_PH_DESC;
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def SUBQH_R_PH : SUBQH_R_PH_ENC, SUBQH_R_PH_DESC;
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def ADDQH_W : ADDQH_W_ENC, ADDQH_W_DESC;
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def ADDQH_R_W : ADDQH_R_W_ENC, ADDQH_R_W_DESC;
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def ADDQH_W : DspMMRel, ADDQH_W_ENC, ADDQH_W_DESC;
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def ADDQH_R_W : DspMMRel, ADDQH_R_W_ENC, ADDQH_R_W_DESC;
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def SUBQH_W : SUBQH_W_ENC, SUBQH_W_DESC;
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def SUBQH_R_W : SUBQH_R_W_ENC, SUBQH_R_W_DESC;
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def MUL_PH : MUL_PH_ENC, MUL_PH_DESC;
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@ -1,6 +1,12 @@
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# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 -mattr=micromips -mattr=+dsp | FileCheck %s
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0x00 0xa4 0x18 0xcd # CHECK: addu.qb $3, $4, $5
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0x00 0xa4 0x1c 0xcd # CHECK: addu_s.qb $3, $4, $5
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0x00 0xa4 0x1b 0x85 # CHECK: addsc $3, $4, $5
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0x00 0xa4 0x1b 0xc5 # CHECK: addwc $3, $4, $5
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0x00 0xa4 0x18 0x0d # CHECK: addq.ph $3, $4, $5
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0x00 0xa4 0x1c 0x0d # CHECK: addq_s.ph $3, $4, $5
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0x00 0xa4 0x1b 0x05 # CHECK: addq_s.w $3, $4, $5
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0x00 0x65 0x42 0xbc # CHECK: dpaq_s.w.ph $ac1, $5, $3
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0x00 0x64 0x92 0xbc # CHECK: dpaq_sa.l.w $ac2, $4, $3
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0x00 0x83 0x60 0xbc # CHECK: dpau.h.qbl $ac1, $3, $4
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@ -1,5 +1,13 @@
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# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 -mattr=micromips -mattr=+dspr2 | FileCheck %s
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0x00 0xa4 0x18 0x4d # CHECK: addqh.ph $3, $4, $5
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0x00 0xa4 0x1c 0x4d # CHECK: addqh_r.ph $3, $4, $5
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0x00 0xa4 0x18 0x8d # CHECK: addqh.w $3, $4, $5
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0x00 0xa4 0x1c 0x8d # CHECK: addqh_r.w $3, $4, $5
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0x00 0xa4 0x19 0x0d # CHECK: addu.ph $3, $4, $5
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0x00 0xa4 0x1d 0x0d # CHECK: addu_s.ph $3, $4, $5
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0x00 0xa4 0x19 0x4d # CHECK: adduh.qb $3, $4, $5
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0x00 0xa4 0x1d 0x4d # CHECK: adduh_r.qb $3, $4, $5
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0x00 0x64 0x01 0x3c # CHECK: absq_s.qb $3, $4
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0x00 0x43 0x00 0xbc # CHECK: dpa.w.ph $ac0, $3, $2
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0x00 0xec 0xe2 0xbc # CHECK: dpaqx_s.w.ph $ac3, $12, $7
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@ -2,6 +2,12 @@
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.set noat
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addu.qb $3, $4, $5 # CHECK: addu.qb $3, $4, $5 # encoding: [0x00,0xa4,0x18,0xcd]
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addu_s.qb $3, $4, $5 # CHECK: addu_s.qb $3, $4, $5 # encoding: [0x00,0xa4,0x1c,0xcd]
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addsc $3, $4, $5 # CHECK: addsc $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x85]
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addwc $3, $4, $5 # CHECK: addwc $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0xc5]
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addq.ph $3, $4, $5 # CHECK: addq.ph $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x0d]
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addq_s.ph $3, $4, $5 # CHECK: addq_s.ph $3, $4, $5 # encoding: [0x00,0xa4,0x1c,0x0d]
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addq_s.w $3, $4, $5 # CHECK: addq_s.w $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x05]
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dpaq_s.w.ph $ac1, $5, $3 # CHECK: dpaq_s.w.ph $ac1, $5, $3 # encoding: [0x00,0x65,0x42,0xbc]
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dpaq_sa.l.w $ac2, $4, $3 # CHECK: dpaq_sa.l.w $ac2, $4, $3 # encoding: [0x00,0x64,0x92,0xbc]
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dpau.h.qbl $ac1, $3, $4 # CHECK: dpau.h.qbl $ac1, $3, $4 # encoding: [0x00,0x83,0x60,0xbc]
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@ -1,6 +1,14 @@
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# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dspr2 | FileCheck %s
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.set noat
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addqh.ph $3, $4, $5 # CHECK: addqh.ph $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x4d]
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addqh_r.ph $3, $4, $5 # CHECK: addqh_r.ph $3, $4, $5 # encoding: [0x00,0xa4,0x1c,0x4d]
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addqh.w $3, $4, $5 # CHECK: addqh.w $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x8d]
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addqh_r.w $3, $4, $5 # CHECK: addqh_r.w $3, $4, $5 # encoding: [0x00,0xa4,0x1c,0x8d]
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addu.ph $3, $4, $5 # CHECK: addu.ph $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x0d]
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addu_s.ph $3, $4, $5 # CHECK: addu_s.ph $3, $4, $5 # encoding: [0x00,0xa4,0x1d,0x0d]
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adduh.qb $3, $4, $5 # CHECK: adduh.qb $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x4d]
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adduh_r.qb $3, $4, $5 # CHECK: adduh_r.qb $3, $4, $5 # encoding: [0x00,0xa4,0x1d,0x4d]
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absq_s.qb $3, $4 # CHECK: absq_s.qb $3, $4 # encoding: [0x00,0x64,0x01,0x3c]
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dpa.w.ph $ac0, $3, $2 # CHECK: dpa.w.ph $ac0, $3, $2 # encoding: [0x00,0x43,0x00,0xbc]
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dpaqx_s.w.ph $ac3, $12, $7 # CHECK: dpaqx_s.w.ph $ac3, $12, $7 # encoding: [0x00,0xec,0xe2,0xbc]
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