forked from OSchip/llvm-project
parent
5f865032db
commit
5291df3c98
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@ -38,7 +38,7 @@ class Scheduler;
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// the following conditions are met:
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// the following conditions are met:
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// 1) There are enough entries in the reorder buffer (see class
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// 1) There are enough entries in the reorder buffer (see class
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// RetireControlUnit) to write the opcodes associated with the instruction.
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// RetireControlUnit) to write the opcodes associated with the instruction.
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// 2) There are enough temporaries to rename output register operands.
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// 2) There are enough physical registers to rename output register operands.
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// 3) There are enough entries available in the used buffered resource(s).
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// 3) There are enough entries available in the used buffered resource(s).
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//
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//
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// The number of micro opcodes that can be dispatched in one cycle is limited by
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// The number of micro opcodes that can be dispatched in one cycle is limited by
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@ -31,7 +31,7 @@ namespace mca {
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/// this RetireControlUnit (RCU) gets notified.
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/// this RetireControlUnit (RCU) gets notified.
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///
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///
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/// On instruction retired, register updates are all architecturally
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/// On instruction retired, register updates are all architecturally
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/// committed, and any temporary registers originally allocated for the
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/// committed, and any physicall registers previously allocated for the
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/// retired instruction are freed.
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/// retired instruction are freed.
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struct RetireControlUnit : public HardwareUnit {
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struct RetireControlUnit : public HardwareUnit {
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// A RUToken is created by the RCU for every instruction dispatched to the
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// A RUToken is created by the RCU for every instruction dispatched to the
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