diff --git a/llvm/tools/llvm-mca/DispatchStage.h b/llvm/tools/llvm-mca/DispatchStage.h
index f21789a29c50..4262a241c08c 100644
--- a/llvm/tools/llvm-mca/DispatchStage.h
+++ b/llvm/tools/llvm-mca/DispatchStage.h
@@ -38,7 +38,7 @@ class Scheduler;
 // the following conditions are met:
 //  1) There are enough entries in the reorder buffer (see class
 //     RetireControlUnit) to write the opcodes associated with the instruction.
-//  2) There are enough temporaries to rename output register operands.
+//  2) There are enough physical registers to rename output register operands.
 //  3) There are enough entries available in the used buffered resource(s).
 //
 // The number of micro opcodes that can be dispatched in one cycle is limited by
diff --git a/llvm/tools/llvm-mca/RetireControlUnit.h b/llvm/tools/llvm-mca/RetireControlUnit.h
index 3530ff21ba0d..8acc8bcc98fe 100644
--- a/llvm/tools/llvm-mca/RetireControlUnit.h
+++ b/llvm/tools/llvm-mca/RetireControlUnit.h
@@ -31,7 +31,7 @@ namespace mca {
 /// this RetireControlUnit (RCU) gets notified.
 ///
 /// On instruction retired, register updates are all architecturally
-/// committed, and any temporary registers originally allocated for the
+/// committed, and any physicall registers previously allocated for the
 /// retired instruction are freed.
 struct RetireControlUnit : public HardwareUnit {
   // A RUToken is created by the RCU for every instruction dispatched to the