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[AArch64] Block tryCombineToBSL combines for vectors wider than NEON 

There are no patterns for the AArch64ISD::BSP ISD node for anything
other than NEON vectors at the moment. As a result, if we hit these
combines for vectors wider than a NEON vector (such as what we might get
with fixed length SVE) we will fail to lower.

This patch simply prevents us from attempting the combines if the input
vector type is too wide.

Reviewed By: peterwaller-arm

Differential Revision: https://reviews.llvm.org/D100961
This commit is contained in:
Joe Ellis 2021-04-22 15:07:26 +00:00
parent ca70512099
commit 528ee161c9
2 changed files with 34 additions and 0 deletions
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5
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -12592,6 +12592,11 @@ static SDValue tryCombineToBSL(SDNode *N,
if (!VT.isVector()) if (!VT.isVector())
return SDValue(); return SDValue();
// The combining code currently only works for NEON vectors. In particular,
// it does not work for SVE when dealing with vectors wider than 128 bits.
if (!VT.is64BitVector() && !VT.is128BitVector())
return SDValue();
SDValue N0 = N->getOperand(0); SDValue N0 = N->getOperand(0);
if (N0.getOpcode() != ISD::AND) if (N0.getOpcode() != ISD::AND)
return SDValue(); return SDValue();

29
llvm/test/CodeGen/AArch64/sve-fixed-length-bitselect.ll Normal file
View File

@ -0,0 +1,29 @@
; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s
target triple = "aarch64"
;
; NOTE: SVE lowering for the BSP pseudoinst is not currently implemented, so we
; don't currently expect the code below to lower to BSL/BIT/BIF. Once
; this is implemented, this test will be fleshed out.
;
define <8 x i32> @fixed_bitselect_v8i32(<8 x i32>* %pre_cond_ptr, <8 x i32>* %left_ptr, <8 x i32>* %right_ptr) #0 {
; CHECK-LABEL: fixed_bitselect_v8i32:
; CHECK-NOT: bsl {{.*}}, {{.*}}, {{.*}}
; CHECK-NOT: bit {{.*}}, {{.*}}, {{.*}}
; CHECK-NOT: bif {{.*}}, {{.*}}, {{.*}}
; CHECK: ret
%pre_cond = load <8 x i32>, <8 x i32>* %pre_cond_ptr
%left = load <8 x i32>, <8 x i32>* %left_ptr
%right = load <8 x i32>, <8 x i32>* %right_ptr
%neg_cond = sub <8 x i32> zeroinitializer, %pre_cond
%min_cond = add <8 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
%left_bits_0 = and <8 x i32> %neg_cond, %left
%right_bits_0 = and <8 x i32> %min_cond, %right
%bsl0000 = or <8 x i32> %right_bits_0, %left_bits_0
ret <8 x i32> %bsl0000
}
attributes #0 = { "target-features"="+sve" }