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Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. 

llvm-svn: 119990
This commit is contained in:
Wesley Peck 2010-11-23 03:31:01 +00:00
parent 4329e078ac
commit 527da1b6e2
30 changed files with 1142 additions and 1145 deletions
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2
llvm/docs/WritingAnLLVMBackend.html
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@ -1825,7 +1825,7 @@ register to convert the floating-point value to an integer.
static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
assert(Op.getValueType() == MVT::i32); assert(Op.getValueType() == MVT::i32);
Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0)); Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); return DAG.getNode(ISD::BITCAST, MVT::i32, Op);
} }
</pre> </pre>
</div> </div>

4
llvm/include/llvm/CodeGen/ISDOpcodes.h
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@ -399,14 +399,14 @@ namespace ISD {
/// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type. /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
FP_EXTEND, FP_EXTEND,
// BIT_CONVERT - This operator converts between integer, vector and FP // BITCAST - This operator converts between integer, vector and FP
// values, as if the value was stored to memory with one type and loaded // values, as if the value was stored to memory with one type and loaded
// from the same address with the other type (or equivalently for vector // from the same address with the other type (or equivalently for vector
// format conversions, etc). The source and result are required to have // format conversions, etc). The source and result are required to have
// the same bit size (e.g. f32 <-> i32). This can also be used for // the same bit size (e.g. f32 <-> i32). This can also be used for
// int-to-int or fp-to-fp conversions, but that is a noop, deleted by // int-to-int or fp-to-fp conversions, but that is a noop, deleted by
// getNode(). // getNode().
BIT_CONVERT, BITCAST,
// CONVERT_RNDSAT - This operator is used to support various conversions // CONVERT_RNDSAT - This operator is used to support various conversions
// between various types (float, signed, unsigned and vectors of those // between various types (float, signed, unsigned and vectors of those

2
llvm/include/llvm/Target/TargetSelectionDAG.td
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@ -329,7 +329,7 @@ def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>; def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>; def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>; def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>; def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>;
def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>; def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>; def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;

60
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -185,7 +185,7 @@ namespace {
SDValue visitANY_EXTEND(SDNode *N); SDValue visitANY_EXTEND(SDNode *N);
SDValue visitSIGN_EXTEND_INREG(SDNode *N); SDValue visitSIGN_EXTEND_INREG(SDNode *N);
SDValue visitTRUNCATE(SDNode *N); SDValue visitTRUNCATE(SDNode *N);
SDValue visitBIT_CONVERT(SDNode *N); SDValue visitBITCAST(SDNode *N);
SDValue visitBUILD_PAIR(SDNode *N); SDValue visitBUILD_PAIR(SDNode *N);
SDValue visitFADD(SDNode *N); SDValue visitFADD(SDNode *N);
SDValue visitFSUB(SDNode *N); SDValue visitFSUB(SDNode *N);
@ -229,7 +229,7 @@ namespace {
SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
unsigned HiOp); unsigned HiOp);
SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, EVT); SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
SDValue BuildSDIV(SDNode *N); SDValue BuildSDIV(SDNode *N);
SDValue BuildUDIV(SDNode *N); SDValue BuildUDIV(SDNode *N);
SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
@ -1057,7 +1057,7 @@ SDValue DAGCombiner::visit(SDNode *N) {
case ISD::ANY_EXTEND: return visitANY_EXTEND(N); case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
case ISD::TRUNCATE: return visitTRUNCATE(N); case ISD::TRUNCATE: return visitTRUNCATE(N);
case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); case ISD::BITCAST: return visitBITCAST(N);
case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
case ISD::FADD: return visitFADD(N); case ISD::FADD: return visitFADD(N);
case ISD::FSUB: return visitFSUB(N); case ISD::FSUB: return visitFSUB(N);
@ -4379,7 +4379,7 @@ SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
return SDValue(); return SDValue();
} }
SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { SDValue DAGCombiner::visitBITCAST(SDNode *N) {
SDValue N0 = N->getOperand(0); SDValue N0 = N->getOperand(0);
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
@ -4403,12 +4403,12 @@ SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
assert(!DestEltVT.isVector() && assert(!DestEltVT.isVector() &&
"Element type of vector ValueType must not be vector!"); "Element type of vector ValueType must not be vector!");
if (isSimple) if (isSimple)
return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
} }
// If the input is a constant, let getNode fold it. // If the input is a constant, let getNode fold it.
if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0); SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0);
if (Res.getNode() != N) { if (Res.getNode() != N) {
if (!LegalOperations || if (!LegalOperations ||
TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
@ -4424,8 +4424,8 @@ SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
} }
// (conv (conv x, t1), t2) -> (conv x, t2) // (conv (conv x, t1), t2) -> (conv x, t2)
if (N0.getOpcode() == ISD::BIT_CONVERT) if (N0.getOpcode() == ISD::BITCAST)
return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT,
N0.getOperand(0)); N0.getOperand(0));
// fold (conv (load x)) -> (load (conv*)x) // fold (conv (load x)) -> (load (conv*)x)
@ -4446,7 +4446,7 @@ SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
OrigAlign); OrigAlign);
AddToWorkList(N); AddToWorkList(N);
CombineTo(N0.getNode(), CombineTo(N0.getNode(),
DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
N0.getValueType(), Load), N0.getValueType(), Load),
Load.getValue(1)); Load.getValue(1));
return Load; return Load;
@ -4458,7 +4458,7 @@ SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
// This often reduces constant pool loads. // This often reduces constant pool loads.
if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT, SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT,
N0.getOperand(0)); N0.getOperand(0));
AddToWorkList(NewConv.getNode()); AddToWorkList(NewConv.getNode());
@ -4481,7 +4481,7 @@ SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
if (isTypeLegal(IntXVT)) { if (isTypeLegal(IntXVT)) {
SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
IntXVT, N0.getOperand(1)); IntXVT, N0.getOperand(1));
AddToWorkList(X.getNode()); AddToWorkList(X.getNode());
@ -4506,7 +4506,7 @@ SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
X, DAG.getConstant(SignBit, VT)); X, DAG.getConstant(SignBit, VT));
AddToWorkList(X.getNode()); AddToWorkList(X.getNode());
SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
VT, N0.getOperand(0)); VT, N0.getOperand(0));
Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
Cst, DAG.getConstant(~SignBit, VT)); Cst, DAG.getConstant(~SignBit, VT));
@ -4531,11 +4531,11 @@ SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
return CombineConsecutiveLoads(N, VT); return CombineConsecutiveLoads(N, VT);
} }
/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector /// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector
/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
/// destination element value type. /// destination element value type.
SDValue DAGCombiner:: SDValue DAGCombiner::
ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
// If this is already the right type, we're done. // If this is already the right type, we're done.
@ -4554,7 +4554,7 @@ ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
// we can end up with a scalar-to-vector node here. // we can end up with a scalar-to-vector node here.
if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(), DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
DstEltVT, BV->getOperand(0))); DstEltVT, BV->getOperand(0)));
SmallVector<SDValue, 8> Ops; SmallVector<SDValue, 8> Ops;
@ -4564,7 +4564,7 @@ ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
// are promoted and implicitly truncated. Make that explicit here. // are promoted and implicitly truncated. Make that explicit here.
if (Op.getValueType() != SrcEltVT) if (Op.getValueType() != SrcEltVT)
Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(), Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
DstEltVT, Op)); DstEltVT, Op));
AddToWorkList(Ops.back().getNode()); AddToWorkList(Ops.back().getNode());
} }
@ -4580,7 +4580,7 @@ ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
// same sizes. // same sizes.
assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode();
SrcEltVT = IntVT; SrcEltVT = IntVT;
} }
@ -4589,10 +4589,10 @@ ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
if (DstEltVT.isFloatingPoint()) { if (DstEltVT.isFloatingPoint()) {
assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode();
// Next, convert to FP elements of the same size. // Next, convert to FP elements of the same size.
return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT);
} }
// Okay, we know the src/dst types are both integers of differing types. // Okay, we know the src/dst types are both integers of differing types.
@ -5068,7 +5068,7 @@ SDValue DAGCombiner::visitFNEG(SDNode *N) {
// Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
// constant pool values. // constant pool values.
if (N0.getOpcode() == ISD::BIT_CONVERT && if (N0.getOpcode() == ISD::BITCAST &&
!VT.isVector() && !VT.isVector() &&
N0.getNode()->hasOneUse() && N0.getNode()->hasOneUse() &&
N0.getOperand(0).getValueType().isInteger()) { N0.getOperand(0).getValueType().isInteger()) {
@ -5078,7 +5078,7 @@ SDValue DAGCombiner::visitFNEG(SDNode *N) {
Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
AddToWorkList(Int.getNode()); AddToWorkList(Int.getNode());
return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
VT, Int); VT, Int);
} }
} }
@ -5104,7 +5104,7 @@ SDValue DAGCombiner::visitFABS(SDNode *N) {
// Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
// constant pool values. // constant pool values.
if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && if (N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() &&
N0.getOperand(0).getValueType().isInteger() && N0.getOperand(0).getValueType().isInteger() &&
!N0.getOperand(0).getValueType().isVector()) { !N0.getOperand(0).getValueType().isVector()) {
SDValue Int = N0.getOperand(0); SDValue Int = N0.getOperand(0);
@ -5113,7 +5113,7 @@ SDValue DAGCombiner::visitFABS(SDNode *N) {
Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
AddToWorkList(Int.getNode()); AddToWorkList(Int.getNode());
return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
N->getValueType(0), Int); N->getValueType(0), Int);
} }
} }
@ -5944,7 +5944,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
// If this is a store of a bit convert, store the input value if the // If this is a store of a bit convert, store the input value if the
// resultant store does not need a higher alignment than the original. // resultant store does not need a higher alignment than the original.
if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
ST->isUnindexed()) { ST->isUnindexed()) {
unsigned OrigAlign = ST->getAlignment(); unsigned OrigAlign = ST->getAlignment();
EVT SVT = Value.getOperand(0).getValueType(); EVT SVT = Value.getOperand(0).getValueType();
@ -6198,7 +6198,7 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
EVT ExtVT = VT.getVectorElementType(); EVT ExtVT = VT.getVectorElementType();
EVT LVT = ExtVT; EVT LVT = ExtVT;
if (InVec.getOpcode() == ISD::BIT_CONVERT) { if (InVec.getOpcode() == ISD::BITCAST) {
EVT BCVT = InVec.getOperand(0).getValueType(); EVT BCVT = InVec.getOperand(0).getValueType();
if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
return SDValue(); return SDValue();
@ -6232,7 +6232,7 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt);
InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
if (InVec.getOpcode() == ISD::BIT_CONVERT) if (InVec.getOpcode() == ISD::BITCAST)
InVec = InVec.getOperand(0); InVec = InVec.getOperand(0);
if (ISD::isNormalLoad(InVec.getNode())) { if (ISD::isNormalLoad(InVec.getNode())) {
LN0 = cast<LoadSDNode>(InVec); LN0 = cast<LoadSDNode>(InVec);
@ -6396,7 +6396,7 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
// If this is a bit convert that changes the element type of the vector but // If this is a bit convert that changes the element type of the vector but
// not the number of vector elements, look through it. Be careful not to // not the number of vector elements, look through it. Be careful not to
// look though conversions that change things like v4f32 to v2f64. // look though conversions that change things like v4f32 to v2f64.
if (V->getOpcode() == ISD::BIT_CONVERT) { if (V->getOpcode() == ISD::BITCAST) {
SDValue ConvInput = V->getOperand(0); SDValue ConvInput = V->getOperand(0);
if (ConvInput.getValueType().isVector() && if (ConvInput.getValueType().isVector() &&
ConvInput.getValueType().getVectorNumElements() == NumElts) ConvInput.getValueType().getVectorNumElements() == NumElts)
@ -6494,7 +6494,7 @@ SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
SDValue LHS = N->getOperand(0); SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1); SDValue RHS = N->getOperand(1);
if (N->getOpcode() == ISD::AND) { if (N->getOpcode() == ISD::AND) {
if (RHS.getOpcode() == ISD::BIT_CONVERT) if (RHS.getOpcode() == ISD::BITCAST)
RHS = RHS.getOperand(0); RHS = RHS.getOperand(0);
if (RHS.getOpcode() == ISD::BUILD_VECTOR) { if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
SmallVector<int, 8> Indices; SmallVector<int, 8> Indices;
@ -6522,9 +6522,9 @@ SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
DAG.getConstant(0, EltVT)); DAG.getConstant(0, EltVT));
SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
RVT, &ZeroOps[0], ZeroOps.size()); RVT, &ZeroOps[0], ZeroOps.size());
LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS); LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf); return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
} }
} }

10
llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
View File

@ -656,7 +656,7 @@ bool FastISel::SelectBitCast(const User *I) {
return true; return true;
} }
// Bitcasts of other values become reg-reg copies or BIT_CONVERT operators. // Bitcasts of other values become reg-reg copies or BITCAST operators.
EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
EVT DstVT = TLI.getValueType(I->getType()); EVT DstVT = TLI.getValueType(I->getType());
@ -686,10 +686,10 @@ bool FastISel::SelectBitCast(const User *I) {
} }
} }
// If the reg-reg copy failed, select a BIT_CONVERT opcode. // If the reg-reg copy failed, select a BITCAST opcode.
if (!ResultReg) if (!ResultReg)
ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
ISD::BIT_CONVERT, Op0, Op0IsKill); ISD::BITCAST, Op0, Op0IsKill);
if (!ResultReg) if (!ResultReg)
return false; return false;
@ -765,7 +765,7 @@ FastISel::SelectFNeg(const User *I) {
return false; return false;
unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
ISD::BIT_CONVERT, OpReg, OpRegIsKill); ISD::BITCAST, OpReg, OpRegIsKill);
if (IntReg == 0) if (IntReg == 0)
return false; return false;
@ -777,7 +777,7 @@ FastISel::SelectFNeg(const User *I) {
return false; return false;
ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(),
ISD::BIT_CONVERT, IntResultReg, /*Kill=*/true); ISD::BITCAST, IntResultReg, /*Kill=*/true);
if (ResultReg == 0) if (ResultReg == 0)
return false; return false;

32
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -403,7 +403,7 @@ SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
// Expand to a bitconvert of the value to the integer type of the // Expand to a bitconvert of the value to the integer type of the
// same size, then a (misaligned) int store. // same size, then a (misaligned) int store.
// FIXME: Does not handle truncating floating point stores! // FIXME: Does not handle truncating floating point stores!
SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val); SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
return DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(), return DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
ST->isVolatile(), ST->isNonTemporal(), Alignment); ST->isVolatile(), ST->isNonTemporal(), Alignment);
} else { } else {
@ -515,7 +515,7 @@ SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(), SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(),
LD->isVolatile(), LD->isVolatile(),
LD->isNonTemporal(), LD->getAlignment()); LD->isNonTemporal(), LD->getAlignment());
SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad); SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
if (VT.isFloatingPoint() && LoadedVT != VT) if (VT.isFloatingPoint() && LoadedVT != VT)
Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result); Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
@ -1145,7 +1145,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(), Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(),
LD->isVolatile(), LD->isNonTemporal(), LD->isVolatile(), LD->isNonTemporal(),
LD->getAlignment()); LD->getAlignment());
Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1)); Tmp3 = LegalizeOp(DAG.getNode(ISD::BITCAST, dl, VT, Tmp1));
Tmp4 = LegalizeOp(Tmp1.getValue(1)); Tmp4 = LegalizeOp(Tmp1.getValue(1));
break; break;
} }
@ -1410,7 +1410,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
break; break;
case TargetLowering::Promote: case TargetLowering::Promote:
assert(VT.isVector() && "Unknown legal promote case!"); assert(VT.isVector() && "Unknown legal promote case!");
Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl, Tmp3 = DAG.getNode(ISD::BITCAST, dl,
TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
ST->getPointerInfo(), isVolatile, ST->getPointerInfo(), isVolatile,
@ -1629,7 +1629,7 @@ SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits()); EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
if (isTypeLegal(IVT)) { if (isTypeLegal(IVT)) {
// Convert to an integer with the same sign bit. // Convert to an integer with the same sign bit.
SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2); SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
} else { } else {
// Store the float to memory, then load the sign part out as an integer. // Store the float to memory, then load the sign part out as an integer.
MVT LoadTy = TLI.getPointerTy(); MVT LoadTy = TLI.getPointerTy();
@ -2120,8 +2120,8 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
DAG.getConstant(32, MVT::i64)); DAG.getConstant(32, MVT::i64));
SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52); SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84); SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
SDValue LoFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, LoOr); SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
SDValue HiFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, HiOr); SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt, SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
TwoP84PlusTwoP52); TwoP84PlusTwoP52);
return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub); return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
@ -2617,7 +2617,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
break; break;
} }
case ISD::FP_ROUND: case ISD::FP_ROUND:
case ISD::BIT_CONVERT: case ISD::BITCAST:
Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
Node->getValueType(0), dl); Node->getValueType(0), dl);
Results.push_back(Tmp1); Results.push_back(Tmp1);
@ -2739,7 +2739,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
case ISD::EXTRACT_VECTOR_ELT: case ISD::EXTRACT_VECTOR_ELT:
if (Node->getOperand(0).getValueType().getVectorNumElements() == 1) if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
// This must be an access of the only element. Return it. // This must be an access of the only element. Return it.
Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
Node->getOperand(0)); Node->getOperand(0));
else else
Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0)); Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
@ -3361,8 +3361,8 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node,
case ISD::XOR: { case ISD::XOR: {
unsigned ExtOp, TruncOp; unsigned ExtOp, TruncOp;
if (OVT.isVector()) { if (OVT.isVector()) {
ExtOp = ISD::BIT_CONVERT; ExtOp = ISD::BITCAST;
TruncOp = ISD::BIT_CONVERT; TruncOp = ISD::BITCAST;
} else { } else {
assert(OVT.isInteger() && "Cannot promote logic operation"); assert(OVT.isInteger() && "Cannot promote logic operation");
ExtOp = ISD::ANY_EXTEND; ExtOp = ISD::ANY_EXTEND;
@ -3379,8 +3379,8 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node,
case ISD::SELECT: { case ISD::SELECT: {
unsigned ExtOp, TruncOp; unsigned ExtOp, TruncOp;
if (Node->getValueType(0).isVector()) { if (Node->getValueType(0).isVector()) {
ExtOp = ISD::BIT_CONVERT; ExtOp = ISD::BITCAST;
TruncOp = ISD::BIT_CONVERT; TruncOp = ISD::BITCAST;
} else if (Node->getValueType(0).isInteger()) { } else if (Node->getValueType(0).isInteger()) {
ExtOp = ISD::ANY_EXTEND; ExtOp = ISD::ANY_EXTEND;
TruncOp = ISD::TRUNCATE; TruncOp = ISD::TRUNCATE;
@ -3407,12 +3407,12 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node,
cast<ShuffleVectorSDNode>(Node)->getMask(Mask); cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
// Cast the two input vectors. // Cast the two input vectors.
Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1)); Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
// Convert the shuffle mask to the right # elements. // Convert the shuffle mask to the right # elements.
Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask); Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1); Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
Results.push_back(Tmp1); Results.push_back(Tmp1);
break; break;
} }

14
llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
View File

@ -55,7 +55,7 @@ void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) {
#endif #endif
llvm_unreachable("Do not know how to soften the result of this operator!"); llvm_unreachable("Do not know how to soften the result of this operator!");
case ISD::BIT_CONVERT: R = SoftenFloatRes_BIT_CONVERT(N); break; case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N); break;
case ISD::BUILD_PAIR: R = SoftenFloatRes_BUILD_PAIR(N); break; case ISD::BUILD_PAIR: R = SoftenFloatRes_BUILD_PAIR(N); break;
case ISD::ConstantFP: case ISD::ConstantFP:
R = SoftenFloatRes_ConstantFP(cast<ConstantFPSDNode>(N)); R = SoftenFloatRes_ConstantFP(cast<ConstantFPSDNode>(N));
@ -102,7 +102,7 @@ void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) {
SetSoftenedFloat(SDValue(N, ResNo), R); SetSoftenedFloat(SDValue(N, ResNo), R);
} }
SDValue DAGTypeLegalizer::SoftenFloatRes_BIT_CONVERT(SDNode *N) { SDValue DAGTypeLegalizer::SoftenFloatRes_BITCAST(SDNode *N) {
return BitConvertToInteger(N->getOperand(0)); return BitConvertToInteger(N->getOperand(0));
} }
@ -557,7 +557,7 @@ bool DAGTypeLegalizer::SoftenFloatOperand(SDNode *N, unsigned OpNo) {
#endif #endif
llvm_unreachable("Do not know how to soften this operator's operand!"); llvm_unreachable("Do not know how to soften this operator's operand!");
case ISD::BIT_CONVERT: Res = SoftenFloatOp_BIT_CONVERT(N); break; case ISD::BITCAST: Res = SoftenFloatOp_BITCAST(N); break;
case ISD::BR_CC: Res = SoftenFloatOp_BR_CC(N); break; case ISD::BR_CC: Res = SoftenFloatOp_BR_CC(N); break;
case ISD::FP_ROUND: Res = SoftenFloatOp_FP_ROUND(N); break; case ISD::FP_ROUND: Res = SoftenFloatOp_FP_ROUND(N); break;
case ISD::FP_TO_SINT: Res = SoftenFloatOp_FP_TO_SINT(N); break; case ISD::FP_TO_SINT: Res = SoftenFloatOp_FP_TO_SINT(N); break;
@ -669,8 +669,8 @@ void DAGTypeLegalizer::SoftenSetCCOperands(SDValue &NewLHS, SDValue &NewRHS,
} }
} }
SDValue DAGTypeLegalizer::SoftenFloatOp_BIT_CONVERT(SDNode *N) { SDValue DAGTypeLegalizer::SoftenFloatOp_BITCAST(SDNode *N) {
return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), N->getValueType(0), return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), N->getValueType(0),
GetSoftenedFloat(N->getOperand(0))); GetSoftenedFloat(N->getOperand(0)));
} }
@ -815,7 +815,7 @@ void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) {
case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break; case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break; case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
@ -1220,7 +1220,7 @@ bool DAGTypeLegalizer::ExpandFloatOperand(SDNode *N, unsigned OpNo) {
#endif #endif
llvm_unreachable("Do not know how to expand this operator's operand!"); llvm_unreachable("Do not know how to expand this operator's operand!");
case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break; case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break; case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;

21
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -49,7 +49,7 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
llvm_unreachable("Do not know how to promote this operator!"); llvm_unreachable("Do not know how to promote this operator!");
case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
case ISD::BIT_CONVERT: Res = PromoteIntRes_BIT_CONVERT(N); break; case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break; case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
case ISD::Constant: Res = PromoteIntRes_Constant(N); break; case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
@ -162,7 +162,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
return Res; return Res;
} }
SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) { SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
SDValue InOp = N->getOperand(0); SDValue InOp = N->getOperand(0);
EVT InVT = InOp.getValueType(); EVT InVT = InOp.getValueType();
EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
@ -179,8 +179,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
case PromoteInteger: case PromoteInteger:
if (NOutVT.bitsEq(NInVT)) if (NOutVT.bitsEq(NInVT))
// The input promotes to the same size. Convert the promoted value. // The input promotes to the same size. Convert the promoted value.
return DAG.getNode(ISD::BIT_CONVERT, dl, return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
NOutVT, GetPromotedInteger(InOp));
break; break;
case SoftenFloat: case SoftenFloat:
// Promote the integer operand by hand. // Promote the integer operand by hand.
@ -193,7 +192,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
BitConvertToInteger(GetScalarizedVector(InOp))); BitConvertToInteger(GetScalarizedVector(InOp)));
case SplitVector: { case SplitVector: {
// For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split // For example, i32 = BITCAST v2i16 on alpha. Convert the split
// pieces of the input into integers and reassemble in the final type. // pieces of the input into integers and reassemble in the final type.
SDValue Lo, Hi; SDValue Lo, Hi;
GetSplitVector(N->getOperand(0), Lo, Hi); GetSplitVector(N->getOperand(0), Lo, Hi);
@ -207,12 +206,12 @@ SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
EVT::getIntegerVT(*DAG.getContext(), EVT::getIntegerVT(*DAG.getContext(),
NOutVT.getSizeInBits()), NOutVT.getSizeInBits()),
JoinIntegers(Lo, Hi)); JoinIntegers(Lo, Hi));
return DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, InOp); return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
} }
case WidenVector: case WidenVector:
if (OutVT.bitsEq(NInVT)) if (OutVT.bitsEq(NInVT))
// The input is widened to the same size. Convert to the widened value. // The input is widened to the same size. Convert to the widened value.
return DAG.getNode(ISD::BIT_CONVERT, dl, OutVT, GetWidenedVector(InOp)); return DAG.getNode(ISD::BITCAST, dl, OutVT, GetWidenedVector(InOp));
} }
return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
@ -631,7 +630,7 @@ bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
llvm_unreachable("Do not know how to promote this operator's operand!"); llvm_unreachable("Do not know how to promote this operator's operand!");
case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
case ISD::BIT_CONVERT: Res = PromoteIntOp_BIT_CONVERT(N); break; case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break; case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
@ -713,7 +712,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op); return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op);
} }
SDValue DAGTypeLegalizer::PromoteIntOp_BIT_CONVERT(SDNode *N) { SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
// This should only occur in unusual situations like bitcasting to an // This should only occur in unusual situations like bitcasting to an
// x86_fp80, so just turn it into a store+load // x86_fp80, so just turn it into a store+load
return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0)); return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
@ -950,7 +949,7 @@ void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break; case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break; case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
@ -2076,7 +2075,7 @@ bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
#endif #endif
llvm_unreachable("Do not know how to expand this operator's operand!"); llvm_unreachable("Do not know how to expand this operator's operand!");
case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break; case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break; case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break; case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;

4
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
View File

@ -858,7 +858,7 @@ void DAGTypeLegalizer::SetWidenedVector(SDValue Op, SDValue Result) {
/// BitConvertToInteger - Convert to an integer of the same size. /// BitConvertToInteger - Convert to an integer of the same size.
SDValue DAGTypeLegalizer::BitConvertToInteger(SDValue Op) { SDValue DAGTypeLegalizer::BitConvertToInteger(SDValue Op) {
unsigned BitWidth = Op.getValueType().getSizeInBits(); unsigned BitWidth = Op.getValueType().getSizeInBits();
return DAG.getNode(ISD::BIT_CONVERT, Op.getDebugLoc(), return DAG.getNode(ISD::BITCAST, Op.getDebugLoc(),
EVT::getIntegerVT(*DAG.getContext(), BitWidth), Op); EVT::getIntegerVT(*DAG.getContext(), BitWidth), Op);
} }
@ -869,7 +869,7 @@ SDValue DAGTypeLegalizer::BitConvertVectorToIntegerVector(SDValue Op) {
unsigned EltWidth = Op.getValueType().getVectorElementType().getSizeInBits(); unsigned EltWidth = Op.getValueType().getVectorElementType().getSizeInBits();
EVT EltNVT = EVT::getIntegerVT(*DAG.getContext(), EltWidth); EVT EltNVT = EVT::getIntegerVT(*DAG.getContext(), EltWidth);
unsigned NumElts = Op.getValueType().getVectorNumElements(); unsigned NumElts = Op.getValueType().getVectorNumElements();
return DAG.getNode(ISD::BIT_CONVERT, Op.getDebugLoc(), return DAG.getNode(ISD::BITCAST, Op.getDebugLoc(),
EVT::getVectorVT(*DAG.getContext(), EltNVT, NumElts), Op); EVT::getVectorVT(*DAG.getContext(), EltNVT, NumElts), Op);
} }

26
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
View File

@ -244,7 +244,7 @@ private:
SDValue PromoteIntRes_AssertZext(SDNode *N); SDValue PromoteIntRes_AssertZext(SDNode *N);
SDValue PromoteIntRes_Atomic1(AtomicSDNode *N); SDValue PromoteIntRes_Atomic1(AtomicSDNode *N);
SDValue PromoteIntRes_Atomic2(AtomicSDNode *N); SDValue PromoteIntRes_Atomic2(AtomicSDNode *N);
SDValue PromoteIntRes_BIT_CONVERT(SDNode *N); SDValue PromoteIntRes_BITCAST(SDNode *N);
SDValue PromoteIntRes_BSWAP(SDNode *N); SDValue PromoteIntRes_BSWAP(SDNode *N);
SDValue PromoteIntRes_BUILD_PAIR(SDNode *N); SDValue PromoteIntRes_BUILD_PAIR(SDNode *N);
SDValue PromoteIntRes_Constant(SDNode *N); SDValue PromoteIntRes_Constant(SDNode *N);
@ -278,7 +278,7 @@ private:
// Integer Operand Promotion. // Integer Operand Promotion.
bool PromoteIntegerOperand(SDNode *N, unsigned OperandNo); bool PromoteIntegerOperand(SDNode *N, unsigned OperandNo);
SDValue PromoteIntOp_ANY_EXTEND(SDNode *N); SDValue PromoteIntOp_ANY_EXTEND(SDNode *N);
SDValue PromoteIntOp_BIT_CONVERT(SDNode *N); SDValue PromoteIntOp_BITCAST(SDNode *N);
SDValue PromoteIntOp_BUILD_PAIR(SDNode *N); SDValue PromoteIntOp_BUILD_PAIR(SDNode *N);
SDValue PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo); SDValue PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo);
SDValue PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo); SDValue PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo);
@ -352,7 +352,7 @@ private:
// Integer Operand Expansion. // Integer Operand Expansion.
bool ExpandIntegerOperand(SDNode *N, unsigned OperandNo); bool ExpandIntegerOperand(SDNode *N, unsigned OperandNo);
SDValue ExpandIntOp_BIT_CONVERT(SDNode *N); SDValue ExpandIntOp_BITCAST(SDNode *N);
SDValue ExpandIntOp_BR_CC(SDNode *N); SDValue ExpandIntOp_BR_CC(SDNode *N);
SDValue ExpandIntOp_BUILD_VECTOR(SDNode *N); SDValue ExpandIntOp_BUILD_VECTOR(SDNode *N);
SDValue ExpandIntOp_EXTRACT_ELEMENT(SDNode *N); SDValue ExpandIntOp_EXTRACT_ELEMENT(SDNode *N);
@ -387,7 +387,7 @@ private:
// Result Float to Integer Conversion. // Result Float to Integer Conversion.
void SoftenFloatResult(SDNode *N, unsigned OpNo); void SoftenFloatResult(SDNode *N, unsigned OpNo);
SDValue SoftenFloatRes_BIT_CONVERT(SDNode *N); SDValue SoftenFloatRes_BITCAST(SDNode *N);
SDValue SoftenFloatRes_BUILD_PAIR(SDNode *N); SDValue SoftenFloatRes_BUILD_PAIR(SDNode *N);
SDValue SoftenFloatRes_ConstantFP(ConstantFPSDNode *N); SDValue SoftenFloatRes_ConstantFP(ConstantFPSDNode *N);
SDValue SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N); SDValue SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N);
@ -426,7 +426,7 @@ private:
// Operand Float to Integer Conversion. // Operand Float to Integer Conversion.
bool SoftenFloatOperand(SDNode *N, unsigned OpNo); bool SoftenFloatOperand(SDNode *N, unsigned OpNo);
SDValue SoftenFloatOp_BIT_CONVERT(SDNode *N); SDValue SoftenFloatOp_BITCAST(SDNode *N);
SDValue SoftenFloatOp_BR_CC(SDNode *N); SDValue SoftenFloatOp_BR_CC(SDNode *N);
SDValue SoftenFloatOp_FP_ROUND(SDNode *N); SDValue SoftenFloatOp_FP_ROUND(SDNode *N);
SDValue SoftenFloatOp_FP_TO_SINT(SDNode *N); SDValue SoftenFloatOp_FP_TO_SINT(SDNode *N);
@ -515,7 +515,7 @@ private:
SDValue ScalarizeVecRes_UnaryOp(SDNode *N); SDValue ScalarizeVecRes_UnaryOp(SDNode *N);
SDValue ScalarizeVecRes_InregOp(SDNode *N); SDValue ScalarizeVecRes_InregOp(SDNode *N);
SDValue ScalarizeVecRes_BIT_CONVERT(SDNode *N); SDValue ScalarizeVecRes_BITCAST(SDNode *N);
SDValue ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N); SDValue ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N);
SDValue ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N); SDValue ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N);
SDValue ScalarizeVecRes_FPOWI(SDNode *N); SDValue ScalarizeVecRes_FPOWI(SDNode *N);
@ -532,7 +532,7 @@ private:
// Vector Operand Scalarization: <1 x ty> -> ty. // Vector Operand Scalarization: <1 x ty> -> ty.
bool ScalarizeVectorOperand(SDNode *N, unsigned OpNo); bool ScalarizeVectorOperand(SDNode *N, unsigned OpNo);
SDValue ScalarizeVecOp_BIT_CONVERT(SDNode *N); SDValue ScalarizeVecOp_BITCAST(SDNode *N);
SDValue ScalarizeVecOp_CONCAT_VECTORS(SDNode *N); SDValue ScalarizeVecOp_CONCAT_VECTORS(SDNode *N);
SDValue ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N); SDValue ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
SDValue ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo); SDValue ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo);
@ -557,7 +557,7 @@ private:
void SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, SDValue &Hi); void SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_InregOp(SDNode *N, SDValue &Lo, SDValue &Hi); void SplitVecRes_InregOp(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo, SDValue &Hi); void SplitVecRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_BUILD_PAIR(SDNode *N, SDValue &Lo, SDValue &Hi); void SplitVecRes_BUILD_PAIR(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi); void SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, SDValue &Hi); void SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, SDValue &Hi);
@ -577,7 +577,7 @@ private:
bool SplitVectorOperand(SDNode *N, unsigned OpNo); bool SplitVectorOperand(SDNode *N, unsigned OpNo);
SDValue SplitVecOp_UnaryOp(SDNode *N); SDValue SplitVecOp_UnaryOp(SDNode *N);
SDValue SplitVecOp_BIT_CONVERT(SDNode *N); SDValue SplitVecOp_BITCAST(SDNode *N);
SDValue SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N); SDValue SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N);
SDValue SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N); SDValue SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
SDValue SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo); SDValue SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo);
@ -603,7 +603,7 @@ private:
// Widen Vector Result Promotion. // Widen Vector Result Promotion.
void WidenVectorResult(SDNode *N, unsigned ResNo); void WidenVectorResult(SDNode *N, unsigned ResNo);
SDValue WidenVecRes_BIT_CONVERT(SDNode* N); SDValue WidenVecRes_BITCAST(SDNode* N);
SDValue WidenVecRes_BUILD_VECTOR(SDNode* N); SDValue WidenVecRes_BUILD_VECTOR(SDNode* N);
SDValue WidenVecRes_CONCAT_VECTORS(SDNode* N); SDValue WidenVecRes_CONCAT_VECTORS(SDNode* N);
SDValue WidenVecRes_CONVERT_RNDSAT(SDNode* N); SDValue WidenVecRes_CONVERT_RNDSAT(SDNode* N);
@ -628,7 +628,7 @@ private:
// Widen Vector Operand. // Widen Vector Operand.
bool WidenVectorOperand(SDNode *N, unsigned ResNo); bool WidenVectorOperand(SDNode *N, unsigned ResNo);
SDValue WidenVecOp_BIT_CONVERT(SDNode *N); SDValue WidenVecOp_BITCAST(SDNode *N);
SDValue WidenVecOp_CONCAT_VECTORS(SDNode *N); SDValue WidenVecOp_CONCAT_VECTORS(SDNode *N);
SDValue WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N); SDValue WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
SDValue WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N); SDValue WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N);
@ -721,7 +721,7 @@ private:
} }
// Generic Result Expansion. // Generic Result Expansion.
void ExpandRes_BIT_CONVERT (SDNode *N, SDValue &Lo, SDValue &Hi); void ExpandRes_BITCAST (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandRes_BUILD_PAIR (SDNode *N, SDValue &Lo, SDValue &Hi); void ExpandRes_BUILD_PAIR (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandRes_EXTRACT_ELEMENT (SDNode *N, SDValue &Lo, SDValue &Hi); void ExpandRes_EXTRACT_ELEMENT (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi); void ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi);
@ -729,7 +729,7 @@ private:
void ExpandRes_VAARG (SDNode *N, SDValue &Lo, SDValue &Hi); void ExpandRes_VAARG (SDNode *N, SDValue &Lo, SDValue &Hi);
// Generic Operand Expansion. // Generic Operand Expansion.
SDValue ExpandOp_BIT_CONVERT (SDNode *N); SDValue ExpandOp_BITCAST (SDNode *N);
SDValue ExpandOp_BUILD_VECTOR (SDNode *N); SDValue ExpandOp_BUILD_VECTOR (SDNode *N);
SDValue ExpandOp_EXTRACT_ELEMENT (SDNode *N); SDValue ExpandOp_EXTRACT_ELEMENT (SDNode *N);
SDValue ExpandOp_INSERT_VECTOR_ELT(SDNode *N); SDValue ExpandOp_INSERT_VECTOR_ELT(SDNode *N);

43
llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
View File

@ -32,8 +32,7 @@ using namespace llvm;
// little/big-endian machines, followed by the Hi/Lo part. This means that // little/big-endian machines, followed by the Hi/Lo part. This means that
// they cannot be used as is on vectors, for which Lo is always stored first. // they cannot be used as is on vectors, for which Lo is always stored first.
void DAGTypeLegalizer::ExpandRes_BIT_CONVERT(SDNode *N, SDValue &Lo, void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) {
SDValue &Hi) {
EVT OutVT = N->getValueType(0); EVT OutVT = N->getValueType(0);
EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
SDValue InOp = N->getOperand(0); SDValue InOp = N->getOperand(0);
@ -50,31 +49,31 @@ void DAGTypeLegalizer::ExpandRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
case SoftenFloat: case SoftenFloat:
// Convert the integer operand instead. // Convert the integer operand instead.
SplitInteger(GetSoftenedFloat(InOp), Lo, Hi); SplitInteger(GetSoftenedFloat(InOp), Lo, Hi);
Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, Lo); Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
Hi = DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, Hi); Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
return; return;
case ExpandInteger: case ExpandInteger:
case ExpandFloat: case ExpandFloat:
// Convert the expanded pieces of the input. // Convert the expanded pieces of the input.
GetExpandedOp(InOp, Lo, Hi); GetExpandedOp(InOp, Lo, Hi);
Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, Lo); Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
Hi = DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, Hi); Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
return; return;
case SplitVector: case SplitVector:
GetSplitVector(InOp, Lo, Hi); GetSplitVector(InOp, Lo, Hi);
if (TLI.isBigEndian()) if (TLI.isBigEndian())
std::swap(Lo, Hi); std::swap(Lo, Hi);
Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, Lo); Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
Hi = DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, Hi); Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
return; return;
case ScalarizeVector: case ScalarizeVector:
// Convert the element instead. // Convert the element instead.
SplitInteger(BitConvertToInteger(GetScalarizedVector(InOp)), Lo, Hi); SplitInteger(BitConvertToInteger(GetScalarizedVector(InOp)), Lo, Hi);
Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, Lo); Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
Hi = DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, Hi); Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
return; return;
case WidenVector: { case WidenVector: {
assert(!(InVT.getVectorNumElements() & 1) && "Unsupported BIT_CONVERT"); assert(!(InVT.getVectorNumElements() & 1) && "Unsupported BITCAST");
InOp = GetWidenedVector(InOp); InOp = GetWidenedVector(InOp);
EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
InVT.getVectorNumElements()/2); InVT.getVectorNumElements()/2);
@ -84,19 +83,19 @@ void DAGTypeLegalizer::ExpandRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
DAG.getIntPtrConstant(InNVT.getVectorNumElements())); DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
if (TLI.isBigEndian()) if (TLI.isBigEndian())
std::swap(Lo, Hi); std::swap(Lo, Hi);
Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, Lo); Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
Hi = DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, Hi); Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
return; return;
} }
} }
if (InVT.isVector() && OutVT.isInteger()) { if (InVT.isVector() && OutVT.isInteger()) {
// Handle cases like i64 = BIT_CONVERT v1i64 on x86, where the operand // Handle cases like i64 = BITCAST v1i64 on x86, where the operand
// is legal but the result is not. // is legal but the result is not.
EVT NVT = EVT::getVectorVT(*DAG.getContext(), NOutVT, 2); EVT NVT = EVT::getVectorVT(*DAG.getContext(), NOutVT, 2);
if (isTypeLegal(NVT)) { if (isTypeLegal(NVT)) {
SDValue CastInOp = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, InOp); SDValue CastInOp = DAG.getNode(ISD::BITCAST, dl, NVT, InOp);
Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NOutVT, CastInOp, Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NOutVT, CastInOp,
DAG.getIntPtrConstant(0)); DAG.getIntPtrConstant(0));
Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NOutVT, CastInOp, Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NOutVT, CastInOp,
@ -173,7 +172,7 @@ void DAGTypeLegalizer::ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDValue &Lo,
EVT OldVT = N->getValueType(0); EVT OldVT = N->getValueType(0);
EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT); EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT);
SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, dl, SDValue NewVec = DAG.getNode(ISD::BITCAST, dl,
EVT::getVectorVT(*DAG.getContext(), EVT::getVectorVT(*DAG.getContext(),
NewVT, 2*OldElts), NewVT, 2*OldElts),
OldVec); OldVec);
@ -262,14 +261,14 @@ void DAGTypeLegalizer::ExpandRes_VAARG(SDNode *N, SDValue &Lo, SDValue &Hi) {
// Generic Operand Expansion. // Generic Operand Expansion.
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
SDValue DAGTypeLegalizer::ExpandOp_BIT_CONVERT(SDNode *N) { SDValue DAGTypeLegalizer::ExpandOp_BITCAST(SDNode *N) {
DebugLoc dl = N->getDebugLoc(); DebugLoc dl = N->getDebugLoc();
if (N->getValueType(0).isVector()) { if (N->getValueType(0).isVector()) {
// An illegal expanding type is being converted to a legal vector type. // An illegal expanding type is being converted to a legal vector type.
// Make a two element vector out of the expanded parts and convert that // Make a two element vector out of the expanded parts and convert that
// instead, but only if the new vector type is legal (otherwise there // instead, but only if the new vector type is legal (otherwise there
// is no point, and it might create expansion loops). For example, on // is no point, and it might create expansion loops). For example, on
// x86 this turns v1i64 = BIT_CONVERT i64 into v1i64 = BIT_CONVERT v2i32. // x86 this turns v1i64 = BITCAST i64 into v1i64 = BITCAST v2i32.
EVT OVT = N->getOperand(0).getValueType(); EVT OVT = N->getOperand(0).getValueType();
EVT NVT = EVT::getVectorVT(*DAG.getContext(), EVT NVT = EVT::getVectorVT(*DAG.getContext(),
TLI.getTypeToTransformTo(*DAG.getContext(), OVT), TLI.getTypeToTransformTo(*DAG.getContext(), OVT),
@ -283,7 +282,7 @@ SDValue DAGTypeLegalizer::ExpandOp_BIT_CONVERT(SDNode *N) {
std::swap(Parts[0], Parts[1]); std::swap(Parts[0], Parts[1]);
SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Parts, 2); SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Parts, 2);
return DAG.getNode(ISD::BIT_CONVERT, dl, N->getValueType(0), Vec); return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), Vec);
} }
} }
@ -322,7 +321,7 @@ SDValue DAGTypeLegalizer::ExpandOp_BUILD_VECTOR(SDNode *N) {
&NewElts[0], NewElts.size()); &NewElts[0], NewElts.size());
// Convert the new vector to the old vector type. // Convert the new vector to the old vector type.
return DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, NewVec); return DAG.getNode(ISD::BITCAST, dl, VecVT, NewVec);
} }
SDValue DAGTypeLegalizer::ExpandOp_EXTRACT_ELEMENT(SDNode *N) { SDValue DAGTypeLegalizer::ExpandOp_EXTRACT_ELEMENT(SDNode *N) {
@ -347,7 +346,7 @@ SDValue DAGTypeLegalizer::ExpandOp_INSERT_VECTOR_ELT(SDNode *N) {
// Bitconvert to a vector of twice the length with elements of the expanded // Bitconvert to a vector of twice the length with elements of the expanded
// type, insert the expanded vector elements, and then convert back. // type, insert the expanded vector elements, and then convert back.
EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewEVT, NumElts*2); EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewEVT, NumElts*2);
SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, dl, SDValue NewVec = DAG.getNode(ISD::BITCAST, dl,
NewVecVT, N->getOperand(0)); NewVecVT, N->getOperand(0));
SDValue Lo, Hi; SDValue Lo, Hi;
@ -363,7 +362,7 @@ SDValue DAGTypeLegalizer::ExpandOp_INSERT_VECTOR_ELT(SDNode *N) {
NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Hi, Idx); NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Hi, Idx);
// Convert the new vector to the old vector type. // Convert the new vector to the old vector type.
return DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, NewVec); return DAG.getNode(ISD::BITCAST, dl, VecVT, NewVec);
} }
SDValue DAGTypeLegalizer::ExpandOp_SCALAR_TO_VECTOR(SDNode *N) { SDValue DAGTypeLegalizer::ExpandOp_SCALAR_TO_VECTOR(SDNode *N) {

4
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
View File

@ -241,14 +241,14 @@ SDValue VectorLegalizer::PromoteVectorOp(SDValue Op) {
for (unsigned j = 0; j != Op.getNumOperands(); ++j) { for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
if (Op.getOperand(j).getValueType().isVector()) if (Op.getOperand(j).getValueType().isVector())
Operands[j] = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Op.getOperand(j)); Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
else else
Operands[j] = Op.getOperand(j); Operands[j] = Op.getOperand(j);
} }
Op = DAG.getNode(Op.getOpcode(), dl, NVT, &Operands[0], Operands.size()); Op = DAG.getNode(Op.getOpcode(), dl, NVT, &Operands[0], Operands.size());
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Op); return DAG.getNode(ISD::BITCAST, dl, VT, Op);
} }
SDValue VectorLegalizer::ExpandFNEG(SDValue Op) { SDValue VectorLegalizer::ExpandFNEG(SDValue Op) {

66
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
View File

@ -46,7 +46,7 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
#endif #endif
llvm_unreachable("Do not know how to scalarize the result of this operator!"); llvm_unreachable("Do not know how to scalarize the result of this operator!");
case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break; case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
case ISD::BUILD_VECTOR: R = N->getOperand(0); break; case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break; case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
@ -122,9 +122,9 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
LHS.getValueType(), LHS, RHS); LHS.getValueType(), LHS, RHS);
} }
SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) { SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
EVT NewVT = N->getValueType(0).getVectorElementType(); EVT NewVT = N->getValueType(0).getVectorElementType();
return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
NewVT, N->getOperand(0)); NewVT, N->getOperand(0));
} }
@ -296,8 +296,8 @@ bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
dbgs() << "\n"; dbgs() << "\n";
#endif #endif
llvm_unreachable("Do not know how to scalarize this operator's operand!"); llvm_unreachable("Do not know how to scalarize this operator's operand!");
case ISD::BIT_CONVERT: case ISD::BITCAST:
Res = ScalarizeVecOp_BIT_CONVERT(N); Res = ScalarizeVecOp_BITCAST(N);
break; break;
case ISD::CONCAT_VECTORS: case ISD::CONCAT_VECTORS:
Res = ScalarizeVecOp_CONCAT_VECTORS(N); Res = ScalarizeVecOp_CONCAT_VECTORS(N);
@ -326,11 +326,11 @@ bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
return false; return false;
} }
/// ScalarizeVecOp_BIT_CONVERT - If the value to convert is a vector that needs /// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs
/// to be scalarized, it must be <1 x ty>. Convert the element instead. /// to be scalarized, it must be <1 x ty>. Convert the element instead.
SDValue DAGTypeLegalizer::ScalarizeVecOp_BIT_CONVERT(SDNode *N) { SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
SDValue Elt = GetScalarizedVector(N->getOperand(0)); SDValue Elt = GetScalarizedVector(N->getOperand(0));
return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
N->getValueType(0), Elt); N->getValueType(0), Elt);
} }
@ -406,7 +406,7 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
case ISD::BIT_CONVERT: SplitVecRes_BIT_CONVERT(N, Lo, Hi); break; case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break; case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break; case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
case ISD::CONVERT_RNDSAT: SplitVecRes_CONVERT_RNDSAT(N, Lo, Hi); break; case ISD::CONVERT_RNDSAT: SplitVecRes_CONVERT_RNDSAT(N, Lo, Hi); break;
@ -496,8 +496,8 @@ void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi); Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi);
} }
void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo, void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
SDValue &Hi) { SDValue &Hi) {
// We know the result is a vector. The input may be either a vector or a // We know the result is a vector. The input may be either a vector or a
// scalar value. // scalar value.
EVT LoVT, HiVT; EVT LoVT, HiVT;
@ -525,8 +525,8 @@ void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
GetExpandedOp(InOp, Lo, Hi); GetExpandedOp(InOp, Lo, Hi);
if (TLI.isBigEndian()) if (TLI.isBigEndian())
std::swap(Lo, Hi); std::swap(Lo, Hi);
Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo); Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi); Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
return; return;
} }
break; break;
@ -534,8 +534,8 @@ void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
// If the input is a vector that needs to be split, convert each split // If the input is a vector that needs to be split, convert each split
// piece of the input now. // piece of the input now.
GetSplitVector(InOp, Lo, Hi); GetSplitVector(InOp, Lo, Hi);
Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo); Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi); Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
return; return;
} }
@ -549,8 +549,8 @@ void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
if (TLI.isBigEndian()) if (TLI.isBigEndian())
std::swap(Lo, Hi); std::swap(Lo, Hi);
Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo); Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi); Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
} }
void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
@ -978,7 +978,7 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
#endif #endif
llvm_unreachable("Do not know how to split this operator's operand!"); llvm_unreachable("Do not know how to split this operator's operand!");
case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break; case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break; case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break; case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break; case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
@ -1034,8 +1034,8 @@ SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
} }
SDValue DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) { SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
// For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
// end up being split all the way down to individual components. Convert the // end up being split all the way down to individual components. Convert the
// split pieces into integers and reassemble. // split pieces into integers and reassemble.
SDValue Lo, Hi; SDValue Lo, Hi;
@ -1046,7 +1046,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) {
if (TLI.isBigEndian()) if (TLI.isBigEndian())
std::swap(Lo, Hi); std::swap(Lo, Hi);
return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), N->getValueType(0), return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), N->getValueType(0),
JoinIntegers(Lo, Hi)); JoinIntegers(Lo, Hi));
} }
@ -1197,7 +1197,7 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
#endif #endif
llvm_unreachable("Do not know how to widen the result of this operator!"); llvm_unreachable("Do not know how to widen the result of this operator!");
case ISD::BIT_CONVERT: Res = WidenVecRes_BIT_CONVERT(N); break; case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break; case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break; case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break; case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
@ -1532,7 +1532,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
WidenVT, WidenLHS, DAG.getValueType(ExtVT)); WidenVT, WidenLHS, DAG.getValueType(ExtVT));
} }
SDValue DAGTypeLegalizer::WidenVecRes_BIT_CONVERT(SDNode *N) { SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
SDValue InOp = N->getOperand(0); SDValue InOp = N->getOperand(0);
EVT InVT = InOp.getValueType(); EVT InVT = InOp.getValueType();
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
@ -1551,7 +1551,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_BIT_CONVERT(SDNode *N) {
InOp = GetPromotedInteger(InOp); InOp = GetPromotedInteger(InOp);
InVT = InOp.getValueType(); InVT = InOp.getValueType();
if (WidenVT.bitsEq(InVT)) if (WidenVT.bitsEq(InVT))
return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, InOp); return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
break; break;
case SoftenFloat: case SoftenFloat:
case ExpandInteger: case ExpandInteger:
@ -1566,7 +1566,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_BIT_CONVERT(SDNode *N) {
InVT = InOp.getValueType(); InVT = InOp.getValueType();
if (WidenVT.bitsEq(InVT)) if (WidenVT.bitsEq(InVT))
// The input widens to the same size. Convert to the widen value. // The input widens to the same size. Convert to the widen value.
return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, InOp); return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
break; break;
} }
@ -1606,7 +1606,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_BIT_CONVERT(SDNode *N) {
else else
NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl,
NewInVT, &Ops[0], NewNumElts); NewInVT, &Ops[0], NewNumElts);
return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, NewVec); return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
} }
} }
@ -1982,7 +1982,7 @@ bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) {
#endif #endif
llvm_unreachable("Do not know how to widen this operator's operand!"); llvm_unreachable("Do not know how to widen this operator's operand!");
case ISD::BIT_CONVERT: Res = WidenVecOp_BIT_CONVERT(N); break; case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break; case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break; case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break; case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
@ -2041,7 +2041,7 @@ SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts); return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
} }
SDValue DAGTypeLegalizer::WidenVecOp_BIT_CONVERT(SDNode *N) { SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
SDValue InOp = GetWidenedVector(N->getOperand(0)); SDValue InOp = GetWidenedVector(N->getOperand(0));
EVT InWidenVT = InOp.getValueType(); EVT InWidenVT = InOp.getValueType();
@ -2055,7 +2055,7 @@ SDValue DAGTypeLegalizer::WidenVecOp_BIT_CONVERT(SDNode *N) {
unsigned NewNumElts = InWidenSize / Size; unsigned NewNumElts = InWidenSize / Size;
EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts); EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
if (TLI.isTypeLegal(NewVT)) { if (TLI.isTypeLegal(NewVT)) {
SDValue BitOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, InOp); SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp, return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
DAG.getIntPtrConstant(0)); DAG.getIntPtrConstant(0));
} }
@ -2199,7 +2199,7 @@ static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
if (NewLdTy != LdTy) { if (NewLdTy != LdTy) {
NumElts = Width / NewLdTy.getSizeInBits(); NumElts = Width / NewLdTy.getSizeInBits();
NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts); NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVecVT, VecOp); VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
// Readjust position and vector position based on new load type // Readjust position and vector position based on new load type
Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits(); Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
LdTy = NewLdTy; LdTy = NewLdTy;
@ -2207,7 +2207,7 @@ static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i], VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
DAG.getIntPtrConstant(Idx++)); DAG.getIntPtrConstant(Idx++));
} }
return DAG.getNode(ISD::BIT_CONVERT, dl, VecTy, VecOp); return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
} }
SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16> &LdChain, SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16> &LdChain,
@ -2247,7 +2247,7 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16> &LdChain,
unsigned NumElts = WidenWidth / NewVTWidth; unsigned NumElts = WidenWidth / NewVTWidth;
EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts); EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp); SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, VecOp); return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
} }
if (NewVT == WidenVT) if (NewVT == WidenVT)
return LdOp; return LdOp;
@ -2441,7 +2441,7 @@ void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain,
// Cast the vector to the scalar type we can store // Cast the vector to the scalar type we can store
unsigned NumElts = ValWidth / NewVTWidth; unsigned NumElts = ValWidth / NewVTWidth;
EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts); EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVecVT, ValOp); SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
// Readjust index position based on new vector type // Readjust index position based on new vector type
Idx = Idx * ValEltWidth / NewVTWidth; Idx = Idx * ValEltWidth / NewVTWidth;
do { do {

22
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -111,7 +111,7 @@ bool ConstantFPSDNode::isValueValidForType(EVT VT,
/// BUILD_VECTOR where all of the elements are ~0 or undef. /// BUILD_VECTOR where all of the elements are ~0 or undef.
bool ISD::isBuildVectorAllOnes(const SDNode *N) { bool ISD::isBuildVectorAllOnes(const SDNode *N) {
// Look through a bit convert. // Look through a bit convert.
if (N->getOpcode() == ISD::BIT_CONVERT) if (N->getOpcode() == ISD::BITCAST)
N = N->getOperand(0).getNode(); N = N->getOperand(0).getNode();
if (N->getOpcode() != ISD::BUILD_VECTOR) return false; if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
@ -152,7 +152,7 @@ bool ISD::isBuildVectorAllOnes(const SDNode *N) {
/// BUILD_VECTOR where all of the elements are 0 or undef. /// BUILD_VECTOR where all of the elements are 0 or undef.
bool ISD::isBuildVectorAllZeros(const SDNode *N) { bool ISD::isBuildVectorAllZeros(const SDNode *N) {
// Look through a bit convert. // Look through a bit convert.
if (N->getOpcode() == ISD::BIT_CONVERT) if (N->getOpcode() == ISD::BITCAST)
N = N->getOperand(0).getNode(); N = N->getOperand(0).getNode();
if (N->getOpcode() != ISD::BUILD_VECTOR) return false; if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
@ -2365,7 +2365,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
APFloat::rmNearestTiesToEven); APFloat::rmNearestTiesToEven);
return getConstantFP(apf, VT); return getConstantFP(apf, VT);
} }
case ISD::BIT_CONVERT: case ISD::BITCAST:
if (VT == MVT::f32 && C->getValueType(0) == MVT::i32) if (VT == MVT::f32 && C->getValueType(0) == MVT::i32)
return getConstantFP(Val.bitsToFloat(), VT); return getConstantFP(Val.bitsToFloat(), VT);
else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64) else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64)
@ -2416,7 +2416,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
APInt api(VT.getSizeInBits(), 2, x); APInt api(VT.getSizeInBits(), 2, x);
return getConstant(api, VT); return getConstant(api, VT);
} }
case ISD::BIT_CONVERT: case ISD::BITCAST:
if (VT == MVT::i32 && C->getValueType(0) == MVT::f32) if (VT == MVT::i32 && C->getValueType(0) == MVT::f32)
return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT); return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT);
else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64) else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64)
@ -2518,13 +2518,13 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
return Operand.getNode()->getOperand(0); return Operand.getNode()->getOperand(0);
} }
break; break;
case ISD::BIT_CONVERT: case ISD::BITCAST:
// Basic sanity checking. // Basic sanity checking.
assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits() assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits()
&& "Cannot BIT_CONVERT between types of different sizes!"); && "Cannot BITCAST between types of different sizes!");
if (VT == Operand.getValueType()) return Operand; // noop conversion. if (VT == Operand.getValueType()) return Operand; // noop conversion.
if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) if (OpOpcode == ISD::BITCAST) // bitconv(bitconv(x)) -> bitconv(x)
return getNode(ISD::BIT_CONVERT, DL, VT, Operand.getOperand(0)); return getNode(ISD::BITCAST, DL, VT, Operand.getOperand(0));
if (OpOpcode == ISD::UNDEF) if (OpOpcode == ISD::UNDEF)
return getUNDEF(VT); return getUNDEF(VT);
break; break;
@ -3060,7 +3060,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
case ISD::VECTOR_SHUFFLE: case ISD::VECTOR_SHUFFLE:
llvm_unreachable("should use getVectorShuffle constructor!"); llvm_unreachable("should use getVectorShuffle constructor!");
break; break;
case ISD::BIT_CONVERT: case ISD::BITCAST:
// Fold bit_convert nodes from a type to themselves. // Fold bit_convert nodes from a type to themselves.
if (N1.getValueType() == VT) if (N1.getValueType() == VT)
return N1; return N1;
@ -3177,7 +3177,7 @@ static SDValue getMemsetStringVal(EVT VT, DebugLoc dl, SelectionDAG &DAG,
else if (VT.isVector()) { else if (VT.isVector()) {
unsigned NumElts = VT.getVectorNumElements(); unsigned NumElts = VT.getVectorNumElements();
MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, return DAG.getNode(ISD::BITCAST, dl, VT,
DAG.getConstant(0, EVT::getVectorVT(*DAG.getContext(), DAG.getConstant(0, EVT::getVectorVT(*DAG.getContext(),
EltVT, NumElts))); EltVT, NumElts)));
} else } else
@ -5788,7 +5788,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::UINT_TO_FP: return "uint_to_fp"; case ISD::UINT_TO_FP: return "uint_to_fp";
case ISD::FP_TO_SINT: return "fp_to_sint"; case ISD::FP_TO_SINT: return "fp_to_sint";
case ISD::FP_TO_UINT: return "fp_to_uint"; case ISD::FP_TO_UINT: return "fp_to_uint";
case ISD::BIT_CONVERT: return "bit_convert"; case ISD::BITCAST: return "bit_convert";
case ISD::FP16_TO_FP32: return "fp16_to_fp32"; case ISD::FP16_TO_FP32: return "fp16_to_fp32";
case ISD::FP32_TO_FP16: return "fp32_to_fp16"; case ISD::FP32_TO_FP16: return "fp32_to_fp16";

80
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -131,8 +131,8 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
RoundParts / 2, PartVT, HalfVT); RoundParts / 2, PartVT, HalfVT);
} else { } else {
Lo = DAG.getNode(ISD::BIT_CONVERT, DL, HalfVT, Parts[0]); Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
Hi = DAG.getNode(ISD::BIT_CONVERT, DL, HalfVT, Parts[1]); Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
} }
if (TLI.isBigEndian()) if (TLI.isBigEndian())
@ -164,8 +164,8 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
"Unexpected split"); "Unexpected split");
SDValue Lo, Hi; SDValue Lo, Hi;
Lo = DAG.getNode(ISD::BIT_CONVERT, DL, EVT(MVT::f64), Parts[0]); Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
Hi = DAG.getNode(ISD::BIT_CONVERT, DL, EVT(MVT::f64), Parts[1]); Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
if (TLI.isBigEndian()) if (TLI.isBigEndian())
std::swap(Lo, Hi); std::swap(Lo, Hi);
Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
@ -207,7 +207,7 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
} }
if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
return DAG.getNode(ISD::BIT_CONVERT, DL, ValueVT, Val); return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
llvm_unreachable("Unknown mismatch!"); llvm_unreachable("Unknown mismatch!");
return SDValue(); return SDValue();
@ -284,7 +284,7 @@ static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
} }
// Vector/Vector bitcast. // Vector/Vector bitcast.
return DAG.getNode(ISD::BIT_CONVERT, DL, ValueVT, Val); return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
} }
assert(ValueVT.getVectorElementType() == PartVT && assert(ValueVT.getVectorElementType() == PartVT &&
@ -342,7 +342,7 @@ static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
} else if (PartBits == ValueVT.getSizeInBits()) { } else if (PartBits == ValueVT.getSizeInBits()) {
// Different types of the same size. // Different types of the same size.
assert(NumParts == 1 && PartVT != ValueVT); assert(NumParts == 1 && PartVT != ValueVT);
Val = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Val); Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
} else if (NumParts * PartBits < ValueVT.getSizeInBits()) { } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
// If the parts cover less bits than value has, truncate the value. // If the parts cover less bits than value has, truncate the value.
assert(PartVT.isInteger() && ValueVT.isInteger() && assert(PartVT.isInteger() && ValueVT.isInteger() &&
@ -385,7 +385,7 @@ static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
// The number of parts is a power of 2. Repeatedly bisect the value using // The number of parts is a power of 2. Repeatedly bisect the value using
// EXTRACT_ELEMENT. // EXTRACT_ELEMENT.
Parts[0] = DAG.getNode(ISD::BIT_CONVERT, DL, Parts[0] = DAG.getNode(ISD::BITCAST, DL,
EVT::getIntegerVT(*DAG.getContext(), EVT::getIntegerVT(*DAG.getContext(),
ValueVT.getSizeInBits()), ValueVT.getSizeInBits()),
Val); Val);
@ -403,8 +403,8 @@ static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
ThisVT, Part0, DAG.getIntPtrConstant(0)); ThisVT, Part0, DAG.getIntPtrConstant(0));
if (ThisBits == PartBits && ThisVT != PartVT) { if (ThisBits == PartBits && ThisVT != PartVT) {
Part0 = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Part0); Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
Part1 = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Part1); Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
} }
} }
} }
@ -428,7 +428,7 @@ static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
// Nothing to do. // Nothing to do.
} else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
// Bitconvert vector->vector case. // Bitconvert vector->vector case.
Val = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Val); Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
} else if (PartVT.isVector() && } else if (PartVT.isVector() &&
PartVT.getVectorElementType() == ValueVT.getVectorElementType()&& PartVT.getVectorElementType() == ValueVT.getVectorElementType()&&
PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
@ -2579,9 +2579,9 @@ void SelectionDAGBuilder::visitBitCast(const User &I) {
EVT DestVT = TLI.getValueType(I.getType()); EVT DestVT = TLI.getValueType(I.getType());
// BitCast assures us that source and destination are the same size so this is // BitCast assures us that source and destination are the same size so this is
// either a BIT_CONVERT or a no-op. // either a BITCAST or a no-op.
if (DestVT != N.getValueType()) if (DestVT != N.getValueType())
setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
DestVT, N)); // convert types. DestVT, N)); // convert types.
else else
setValue(&I, N); // noop cast. setValue(&I, N); // noop cast.
@ -3198,7 +3198,7 @@ void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
if (!I.getType()->isVoidTy()) { if (!I.getType()->isVoidTy()) {
if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
EVT VT = TLI.getValueType(PTy); EVT VT = TLI.getValueType(PTy);
Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result); Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result);
} }
setValue(&I, Result); setValue(&I, Result);
@ -3217,7 +3217,7 @@ GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
DAG.getConstant(0x007fffff, MVT::i32)); DAG.getConstant(0x007fffff, MVT::i32));
SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
DAG.getConstant(0x3f800000, MVT::i32)); DAG.getConstant(0x3f800000, MVT::i32));
return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2); return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
} }
/// GetExponent - Get the exponent: /// GetExponent - Get the exponent:
@ -3316,13 +3316,13 @@ SelectionDAGBuilder::visitExp(const CallInst &I) {
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
getF32Constant(DAG, 0x3f7f5e7e)); getF32Constant(DAG, 0x3f7f5e7e));
SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5); SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5);
// Add the exponent into the result in integer domain. // Add the exponent into the result in integer domain.
SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
TwoToFracPartOfX, IntegerPartOfX); TwoToFracPartOfX, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6); result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12: // For floating-point precision of 12:
// //
@ -3342,13 +3342,13 @@ SelectionDAGBuilder::visitExp(const CallInst &I) {
SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
getF32Constant(DAG, 0x3f7ff8fd)); getF32Constant(DAG, 0x3f7ff8fd));
SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7); SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7);
// Add the exponent into the result in integer domain. // Add the exponent into the result in integer domain.
SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
TwoToFracPartOfX, IntegerPartOfX); TwoToFracPartOfX, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8); result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18: // For floating-point precision of 18:
// //
@ -3380,14 +3380,14 @@ SelectionDAGBuilder::visitExp(const CallInst &I) {
SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
getF32Constant(DAG, 0x3f800000)); getF32Constant(DAG, 0x3f800000));
SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl, SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,
MVT::i32, t13); MVT::i32, t13);
// Add the exponent into the result in integer domain. // Add the exponent into the result in integer domain.
SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
TwoToFracPartOfX, IntegerPartOfX); TwoToFracPartOfX, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14); result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14);
} }
} else { } else {
// No special expansion. // No special expansion.
@ -3409,7 +3409,7 @@ SelectionDAGBuilder::visitLog(const CallInst &I) {
if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
SDValue Op = getValue(I.getArgOperand(0)); SDValue Op = getValue(I.getArgOperand(0));
SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
// Scale the exponent by log(2) [0.69314718f]. // Scale the exponent by log(2) [0.69314718f].
SDValue Exp = GetExponent(DAG, Op1, TLI, dl); SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
@ -3519,7 +3519,7 @@ SelectionDAGBuilder::visitLog2(const CallInst &I) {
if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
SDValue Op = getValue(I.getArgOperand(0)); SDValue Op = getValue(I.getArgOperand(0));
SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
// Get the exponent. // Get the exponent.
SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
@ -3628,7 +3628,7 @@ SelectionDAGBuilder::visitLog10(const CallInst &I) {
if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
SDValue Op = getValue(I.getArgOperand(0)); SDValue Op = getValue(I.getArgOperand(0));
SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
// Scale the exponent by log10(2) [0.30102999f]. // Scale the exponent by log10(2) [0.30102999f].
SDValue Exp = GetExponent(DAG, Op1, TLI, dl); SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
@ -3756,11 +3756,11 @@ SelectionDAGBuilder::visitExp2(const CallInst &I) {
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
getF32Constant(DAG, 0x3f7f5e7e)); getF32Constant(DAG, 0x3f7f5e7e));
SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5); SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
SDValue TwoToFractionalPartOfX = SDValue TwoToFractionalPartOfX =
DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl, result = DAG.getNode(ISD::BITCAST, dl,
MVT::f32, TwoToFractionalPartOfX); MVT::f32, TwoToFractionalPartOfX);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12: // For floating-point precision of 12:
@ -3781,11 +3781,11 @@ SelectionDAGBuilder::visitExp2(const CallInst &I) {
SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
getF32Constant(DAG, 0x3f7ff8fd)); getF32Constant(DAG, 0x3f7ff8fd));
SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7); SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
SDValue TwoToFractionalPartOfX = SDValue TwoToFractionalPartOfX =
DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl, result = DAG.getNode(ISD::BITCAST, dl,
MVT::f32, TwoToFractionalPartOfX); MVT::f32, TwoToFractionalPartOfX);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18: // For floating-point precision of 18:
@ -3817,11 +3817,11 @@ SelectionDAGBuilder::visitExp2(const CallInst &I) {
SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
getF32Constant(DAG, 0x3f800000)); getF32Constant(DAG, 0x3f800000));
SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13); SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
SDValue TwoToFractionalPartOfX = SDValue TwoToFractionalPartOfX =
DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl, result = DAG.getNode(ISD::BITCAST, dl,
MVT::f32, TwoToFractionalPartOfX); MVT::f32, TwoToFractionalPartOfX);
} }
} else { } else {
@ -3889,11 +3889,11 @@ SelectionDAGBuilder::visitPow(const CallInst &I) {
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
getF32Constant(DAG, 0x3f7f5e7e)); getF32Constant(DAG, 0x3f7f5e7e));
SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5); SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
SDValue TwoToFractionalPartOfX = SDValue TwoToFractionalPartOfX =
DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl, result = DAG.getNode(ISD::BITCAST, dl,
MVT::f32, TwoToFractionalPartOfX); MVT::f32, TwoToFractionalPartOfX);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12: // For floating-point precision of 12:
@ -3914,11 +3914,11 @@ SelectionDAGBuilder::visitPow(const CallInst &I) {
SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
getF32Constant(DAG, 0x3f7ff8fd)); getF32Constant(DAG, 0x3f7ff8fd));
SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7); SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
SDValue TwoToFractionalPartOfX = SDValue TwoToFractionalPartOfX =
DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl, result = DAG.getNode(ISD::BITCAST, dl,
MVT::f32, TwoToFractionalPartOfX); MVT::f32, TwoToFractionalPartOfX);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18: // For floating-point precision of 18:
@ -3950,11 +3950,11 @@ SelectionDAGBuilder::visitPow(const CallInst &I) {
SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
getF32Constant(DAG, 0x3f800000)); getF32Constant(DAG, 0x3f800000));
SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13); SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
SDValue TwoToFractionalPartOfX = SDValue TwoToFractionalPartOfX =
DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl, result = DAG.getNode(ISD::BITCAST, dl,
MVT::f32, TwoToFractionalPartOfX); MVT::f32, TwoToFractionalPartOfX);
} }
} else { } else {
@ -4476,7 +4476,7 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
ShOps[1] = DAG.getConstant(0, MVT::i32); ShOps[1] = DAG.getConstant(0, MVT::i32);
ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
EVT DestVT = TLI.getValueType(I.getType()); EVT DestVT = TLI.getValueType(I.getType());
ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, DestVT, ShAmt); ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt);
Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
DAG.getConstant(NewIntrinsic, MVT::i32), DAG.getConstant(NewIntrinsic, MVT::i32),
getValue(I.getArgOperand(0)), ShAmt); getValue(I.getArgOperand(0)), ShAmt);
@ -5419,7 +5419,7 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
// vector types). // vector types).
EVT RegVT = *PhysReg.second->vt_begin(); EVT RegVT = *PhysReg.second->vt_begin();
if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
RegVT, OpInfo.CallOperand); RegVT, OpInfo.CallOperand);
OpInfo.ConstraintVT = RegVT; OpInfo.ConstraintVT = RegVT;
} else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
@ -5429,7 +5429,7 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
// machine. // machine.
RegVT = EVT::getIntegerVT(Context, RegVT = EVT::getIntegerVT(Context,
OpInfo.ConstraintVT.getSizeInBits()); OpInfo.ConstraintVT.getSizeInBits());
OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
RegVT, OpInfo.CallOperand); RegVT, OpInfo.CallOperand);
OpInfo.ConstraintVT = RegVT; OpInfo.ConstraintVT = RegVT;
} }
@ -5945,7 +5945,7 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
// not have the same VT as was expected. Convert it to the right type // not have the same VT as was expected. Convert it to the right type
// with bit_convert. // with bit_convert.
if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
ResultType, Val); ResultType, Val);
} else if (ResultType != Val.getValueType() && } else if (ResultType != Val.getValueType() &&

2
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -1697,7 +1697,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
KnownZero |= ~InMask & NewMask; KnownZero |= ~InMask & NewMask;
break; break;
} }
case ISD::BIT_CONVERT: case ISD::BITCAST:
#if 0 #if 0
// If this is an FP->Int bitcast and if the sign bit is the only thing that // If this is an FP->Int bitcast and if the sign bit is the only thing that
// is demanded, turn this into a FGETSIGN. // is demanded, turn this into a FGETSIGN.

2
llvm/lib/Target/ARM/ARMFastISel.cpp
View File

@ -1519,7 +1519,7 @@ bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
break; break;
} }
case CCValAssign::BCvt: { case CCValAssign::BCvt: {
unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BIT_CONVERT, Arg, unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
/*TODO: Kill=*/false); /*TODO: Kill=*/false);
assert(BC != 0 && "Failed to emit a bitcast!"); assert(BC != 0 && "Failed to emit a bitcast!");
Arg = BC; Arg = BC;

80
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -609,7 +609,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
// Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
// iff target supports vfp2. // iff target supports vfp2.
setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom); setOperationAction(ISD::BITCAST, MVT::i64, Custom);
setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
} }
@ -1061,7 +1061,7 @@ ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
default: llvm_unreachable("Unknown loc info!"); default: llvm_unreachable("Unknown loc info!");
case CCValAssign::Full: break; case CCValAssign::Full: break;
case CCValAssign::BCvt: case CCValAssign::BCvt:
Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val); Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
break; break;
} }
@ -1209,7 +1209,7 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
break; break;
case CCValAssign::BCvt: case CCValAssign::BCvt:
Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg); Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
break; break;
} }
@ -1666,7 +1666,7 @@ ARMTargetLowering::LowerReturn(SDValue Chain,
default: llvm_unreachable("Unknown loc info!"); default: llvm_unreachable("Unknown loc info!");
case CCValAssign::Full: break; case CCValAssign::Full: break;
case CCValAssign::BCvt: case CCValAssign::BCvt:
Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg); Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
break; break;
} }
@ -2223,7 +2223,7 @@ ARMTargetLowering::LowerFormalArguments(SDValue Chain,
default: llvm_unreachable("Unknown loc info!"); default: llvm_unreachable("Unknown loc info!");
case CCValAssign::Full: break; case CCValAssign::Full: break;
case CCValAssign::BCvt: case CCValAssign::BCvt:
ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
break; break;
case CCValAssign::SExt: case CCValAssign::SExt:
ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
@ -2689,7 +2689,7 @@ static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
break; break;
} }
Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0)); Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
} }
static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) { static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
@ -2708,7 +2708,7 @@ static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
break; break;
} }
Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0)); Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
return DAG.getNode(Opc, dl, VT, Op); return DAG.getNode(Opc, dl, VT, Op);
} }
@ -2765,12 +2765,12 @@ SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
return FrameAddr; return FrameAddr;
} }
/// ExpandBIT_CONVERT - If the target supports VFP, this function is called to /// ExpandBITCAST - If the target supports VFP, this function is called to
/// expand a bit convert where either the source or destination type is i64 to /// expand a bit convert where either the source or destination type is i64 to
/// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
/// operand type is illegal (e.g., v2f32 for a target that doesn't support /// operand type is illegal (e.g., v2f32 for a target that doesn't support
/// vectors), since the legalizer won't know what to do with that. /// vectors), since the legalizer won't know what to do with that.
static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) { static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); const TargetLowering &TLI = DAG.getTargetLoweringInfo();
DebugLoc dl = N->getDebugLoc(); DebugLoc dl = N->getDebugLoc();
SDValue Op = N->getOperand(0); SDValue Op = N->getOperand(0);
@ -2780,7 +2780,7 @@ static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
EVT SrcVT = Op.getValueType(); EVT SrcVT = Op.getValueType();
EVT DstVT = N->getValueType(0); EVT DstVT = N->getValueType(0);
assert((SrcVT == MVT::i64 || DstVT == MVT::i64) && assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
"ExpandBIT_CONVERT called for non-i64 type"); "ExpandBITCAST called for non-i64 type");
// Turn i64->f64 into VMOVDRR. // Turn i64->f64 into VMOVDRR.
if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) { if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
@ -2788,7 +2788,7 @@ static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
DAG.getConstant(0, MVT::i32)); DAG.getConstant(0, MVT::i32));
SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
DAG.getConstant(1, MVT::i32)); DAG.getConstant(1, MVT::i32));
return DAG.getNode(ISD::BIT_CONVERT, dl, DstVT, return DAG.getNode(ISD::BITCAST, dl, DstVT,
DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi)); DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
} }
@ -2815,7 +2815,7 @@ static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32); SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32; EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal); SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov); return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
} }
/// LowerShiftRightParts - Lower SRA_PARTS, which returns two /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
@ -3068,13 +3068,13 @@ static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
AndOp = Op1; AndOp = Op1;
// Ignore bitconvert. // Ignore bitconvert.
if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT) if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
AndOp = AndOp.getOperand(0); AndOp = AndOp.getOperand(0);
if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) { if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
Opc = ARMISD::VTST; Opc = ARMISD::VTST;
Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0)); Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));
Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1)); Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));
Invert = !Invert; Invert = !Invert;
} }
} }
@ -3499,7 +3499,7 @@ static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
VMOVModImm); VMOVModImm);
if (Val.getNode()) { if (Val.getNode()) {
SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val); SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov); return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
} }
// Try an immediate VMVN. // Try an immediate VMVN.
@ -3511,7 +3511,7 @@ static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
VMVNModImm); VMVNModImm);
if (Val.getNode()) { if (Val.getNode()) {
SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val); SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov); return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
} }
} }
} }
@ -3553,13 +3553,13 @@ static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
if (VT.getVectorElementType().isFloatingPoint()) { if (VT.getVectorElementType().isFloatingPoint()) {
SmallVector<SDValue, 8> Ops; SmallVector<SDValue, 8> Ops;
for (unsigned i = 0; i < NumElts; ++i) for (unsigned i = 0; i < NumElts; ++i)
Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
Op.getOperand(i))); Op.getOperand(i)));
EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts); EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts); SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts);
Val = LowerBUILD_VECTOR(Val, DAG, ST); Val = LowerBUILD_VECTOR(Val, DAG, ST);
if (Val.getNode()) if (Val.getNode())
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val); return DAG.getNode(ISD::BITCAST, dl, VT, Val);
} }
SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl); SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
if (Val.getNode()) if (Val.getNode())
@ -3582,9 +3582,9 @@ static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
SmallVector<SDValue, 8> Ops; SmallVector<SDValue, 8> Ops;
for (unsigned i = 0; i < NumElts; ++i) for (unsigned i = 0; i < NumElts; ++i)
Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, EltVT, Op.getOperand(i))); Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts); SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val); return DAG.getNode(ISD::BITCAST, dl, VT, Val);
} }
return SDValue(); return SDValue();
@ -3805,8 +3805,8 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
// registers are defined to use, and since i64 is not legal. // registers are defined to use, and since i64 is not legal.
EVT EltVT = EVT::getFloatingPointVT(EltSize); EVT EltVT = EVT::getFloatingPointVT(EltSize);
EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
V1 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V1); V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
V2 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V2); V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
SmallVector<SDValue, 8> Ops; SmallVector<SDValue, 8> Ops;
for (unsigned i = 0; i < NumElts; ++i) { for (unsigned i = 0; i < NumElts; ++i) {
if (ShuffleMask[i] < 0) if (ShuffleMask[i] < 0)
@ -3818,7 +3818,7 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
MVT::i32))); MVT::i32)));
} }
SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts); SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val); return DAG.getNode(ISD::BITCAST, dl, VT, Val);
} }
return SDValue(); return SDValue();
@ -3851,13 +3851,13 @@ static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
SDValue Op1 = Op.getOperand(1); SDValue Op1 = Op.getOperand(1);
if (Op0.getOpcode() != ISD::UNDEF) if (Op0.getOpcode() != ISD::UNDEF)
Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0), DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
DAG.getIntPtrConstant(0)); DAG.getIntPtrConstant(0));
if (Op1.getOpcode() != ISD::UNDEF) if (Op1.getOpcode() != ISD::UNDEF)
Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1), DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
DAG.getIntPtrConstant(1)); DAG.getIntPtrConstant(1));
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val); return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
} }
/// SkipExtension - For a node that is either a SIGN_EXTEND, ZERO_EXTEND, or /// SkipExtension - For a node that is either a SIGN_EXTEND, ZERO_EXTEND, or
@ -3933,7 +3933,7 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::EH_SJLJ_DISPATCHSETUP: return LowerEH_SJLJ_DISPATCHSETUP(Op, DAG); case ISD::EH_SJLJ_DISPATCHSETUP: return LowerEH_SJLJ_DISPATCHSETUP(Op, DAG);
case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG, case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
Subtarget); Subtarget);
case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG); case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
case ISD::SHL: case ISD::SHL:
case ISD::SRL: case ISD::SRL:
case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget); case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
@ -3962,8 +3962,8 @@ void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
default: default:
llvm_unreachable("Don't know how to custom expand this!"); llvm_unreachable("Don't know how to custom expand this!");
break; break;
case ISD::BIT_CONVERT: case ISD::BITCAST:
Res = ExpandBIT_CONVERT(N, DAG); Res = ExpandBITCAST(N, DAG);
break; break;
case ISD::SRL: case ISD::SRL:
case ISD::SRA: case ISD::SRA:
@ -4511,9 +4511,9 @@ static SDValue PerformANDCombine(SDNode *N,
OtherModImm); OtherModImm);
if (Val.getNode()) { if (Val.getNode()) {
SDValue Input = SDValue Input =
DAG.getNode(ISD::BIT_CONVERT, dl, VbicVT, N->getOperand(0)); DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val); SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vbic); return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
} }
} }
} }
@ -4544,9 +4544,9 @@ static SDValue PerformORCombine(SDNode *N,
OtherModImm); OtherModImm);
if (Val.getNode()) { if (Val.getNode()) {
SDValue Input = SDValue Input =
DAG.getNode(ISD::BIT_CONVERT, dl, VorrVT, N->getOperand(0)); DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val); SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vorr); return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
} }
} }
} }
@ -4661,14 +4661,14 @@ static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
// N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X) // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
SDValue Op0 = N->getOperand(0); SDValue Op0 = N->getOperand(0);
SDValue Op1 = N->getOperand(1); SDValue Op1 = N->getOperand(1);
if (Op0.getOpcode() == ISD::BIT_CONVERT) if (Op0.getOpcode() == ISD::BITCAST)
Op0 = Op0.getOperand(0); Op0 = Op0.getOperand(0);
if (Op1.getOpcode() == ISD::BIT_CONVERT) if (Op1.getOpcode() == ISD::BITCAST)
Op1 = Op1.getOperand(0); Op1 = Op1.getOperand(0);
if (Op0.getOpcode() == ARMISD::VMOVRRD && if (Op0.getOpcode() == ARMISD::VMOVRRD &&
Op0.getNode() == Op1.getNode() && Op0.getNode() == Op1.getNode() &&
Op0.getResNo() == 0 && Op1.getResNo() == 1) Op0.getResNo() == 0 && Op1.getResNo() == 1)
return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
N->getValueType(0), Op0.getOperand(0)); N->getValueType(0), Op0.getOperand(0));
return SDValue(); return SDValue();
} }
@ -4748,7 +4748,7 @@ static SDValue PerformVDUPLANECombine(SDNode *N, SelectionDAG &DAG) {
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
// Ignore bit_converts. // Ignore bit_converts.
while (Op.getOpcode() == ISD::BIT_CONVERT) while (Op.getOpcode() == ISD::BITCAST)
Op = Op.getOperand(0); Op = Op.getOperand(0);
if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM) if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
return SDValue(); return SDValue();
@ -4763,7 +4763,7 @@ static SDValue PerformVDUPLANECombine(SDNode *N, SelectionDAG &DAG) {
if (EltSize > VT.getVectorElementType().getSizeInBits()) if (EltSize > VT.getVectorElementType().getSizeInBits())
return SDValue(); return SDValue();
return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op); return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
} }
/// getVShiftImm - Check if this is a valid build_vector for the immediate /// getVShiftImm - Check if this is a valid build_vector for the immediate
@ -4771,7 +4771,7 @@ static SDValue PerformVDUPLANECombine(SDNode *N, SelectionDAG &DAG) {
/// build_vector must have the same constant integer value. /// build_vector must have the same constant integer value.
static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) { static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
// Ignore bit_converts. // Ignore bit_converts.
while (Op.getOpcode() == ISD::BIT_CONVERT) while (Op.getOpcode() == ISD::BITCAST)
Op = Op.getOperand(0); Op = Op.getOperand(0);
BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
APInt SplatBits, SplatUndef; APInt SplatBits, SplatUndef;

6
llvm/lib/Target/Alpha/AlphaISelLowering.cpp
View File

@ -125,7 +125,7 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM)
setOperationAction(ISD::SETCC, MVT::f32, Promote); setOperationAction(ISD::SETCC, MVT::f32, Promote);
setOperationAction(ISD::BIT_CONVERT, MVT::f32, Promote); setOperationAction(ISD::BITCAST, MVT::f32, Promote);
setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
@ -616,7 +616,7 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op,
"Unhandled SINT_TO_FP type in custom expander!"); "Unhandled SINT_TO_FP type in custom expander!");
SDValue LD; SDValue LD;
bool isDouble = Op.getValueType() == MVT::f64; bool isDouble = Op.getValueType() == MVT::f64;
LD = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op.getOperand(0)); LD = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op.getOperand(0));
SDValue FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_, dl, SDValue FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_, dl,
isDouble?MVT::f64:MVT::f32, LD); isDouble?MVT::f64:MVT::f32, LD);
return FP; return FP;
@ -630,7 +630,7 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op,
src = DAG.getNode(AlphaISD::CVTTQ_, dl, MVT::f64, src); src = DAG.getNode(AlphaISD::CVTTQ_, dl, MVT::f64, src);
return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, src); return DAG.getNode(ISD::BITCAST, dl, MVT::i64, src);
} }
case ISD::ConstantPool: { case ISD::ConstantPool: {
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);

8
llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
View File

@ -1135,7 +1135,7 @@ SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, EVT OpVT,
// Here's where it gets interesting, because we have to parse out the // Here's where it gets interesting, because we have to parse out the
// subtree handed back in i64vec: // subtree handed back in i64vec:
if (i64vec.getOpcode() == ISD::BIT_CONVERT) { if (i64vec.getOpcode() == ISD::BITCAST) {
// The degenerate case where the upper and lower bits in the splat are // The degenerate case where the upper and lower bits in the splat are
// identical: // identical:
SDValue Op0 = i64vec.getOperand(0); SDValue Op0 = i64vec.getOperand(0);
@ -1149,7 +1149,7 @@ SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, EVT OpVT,
SDValue rhs = i64vec.getOperand(1); SDValue rhs = i64vec.getOperand(1);
SDValue shufmask = i64vec.getOperand(2); SDValue shufmask = i64vec.getOperand(2);
if (lhs.getOpcode() == ISD::BIT_CONVERT) { if (lhs.getOpcode() == ISD::BITCAST) {
ReplaceUses(lhs, lhs.getOperand(0)); ReplaceUses(lhs, lhs.getOperand(0));
lhs = lhs.getOperand(0); lhs = lhs.getOperand(0);
} }
@ -1158,7 +1158,7 @@ SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, EVT OpVT,
? lhs.getNode() ? lhs.getNode()
: emitBuildVector(lhs.getNode())); : emitBuildVector(lhs.getNode()));
if (rhs.getOpcode() == ISD::BIT_CONVERT) { if (rhs.getOpcode() == ISD::BITCAST) {
ReplaceUses(rhs, rhs.getOperand(0)); ReplaceUses(rhs, rhs.getOperand(0));
rhs = rhs.getOperand(0); rhs = rhs.getOperand(0);
} }
@ -1167,7 +1167,7 @@ SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, EVT OpVT,
? rhs.getNode() ? rhs.getNode()
: emitBuildVector(rhs.getNode())); : emitBuildVector(rhs.getNode()));
if (shufmask.getOpcode() == ISD::BIT_CONVERT) { if (shufmask.getOpcode() == ISD::BITCAST) {
ReplaceUses(shufmask, shufmask.getOperand(0)); ReplaceUses(shufmask, shufmask.getOperand(0));
shufmask = shufmask.getOperand(0); shufmask = shufmask.getOperand(0);
} }

60
llvm/lib/Target/CellSPU/SPUISelLowering.cpp
View File

@ -348,10 +348,10 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
setOperationAction(ISD::BIT_CONVERT, MVT::i32, Legal); setOperationAction(ISD::BITCAST, MVT::i32, Legal);
setOperationAction(ISD::BIT_CONVERT, MVT::f32, Legal); setOperationAction(ISD::BITCAST, MVT::f32, Legal);
setOperationAction(ISD::BIT_CONVERT, MVT::i64, Legal); setOperationAction(ISD::BITCAST, MVT::i64, Legal);
setOperationAction(ISD::BIT_CONVERT, MVT::f64, Legal); setOperationAction(ISD::BITCAST, MVT::f64, Legal);
// We cannot sextinreg(i1). Expand to shifts. // We cannot sextinreg(i1). Expand to shifts.
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
@ -665,7 +665,7 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
EVT vecVT = EVT::getVectorVT(*DAG.getContext(), EVT vecVT = EVT::getVectorVT(*DAG.getContext(),
InVT, (128 / InVT.getSizeInBits())); InVT, (128 / InVT.getSizeInBits()));
result = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, InVT, result = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, InVT,
DAG.getNode(ISD::BIT_CONVERT, dl, vecVT, result)); DAG.getNode(ISD::BITCAST, dl, vecVT, result));
} }
// When alignment is less than the size, we might need (known only at // When alignment is less than the size, we might need (known only at
// run-time) two loads // run-time) two loads
@ -682,7 +682,7 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
// get a registerfull of ones. (this implementation is a workaround: LLVM // get a registerfull of ones. (this implementation is a workaround: LLVM
// cannot handle 128 bit signed int constants) // cannot handle 128 bit signed int constants)
SDValue ones = DAG.getConstant(-1, MVT::v4i32 ); SDValue ones = DAG.getConstant(-1, MVT::v4i32 );
ones = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i128, ones); ones = DAG.getNode(ISD::BITCAST, dl, MVT::i128, ones);
SDValue high = DAG.getLoad(MVT::i128, dl, the_chain, SDValue high = DAG.getLoad(MVT::i128, dl, the_chain,
DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getNode(ISD::ADD, dl, PtrVT,
@ -708,7 +708,7 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
low = DAG.getNode(SPUISD::SHL_BYTES, dl, MVT::i128, low, offset ); low = DAG.getNode(SPUISD::SHL_BYTES, dl, MVT::i128, low, offset );
// Merge the two parts // Merge the two parts
result = DAG.getNode(ISD::BIT_CONVERT, dl, vecVT, result = DAG.getNode(ISD::BITCAST, dl, vecVT,
DAG.getNode(ISD::OR, dl, MVT::i128, low, high)); DAG.getNode(ISD::OR, dl, MVT::i128, low, high));
if (!InVT.isVector()) { if (!InVT.isVector()) {
@ -881,7 +881,7 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
result = DAG.getNode(SPUISD::SHUFB, dl, vecVT, result = DAG.getNode(SPUISD::SHUFB, dl, vecVT,
vectorizeOp, low, vectorizeOp, low,
DAG.getNode(ISD::BIT_CONVERT, dl, DAG.getNode(ISD::BITCAST, dl,
MVT::v4i32, insertEltOp)); MVT::v4i32, insertEltOp));
result = DAG.getStore(the_chain, dl, result, basePtr, result = DAG.getStore(the_chain, dl, result, basePtr,
@ -914,7 +914,7 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
MVT::i32)); MVT::i32));
// get a registerfull of ones // get a registerfull of ones
SDValue ones = DAG.getConstant(-1, MVT::v4i32); SDValue ones = DAG.getConstant(-1, MVT::v4i32);
ones = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i128, ones); ones = DAG.getNode(ISD::BITCAST, dl, MVT::i128, ones);
// Create the 128 bit masks that have ones where the data to store is // Create the 128 bit masks that have ones where the data to store is
// located. // located.
@ -928,13 +928,13 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
lowmask = DAG.getNode(SPUISD::SRL_BYTES, dl, MVT::i128, ones, surplus); lowmask = DAG.getNode(SPUISD::SRL_BYTES, dl, MVT::i128, ones, surplus);
lowmask = DAG.getNode(SPUISD::SHL_BYTES, dl, MVT::i128, lowmask, lowmask = DAG.getNode(SPUISD::SHL_BYTES, dl, MVT::i128, lowmask,
surplus); surplus);
Value = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i128, Value); Value = DAG.getNode(ISD::BITCAST, dl, MVT::i128, Value);
Value = DAG.getNode(ISD::AND, dl, MVT::i128, Value, lowmask); Value = DAG.getNode(ISD::AND, dl, MVT::i128, Value, lowmask);
} }
else { else {
lowmask = ones; lowmask = ones;
Value = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i128, Value); Value = DAG.getNode(ISD::BITCAST, dl, MVT::i128, Value);
} }
// this will zero, if there are no data that goes to the high quad // this will zero, if there are no data that goes to the high quad
himask = DAG.getNode(SPUISD::SHL_BYTES, dl, MVT::i128, lowmask, himask = DAG.getNode(SPUISD::SHL_BYTES, dl, MVT::i128, lowmask,
@ -953,10 +953,10 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
hi.getValue(1)); hi.getValue(1));
low = DAG.getNode(ISD::AND, dl, MVT::i128, low = DAG.getNode(ISD::AND, dl, MVT::i128,
DAG.getNode( ISD::BIT_CONVERT, dl, MVT::i128, low), DAG.getNode( ISD::BITCAST, dl, MVT::i128, low),
DAG.getNode( ISD::XOR, dl, MVT::i128, lowmask, ones)); DAG.getNode( ISD::XOR, dl, MVT::i128, lowmask, ones));
hi = DAG.getNode(ISD::AND, dl, MVT::i128, hi = DAG.getNode(ISD::AND, dl, MVT::i128,
DAG.getNode( ISD::BIT_CONVERT, dl, MVT::i128, hi), DAG.getNode( ISD::BITCAST, dl, MVT::i128, hi),
DAG.getNode( ISD::XOR, dl, MVT::i128, himask, ones)); DAG.getNode( ISD::XOR, dl, MVT::i128, himask, ones));
// Shift the Value to store into place. rlow contains the parts that go to // Shift the Value to store into place. rlow contains the parts that go to
@ -969,11 +969,11 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
// Merge the old data and the new data and store the results // Merge the old data and the new data and store the results
// Need to convert vectors here to integer as 'OR'ing floats assert // Need to convert vectors here to integer as 'OR'ing floats assert
rlow = DAG.getNode(ISD::OR, dl, MVT::i128, rlow = DAG.getNode(ISD::OR, dl, MVT::i128,
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i128, low), DAG.getNode(ISD::BITCAST, dl, MVT::i128, low),
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i128, rlow)); DAG.getNode(ISD::BITCAST, dl, MVT::i128, rlow));
rhi = DAG.getNode(ISD::OR, dl, MVT::i128, rhi = DAG.getNode(ISD::OR, dl, MVT::i128,
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i128, hi), DAG.getNode(ISD::BITCAST, dl, MVT::i128, hi),
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i128, rhi)); DAG.getNode(ISD::BITCAST, dl, MVT::i128, rhi));
low = DAG.getStore(the_chain, dl, rlow, basePtr, low = DAG.getStore(the_chain, dl, rlow, basePtr,
lowMemPtr, lowMemPtr,
@ -1095,7 +1095,7 @@ LowerConstantFP(SDValue Op, SelectionDAG &DAG) {
SDValue T = DAG.getConstant(dbits, MVT::i64); SDValue T = DAG.getConstant(dbits, MVT::i64);
SDValue Tvec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T); SDValue Tvec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T);
return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT, return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT,
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Tvec)); DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Tvec));
} }
return SDValue(); return SDValue();
@ -1671,7 +1671,7 @@ LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
&& "LowerBUILD_VECTOR: Unexpected floating point vector element."); && "LowerBUILD_VECTOR: Unexpected floating point vector element.");
// NOTE: pretend the constant is an integer. LLVM won't load FP constants // NOTE: pretend the constant is an integer. LLVM won't load FP constants
SDValue T = DAG.getConstant(Value32, MVT::i32); SDValue T = DAG.getConstant(Value32, MVT::i32);
return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, return DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,
DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, T,T,T,T)); DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, T,T,T,T));
break; break;
} }
@ -1681,7 +1681,7 @@ LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
&& "LowerBUILD_VECTOR: 64-bit float vector size > 8 bytes."); && "LowerBUILD_VECTOR: 64-bit float vector size > 8 bytes.");
// NOTE: pretend the constant is an integer. LLVM won't load FP constants // NOTE: pretend the constant is an integer. LLVM won't load FP constants
SDValue T = DAG.getConstant(f64val, MVT::i64); SDValue T = DAG.getConstant(f64val, MVT::i64);
return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, return DAG.getNode(ISD::BITCAST, dl, MVT::v2f64,
DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T)); DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T));
break; break;
} }
@ -1691,7 +1691,7 @@ LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
SmallVector<SDValue, 8> Ops; SmallVector<SDValue, 8> Ops;
Ops.assign(8, DAG.getConstant(Value16, MVT::i16)); Ops.assign(8, DAG.getConstant(Value16, MVT::i16));
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, return DAG.getNode(ISD::BITCAST, dl, VT,
DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i16, &Ops[0], Ops.size())); DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i16, &Ops[0], Ops.size()));
} }
case MVT::v8i16: { case MVT::v8i16: {
@ -1725,7 +1725,7 @@ SPU::LowerV2I64Splat(EVT OpVT, SelectionDAG& DAG, uint64_t SplatVal,
if (upper == lower) { if (upper == lower) {
// Magic constant that can be matched by IL, ILA, et. al. // Magic constant that can be matched by IL, ILA, et. al.
SDValue Val = DAG.getTargetConstant(upper, MVT::i32); SDValue Val = DAG.getTargetConstant(upper, MVT::i32);
return DAG.getNode(ISD::BIT_CONVERT, dl, OpVT, return DAG.getNode(ISD::BITCAST, dl, OpVT,
DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
Val, Val, Val, Val)); Val, Val, Val, Val));
} else { } else {
@ -1754,7 +1754,7 @@ SPU::LowerV2I64Splat(EVT OpVT, SelectionDAG& DAG, uint64_t SplatVal,
// Create lower vector if not a special pattern // Create lower vector if not a special pattern
if (!lower_special) { if (!lower_special) {
SDValue LO32C = DAG.getConstant(lower, MVT::i32); SDValue LO32C = DAG.getConstant(lower, MVT::i32);
LO32 = DAG.getNode(ISD::BIT_CONVERT, dl, OpVT, LO32 = DAG.getNode(ISD::BITCAST, dl, OpVT,
DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
LO32C, LO32C, LO32C, LO32C)); LO32C, LO32C, LO32C, LO32C));
} }
@ -1762,7 +1762,7 @@ SPU::LowerV2I64Splat(EVT OpVT, SelectionDAG& DAG, uint64_t SplatVal,
// Create upper vector if not a special pattern // Create upper vector if not a special pattern
if (!upper_special) { if (!upper_special) {
SDValue HI32C = DAG.getConstant(upper, MVT::i32); SDValue HI32C = DAG.getConstant(upper, MVT::i32);
HI32 = DAG.getNode(ISD::BIT_CONVERT, dl, OpVT, HI32 = DAG.getNode(ISD::BITCAST, dl, OpVT,
DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
HI32C, HI32C, HI32C, HI32C)); HI32C, HI32C, HI32C, HI32C));
} }
@ -2181,7 +2181,7 @@ static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
DAG.getNode(SPUISD::SHUFB, dl, VT, DAG.getNode(SPUISD::SHUFB, dl, VT,
DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, ValOp), DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, ValOp),
VecOp, VecOp,
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, ShufMask)); DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ShufMask));
return result; return result;
} }
@ -2301,12 +2301,12 @@ LowerByteImmed(SDValue Op, SelectionDAG &DAG) {
ConstVec = Op.getOperand(0); ConstVec = Op.getOperand(0);
Arg = Op.getOperand(1); Arg = Op.getOperand(1);
if (ConstVec.getNode()->getOpcode() != ISD::BUILD_VECTOR) { if (ConstVec.getNode()->getOpcode() != ISD::BUILD_VECTOR) {
if (ConstVec.getNode()->getOpcode() == ISD::BIT_CONVERT) { if (ConstVec.getNode()->getOpcode() == ISD::BITCAST) {
ConstVec = ConstVec.getOperand(0); ConstVec = ConstVec.getOperand(0);
} else { } else {
ConstVec = Op.getOperand(1); ConstVec = Op.getOperand(1);
Arg = Op.getOperand(0); Arg = Op.getOperand(0);
if (ConstVec.getNode()->getOpcode() == ISD::BIT_CONVERT) { if (ConstVec.getNode()->getOpcode() == ISD::BITCAST) {
ConstVec = ConstVec.getOperand(0); ConstVec = ConstVec.getOperand(0);
} }
} }
@ -2523,7 +2523,7 @@ static SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG,
// Take advantage of the fact that (truncate (sra arg, 32)) is efficiently // Take advantage of the fact that (truncate (sra arg, 32)) is efficiently
// selected to a NOP: // selected to a NOP:
SDValue i64lhs = DAG.getNode(ISD::BIT_CONVERT, dl, IntVT, lhs); SDValue i64lhs = DAG.getNode(ISD::BITCAST, dl, IntVT, lhs);
SDValue lhsHi32 = SDValue lhsHi32 =
DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
DAG.getNode(ISD::SRL, dl, IntVT, DAG.getNode(ISD::SRL, dl, IntVT,
@ -2557,7 +2557,7 @@ static SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG,
ISD::SETGT)); ISD::SETGT));
} }
SDValue i64rhs = DAG.getNode(ISD::BIT_CONVERT, dl, IntVT, rhs); SDValue i64rhs = DAG.getNode(ISD::BITCAST, dl, IntVT, rhs);
SDValue rhsHi32 = SDValue rhsHi32 =
DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
DAG.getNode(ISD::SRL, dl, IntVT, DAG.getNode(ISD::SRL, dl, IntVT,
@ -2754,7 +2754,7 @@ static SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG)
// and the input value into the lower 64 bits. // and the input value into the lower 64 bits.
SDValue extShuffle = DAG.getNode(SPUISD::SHUFB, dl, mvt, SDValue extShuffle = DAG.getNode(SPUISD::SHUFB, dl, mvt,
extended, sraVal, shufMask); extended, sraVal, shufMask);
return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i128, extShuffle); return DAG.getNode(ISD::BITCAST, dl, MVT::i128, extShuffle);
} }
//! Custom (target-specific) lowering entry point //! Custom (target-specific) lowering entry point

4
llvm/lib/Target/MBlaze/MBlazeISelLowering.cpp
View File

@ -116,8 +116,8 @@ MBlazeTargetLowering::MBlazeTargetLowering(MBlazeTargetMachine &TM)
} }
// Expand unsupported conversions // Expand unsupported conversions
setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); setOperationAction(ISD::BITCAST, MVT::f32, Expand);
setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); setOperationAction(ISD::BITCAST, MVT::i32, Expand);
// Expand SELECT_CC // Expand SELECT_CC
setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);

12
llvm/lib/Target/Mips/MipsISelLowering.cpp
View File

@ -364,7 +364,7 @@ LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const
// Emit the round instruction and bit convert to integer // Emit the round instruction and bit convert to integer
SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, MVT::f32, SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, MVT::f32,
Src, CondReg.getValue(1)); Src, CondReg.getValue(1));
SDValue BitCvt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Trunc); SDValue BitCvt = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Trunc);
return BitCvt; return BitCvt;
} }
@ -820,9 +820,9 @@ MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
case CCValAssign::Full: case CCValAssign::Full:
if (Subtarget->isABI_O32() && VA.isRegLoc()) { if (Subtarget->isABI_O32() && VA.isRegLoc()) {
if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32) if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Arg); Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) { if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg); Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg, SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
DAG.getConstant(0, getPointerTy())); DAG.getConstant(0, getPointerTy()));
SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg, SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
@ -1074,13 +1074,13 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain,
// Handle O32 ABI cases: i32->f32 and (i32,i32)->f64 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
if (Subtarget->isABI_O32()) { if (Subtarget->isABI_O32()) {
if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32) if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue); ArgValue = DAG.getNode(ISD::BITCAST, dl, MVT::f32, ArgValue);
if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) { if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(), unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
VA.getLocReg()+1, RC); VA.getLocReg()+1, RC);
SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT); SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
SDValue Hi = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue); SDValue Hi = DAG.getNode(ISD::BITCAST, dl, MVT::f32, ArgValue);
SDValue Lo = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue2); SDValue Lo = DAG.getNode(ISD::BITCAST, dl, MVT::f32, ArgValue2);
ArgValue = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::f64, Lo, Hi); ArgValue = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::f64, Lo, Hi);
} }
} }

55
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -178,10 +178,10 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); setOperationAction(ISD::BITCAST, MVT::f32, Expand);
setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); setOperationAction(ISD::BITCAST, MVT::i32, Expand);
setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand); setOperationAction(ISD::BITCAST, MVT::i64, Expand);
setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand); setOperationAction(ISD::BITCAST, MVT::f64, Expand);
// We cannot sextinreg(i1). Expand to shifts. // We cannot sextinreg(i1). Expand to shifts.
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
@ -3555,8 +3555,7 @@ SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op,
return SDValue(); return SDValue();
if (Op.getOperand(0).getValueType() == MVT::i64) { if (Op.getOperand(0).getValueType() == MVT::i64) {
SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, dl, SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op.getOperand(0));
MVT::f64, Op.getOperand(0));
SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits); SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits);
if (Op.getValueType() == MVT::f32) if (Op.getValueType() == MVT::f32)
FP = DAG.getNode(ISD::FP_ROUND, dl, FP = DAG.getNode(ISD::FP_ROUND, dl,
@ -3777,7 +3776,7 @@ static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
Ops.assign(CanonicalVT.getVectorNumElements(), Elt); Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
&Ops[0], Ops.size()); &Ops[0], Ops.size());
return DAG.getNode(ISD::BIT_CONVERT, dl, ReqVT, Res); return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
} }
/// BuildIntrinsicOp - Return a binary operator intrinsic node with the /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
@ -3806,14 +3805,14 @@ static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
EVT VT, SelectionDAG &DAG, DebugLoc dl) { EVT VT, SelectionDAG &DAG, DebugLoc dl) {
// Force LHS/RHS to be the right type. // Force LHS/RHS to be the right type.
LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, LHS); LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, RHS); RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
int Ops[16]; int Ops[16];
for (unsigned i = 0; i != 16; ++i) for (unsigned i = 0; i != 16; ++i)
Ops[i] = i + Amt; Ops[i] = i + Amt;
SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops); SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T); return DAG.getNode(ISD::BITCAST, dl, VT, T);
} }
// If this is a case we can't handle, return null and let the default // If this is a case we can't handle, return null and let the default
@ -3847,7 +3846,7 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
SDValue Z = DAG.getConstant(0, MVT::i32); SDValue Z = DAG.getConstant(0, MVT::i32);
Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z); Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
Op = DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Z); Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
} }
return Op; return Op;
} }
@ -3866,7 +3865,7 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl); SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl);
Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res); Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res);
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
} }
// If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
@ -3882,7 +3881,7 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
// xor by OnesV to invert it. // xor by OnesV to invert it.
Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV); Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
} }
// Check to see if this is a wide variety of vsplti*, binop self cases. // Check to see if this is a wide variety of vsplti*, binop self cases.
@ -3908,7 +3907,7 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
Intrinsic::ppc_altivec_vslw Intrinsic::ppc_altivec_vslw
}; };
Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
} }
// vsplti + srl self. // vsplti + srl self.
@ -3919,7 +3918,7 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
Intrinsic::ppc_altivec_vsrw Intrinsic::ppc_altivec_vsrw
}; };
Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
} }
// vsplti + sra self. // vsplti + sra self.
@ -3930,7 +3929,7 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
Intrinsic::ppc_altivec_vsraw Intrinsic::ppc_altivec_vsraw
}; };
Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
} }
// vsplti + rol self. // vsplti + rol self.
@ -3942,7 +3941,7 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
Intrinsic::ppc_altivec_vrlw Intrinsic::ppc_altivec_vrlw
}; };
Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
} }
// t = vsplti c, result = vsldoi t, t, 1 // t = vsplti c, result = vsldoi t, t, 1
@ -3969,14 +3968,14 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl); SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl);
SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl); SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS); LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS);
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS); return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS);
} }
// Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
if (SextVal >= -31 && SextVal <= 0) { if (SextVal >= -31 && SextVal <= 0) {
SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl); SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl);
SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl); SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS); LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS);
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS); return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS);
} }
return SDValue(); return SDValue();
@ -4053,10 +4052,10 @@ static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl); return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
} }
EVT VT = OpLHS.getValueType(); EVT VT = OpLHS.getValueType();
OpLHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpLHS); OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
OpRHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpRHS); OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs); SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T); return DAG.getNode(ISD::BITCAST, dl, VT, T);
} }
/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
@ -4244,7 +4243,7 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(), SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
Op.getOperand(1), Op.getOperand(2), Op.getOperand(1), Op.getOperand(2),
DAG.getConstant(CompareOpc, MVT::i32)); DAG.getConstant(CompareOpc, MVT::i32));
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Tmp); return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
} }
// Create the PPCISD altivec 'dot' comparison node. // Create the PPCISD altivec 'dot' comparison node.
@ -4327,9 +4326,9 @@ SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl); BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
// Shrinkify inputs to v8i16. // Shrinkify inputs to v8i16.
LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, LHS); LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHS); RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
RHSSwap = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHSSwap); RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
// Low parts multiplied together, generating 32-bit results (we ignore the // Low parts multiplied together, generating 32-bit results (we ignore the
// top parts). // top parts).
@ -4355,12 +4354,12 @@ SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
// Multiply the even 8-bit parts, producing 16-bit sums. // Multiply the even 8-bit parts, producing 16-bit sums.
SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
LHS, RHS, DAG, dl, MVT::v8i16); LHS, RHS, DAG, dl, MVT::v8i16);
EvenParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, EvenParts); EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
// Multiply the odd 8-bit parts, producing 16-bit sums. // Multiply the odd 8-bit parts, producing 16-bit sums.
SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
LHS, RHS, DAG, dl, MVT::v8i16); LHS, RHS, DAG, dl, MVT::v8i16);
OddParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OddParts); OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
// Merge the results together. // Merge the results together.
int Ops[16]; int Ops[16];

4
llvm/lib/Target/PowerPC/README.txt
View File

@ -285,8 +285,8 @@ including having this work sanely.
Fix Darwin FP-In-Integer Registers ABI Fix Darwin FP-In-Integer Registers ABI
Darwin passes doubles in structures in integer registers, which is very very Darwin passes doubles in structures in integer registers, which is very very
bad. Add something like a BIT_CONVERT to LLVM, then do an i-p transformation bad. Add something like a BITCAST to LLVM, then do an i-p transformation that
that percolates these things out of functions. percolates these things out of functions.
Check out how horrible this is: Check out how horrible this is:
http://gcc.gnu.org/ml/gcc/2005-10/msg01036.html http://gcc.gnu.org/ml/gcc/2005-10/msg01036.html

16
llvm/lib/Target/Sparc/SparcISelLowering.cpp
View File

@ -166,7 +166,7 @@ SparcTargetLowering::LowerFormalArguments(SDValue Chain,
MF.getRegInfo().addLiveIn(*CurArgReg++, VReg); MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Arg); Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
InVals.push_back(Arg); InVals.push_back(Arg);
} else { } else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset, int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
@ -219,7 +219,7 @@ SparcTargetLowering::LowerFormalArguments(SDValue Chain,
// If we want a double, do a bit convert. // If we want a double, do a bit convert.
if (ObjectVT == MVT::f64) if (ObjectVT == MVT::f64)
WholeValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, WholeValue); WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
InVals.push_back(WholeValue); InVals.push_back(WholeValue);
} }
@ -383,7 +383,7 @@ SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
ValToStore = Val; ValToStore = Val;
} else { } else {
// Convert this to a FP value in an int reg. // Convert this to a FP value in an int reg.
Val = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Val); Val = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Val);
RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val)); RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val));
} }
break; break;
@ -612,8 +612,8 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); setOperationAction(ISD::BITCAST, MVT::f32, Expand);
setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); setOperationAction(ISD::BITCAST, MVT::i32, Expand);
// Sparc has no select or setcc: expand to SELECT_CC. // Sparc has no select or setcc: expand to SELECT_CC.
setOperationAction(ISD::SELECT, MVT::i32, Expand); setOperationAction(ISD::SELECT, MVT::i32, Expand);
@ -805,13 +805,13 @@ static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
// Convert the fp value to integer in an FP register. // Convert the fp value to integer in an FP register.
assert(Op.getValueType() == MVT::i32); assert(Op.getValueType() == MVT::i32);
Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0)); Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
} }
static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
assert(Op.getOperand(0).getValueType() == MVT::i32); assert(Op.getOperand(0).getValueType() == MVT::i32);
SDValue Tmp = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0)); SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
// Convert the int value to FP in an FP register. // Convert the int value to FP in an FP register.
return DAG.getNode(SPISD::ITOF, dl, Op.getValueType(), Tmp); return DAG.getNode(SPISD::ITOF, dl, Op.getValueType(), Tmp);
} }
@ -925,7 +925,7 @@ static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
// Bit-Convert the value to f64. // Bit-Convert the value to f64.
SDValue Ops[2] = { SDValue Ops[2] = {
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, V), DAG.getNode(ISD::BITCAST, dl, MVT::f64, V),
V.getValue(1) V.getValue(1)
}; };
return DAG.getMergeValues(Ops, 2, dl); return DAG.getMergeValues(Ops, 2, dl);

4
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
View File

@ -147,8 +147,8 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
setOperationAction(ISD::FREM, MVT::f64, Expand); setOperationAction(ISD::FREM, MVT::f64, Expand);
// We have only 64-bit bitconverts // We have only 64-bit bitconverts
setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); setOperationAction(ISD::BITCAST, MVT::f32, Expand);
setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); setOperationAction(ISD::BITCAST, MVT::i32, Expand);
setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);

2
llvm/lib/Target/X86/X86FastISel.cpp
View File

@ -1579,7 +1579,7 @@ bool X86FastISel::X86SelectCall(const Instruction *I) {
} }
case CCValAssign::BCvt: { case CCValAssign::BCvt: {
unsigned BC = FastEmit_r(ArgVT.getSimpleVT(), VA.getLocVT(), unsigned BC = FastEmit_r(ArgVT.getSimpleVT(), VA.getLocVT(),
ISD::BIT_CONVERT, Arg, /*TODO: Kill=*/false); ISD::BITCAST, Arg, /*TODO: Kill=*/false);
assert(BC != 0 && "Failed to emit a bitcast!"); assert(BC != 0 && "Failed to emit a bitcast!");
Arg = BC; Arg = BC;
ArgVT = VA.getLocVT(); ArgVT = VA.getLocVT();

154
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -226,12 +226,12 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
// TODO: when we have SSE, these could be more efficient, by using movd/movq. // TODO: when we have SSE, these could be more efficient, by using movd/movq.
if (!X86ScalarSSEf64) { if (!X86ScalarSSEf64) {
setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand); setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
if (Subtarget->is64Bit()) { if (Subtarget->is64Bit()) {
setOperationAction(ISD::BIT_CONVERT , MVT::f64 , Expand); setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
// Without SSE, i64->f64 goes through memory. // Without SSE, i64->f64 goes through memory.
setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Expand); setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
} }
} }
@ -654,10 +654,10 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
setOperationAction(ISD::SELECT, MVT::v4i16, Expand); setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
setOperationAction(ISD::SELECT, MVT::v2i32, Expand); setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
setOperationAction(ISD::SELECT, MVT::v1i64, Expand); setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
setOperationAction(ISD::BIT_CONVERT, MVT::v8i8, Expand); setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
setOperationAction(ISD::BIT_CONVERT, MVT::v4i16, Expand); setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
setOperationAction(ISD::BIT_CONVERT, MVT::v2i32, Expand); setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
setOperationAction(ISD::BIT_CONVERT, MVT::v1i64, Expand); setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
if (!UseSoftFloat && Subtarget->hasSSE1()) { if (!UseSoftFloat && Subtarget->hasSSE1()) {
addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
@ -1293,13 +1293,13 @@ X86TargetLowering::LowerReturn(SDValue Chain,
if (Subtarget->is64Bit()) { if (Subtarget->is64Bit()) {
if (ValVT == MVT::x86mmx) { if (ValVT == MVT::x86mmx) {
if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy); ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
ValToCopy); ValToCopy);
// If we don't have SSE2 available, convert to v4f32 so the generated // If we don't have SSE2 available, convert to v4f32 so the generated
// register is legal. // register is legal.
if (!Subtarget->hasSSE2()) if (!Subtarget->hasSSE2())
ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32,ValToCopy); ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
} }
} }
} }
@ -1406,7 +1406,7 @@ X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
MVT::i64, InFlag).getValue(1); MVT::i64, InFlag).getValue(1);
Val = Chain.getValue(0); Val = Chain.getValue(0);
} }
Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val); Val = DAG.getNode(ISD::BITCAST, dl, CopyVT, Val);
} else { } else {
Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
CopyVT, InFlag).getValue(1); CopyVT, InFlag).getValue(1);
@ -1589,7 +1589,7 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain,
ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
DAG.getValueType(VA.getValVT())); DAG.getValueType(VA.getValVT()));
else if (VA.getLocInfo() == CCValAssign::BCvt) else if (VA.getLocInfo() == CCValAssign::BCvt)
ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
if (VA.isExtInLoc()) { if (VA.isExtInLoc()) {
// Handle MMX values passed in XMM regs. // Handle MMX values passed in XMM regs.
@ -1922,14 +1922,14 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
case CCValAssign::AExt: case CCValAssign::AExt:
if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
// Special case: passing MMX values in XMM registers. // Special case: passing MMX values in XMM registers.
Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg); Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
} else } else
Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
break; break;
case CCValAssign::BCvt: case CCValAssign::BCvt:
Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg); Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
break; break;
case CCValAssign::Indirect: { case CCValAssign::Indirect: {
// Store the argument. // Store the argument.
@ -3501,7 +3501,7 @@ static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8); Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
} }
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
} }
/// getOnesVector - Returns a vector of specified type with all bits set. /// getOnesVector - Returns a vector of specified type with all bits set.
@ -3514,7 +3514,7 @@ static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
SDValue Vec; SDValue Vec;
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
} }
@ -3599,9 +3599,9 @@ static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
// Perform the splat. // Perform the splat.
int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1); V1 = DAG.getNode(ISD::BITCAST, dl, PVT, V1);
V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]); V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1); return DAG.getNode(ISD::BITCAST, dl, VT, V1);
} }
/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
@ -3725,7 +3725,7 @@ SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
} }
// Actual nodes that may contain scalar elements // Actual nodes that may contain scalar elements
if (Opcode == ISD::BIT_CONVERT) { if (Opcode == ISD::BITCAST) {
V = V.getOperand(0); V = V.getOperand(0);
EVT SrcVT = V.getValueType(); EVT SrcVT = V.getValueType();
unsigned NumElems = VT.getVectorNumElements(); unsigned NumElems = VT.getVectorNumElements();
@ -3914,7 +3914,7 @@ static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
} }
} }
return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V); return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
} }
/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
@ -3955,8 +3955,8 @@ static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
const TargetLowering &TLI, DebugLoc dl) { const TargetLowering &TLI, DebugLoc dl) {
EVT ShVT = MVT::v2i64; EVT ShVT = MVT::v2i64;
unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp); SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, return DAG.getNode(ISD::BITCAST, dl, VT,
DAG.getNode(Opc, dl, ShVT, SrcOp, DAG.getNode(Opc, dl, ShVT, SrcOp,
DAG.getConstant(NumBits, TLI.getShiftAmountTy()))); DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
} }
@ -4023,8 +4023,8 @@ X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
LD->getPointerInfo().getWithOffset(StartOffset), LD->getPointerInfo().getWithOffset(StartOffset),
false, false, 0); false, false, 0);
// Canonicalize it to a v4i32 shuffle. // Canonicalize it to a v4i32 shuffle.
V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1); V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, return DAG.getNode(ISD::BITCAST, dl, VT,
DAG.getVectorShuffle(MVT::v4i32, dl, V1, DAG.getVectorShuffle(MVT::v4i32, dl, V1,
DAG.getUNDEF(MVT::v4i32),&Mask[0])); DAG.getUNDEF(MVT::v4i32),&Mask[0]));
} }
@ -4092,7 +4092,7 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
SDValue ResNode = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, SDValue ResNode = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys,
Ops, 2, MVT::i32, Ops, 2, MVT::i32,
LDBase->getMemOperand()); LDBase->getMemOperand());
return DAG.getNode(ISD::BIT_CONVERT, DL, VT, ResNode); return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
} }
return SDValue(); return SDValue();
} }
@ -4184,7 +4184,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
DAG.getUNDEF(Item.getValueType()), DAG.getUNDEF(Item.getValueType()),
&Mask[0]); &Mask[0]);
} }
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item); return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item);
} }
} }
@ -4208,7 +4208,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item); Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
Item = getShuffleVectorZeroOrUndef(Item, 0, true, Item = getShuffleVectorZeroOrUndef(Item, 0, true,
Subtarget->hasSSE2(), DAG); Subtarget->hasSSE2(), DAG);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item); return DAG.getNode(ISD::BITCAST, dl, VT, Item);
} }
} }
@ -4401,21 +4401,21 @@ X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
ResVT == MVT::v8i16 || ResVT == MVT::v16i8); ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
int Mask[2]; int Mask[2];
SDValue InVec = DAG.getNode(ISD::BIT_CONVERT,dl, MVT::v1i64, Op.getOperand(0)); SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
InVec = Op.getOperand(1); InVec = Op.getOperand(1);
if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
unsigned NumElts = ResVT.getVectorNumElements(); unsigned NumElts = ResVT.getVectorNumElements();
VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp); VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
} else { } else {
InVec = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64, InVec); InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
Mask[0] = 0; Mask[1] = 2; Mask[0] = 0; Mask[1] = 2;
VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
} }
return DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp); return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
} }
// v8i16 shuffles - Prefer shuffles in the following order: // v8i16 shuffles - Prefer shuffles in the following order:
@ -4497,9 +4497,9 @@ X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad); MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad); MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
NewV = DAG.getVectorShuffle(MVT::v2i64, dl, NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1), DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]); DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV); NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
// Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
// source words for the shuffle, to aid later transformations. // source words for the shuffle, to aid later transformations.
@ -4568,12 +4568,12 @@ X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
} }
V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1); V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
DAG.getNode(ISD::BUILD_VECTOR, dl, DAG.getNode(ISD::BUILD_VECTOR, dl,
MVT::v16i8, &pshufbMask[0], 16)); MVT::v16i8, &pshufbMask[0], 16));
if (!TwoInputs) if (!TwoInputs)
return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
// Calculate the shuffle mask for the second input, shuffle it, and // Calculate the shuffle mask for the second input, shuffle it, and
// OR it with the first shuffled input. // OR it with the first shuffled input.
@ -4588,12 +4588,12 @@ X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
} }
V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2); V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
DAG.getNode(ISD::BUILD_VECTOR, dl, DAG.getNode(ISD::BUILD_VECTOR, dl,
MVT::v16i8, &pshufbMask[0], 16)); MVT::v16i8, &pshufbMask[0], 16));
V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
} }
// If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
@ -4760,8 +4760,8 @@ SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
// No SSSE3 - Calculate in place words and then fix all out of place words // No SSSE3 - Calculate in place words and then fix all out of place words
// With 0-16 extracts & inserts. Worst case is 16 bytes out of order from // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
// the 16 different words that comprise the two doublequadword input vectors. // the 16 different words that comprise the two doublequadword input vectors.
V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2); V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
SDValue NewV = V2Only ? V2 : V1; SDValue NewV = V2Only ? V2 : V1;
for (int i = 0; i != 8; ++i) { for (int i = 0; i != 8; ++i) {
int Elt0 = MaskVals[i*2]; int Elt0 = MaskVals[i*2];
@ -4823,7 +4823,7 @@ SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
DAG.getIntPtrConstant(i)); DAG.getIntPtrConstant(i));
} }
return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV); return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
} }
/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
@ -4867,8 +4867,8 @@ SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
MaskVec.push_back(StartIdx / Scale); MaskVec.push_back(StartIdx / Scale);
} }
V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1); V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2); V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
} }
@ -4887,11 +4887,11 @@ static SDValue getVZextMovL(EVT VT, EVT OpVT,
MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) && if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT && SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
// PR2108 // PR2108
OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, return DAG.getNode(ISD::BITCAST, dl, VT,
DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
OpVT, OpVT,
@ -4901,9 +4901,9 @@ static SDValue getVZextMovL(EVT VT, EVT OpVT,
} }
} }
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, return DAG.getNode(ISD::BITCAST, dl, VT,
DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
DAG.getNode(ISD::BIT_CONVERT, dl, DAG.getNode(ISD::BITCAST, dl,
OpVT, SrcOp))); OpVT, SrcOp)));
} }
@ -5057,7 +5057,7 @@ LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
} }
static bool MayFoldVectorLoad(SDValue V) { static bool MayFoldVectorLoad(SDValue V) {
if (V.hasOneUse() && V.getOpcode() == ISD::BIT_CONVERT) if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
V = V.getOperand(0); V = V.getOperand(0);
if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
V = V.getOperand(0); V = V.getOperand(0);
@ -5074,7 +5074,7 @@ static bool MayFoldVectorLoad(SDValue V) {
// one use. Remove this version after this bug get fixed. // one use. Remove this version after this bug get fixed.
// rdar://8434668, PR8156 // rdar://8434668, PR8156
static bool RelaxedMayFoldVectorLoad(SDValue V) { static bool RelaxedMayFoldVectorLoad(SDValue V) {
if (V.hasOneUse() && V.getOpcode() == ISD::BIT_CONVERT) if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
V = V.getOperand(0); V = V.getOperand(0);
if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
V = V.getOperand(0); V = V.getOperand(0);
@ -5112,7 +5112,7 @@ bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
// If the bit convert changed the number of elements, it is unsafe // If the bit convert changed the number of elements, it is unsafe
// to examine the mask. // to examine the mask.
bool HasShuffleIntoBitcast = false; bool HasShuffleIntoBitcast = false;
if (V.getOpcode() == ISD::BIT_CONVERT) { if (V.getOpcode() == ISD::BITCAST) {
EVT SrcVT = V.getOperand(0).getValueType(); EVT SrcVT = V.getOperand(0).getValueType();
if (SrcVT.getVectorNumElements() != VT.getVectorNumElements()) if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
return false; return false;
@ -5127,7 +5127,7 @@ bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1); V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
// Skip one more bit_convert if necessary // Skip one more bit_convert if necessary
if (V.getOpcode() == ISD::BIT_CONVERT) if (V.getOpcode() == ISD::BITCAST)
V = V.getOperand(0); V = V.getOperand(0);
if (ISD::isNormalLoad(V.getNode())) { if (ISD::isNormalLoad(V.getNode())) {
@ -5164,8 +5164,8 @@ SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
// Canonizalize to v2f64. // Canonizalize to v2f64.
V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, V1); V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, return DAG.getNode(ISD::BITCAST, dl, VT,
getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64, getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
V1, DAG)); V1, DAG));
} }
@ -5319,7 +5319,7 @@ SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
if (VT == MVT::v8i16 || VT == MVT::v16i8) { if (VT == MVT::v8i16 || VT == MVT::v16i8) {
SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
if (NewOp.getNode()) if (NewOp.getNode())
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, NewOp); return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
} else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
// FIXME: Figure out a cleaner way to do this. // FIXME: Figure out a cleaner way to do this.
// Try to make use of movq to zero out the top part. // Try to make use of movq to zero out the top part.
@ -5629,7 +5629,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
if (Idx == 0) if (Idx == 0)
return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
DAG.getNode(ISD::BIT_CONVERT, dl, DAG.getNode(ISD::BITCAST, dl,
MVT::v4i32, MVT::v4i32,
Op.getOperand(0)), Op.getOperand(0)),
Op.getOperand(1))); Op.getOperand(1)));
@ -5650,14 +5650,14 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
if ((User->getOpcode() != ISD::STORE || if ((User->getOpcode() != ISD::STORE ||
(isa<ConstantSDNode>(Op.getOperand(1)) && (isa<ConstantSDNode>(Op.getOperand(1)) &&
cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
(User->getOpcode() != ISD::BIT_CONVERT || (User->getOpcode() != ISD::BITCAST ||
User->getValueType(0) != MVT::i32)) User->getValueType(0) != MVT::i32))
return SDValue(); return SDValue();
SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
Op.getOperand(0)), Op.getOperand(0)),
Op.getOperand(1)); Op.getOperand(1));
return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract); return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
} else if (VT == MVT::i32) { } else if (VT == MVT::i32) {
// ExtractPS works with constant index. // ExtractPS works with constant index.
if (isa<ConstantSDNode>(Op.getOperand(1))) if (isa<ConstantSDNode>(Op.getOperand(1)))
@ -5688,7 +5688,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
if (Idx == 0) if (Idx == 0)
return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
DAG.getNode(ISD::BIT_CONVERT, dl, DAG.getNode(ISD::BITCAST, dl,
MVT::v4i32, Vec), MVT::v4i32, Vec),
Op.getOperand(1))); Op.getOperand(1)));
// Transform it so it match pextrw which produces a 32-bit result. // Transform it so it match pextrw which produces a 32-bit result.
@ -5819,7 +5819,7 @@ X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 && assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
"Expected an SSE type!"); "Expected an SSE type!");
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt)); DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
} }
@ -6390,7 +6390,7 @@ SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
MachinePointerInfo::getConstantPool(), MachinePointerInfo::getConstantPool(),
false, false, 16); false, false, 16);
SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0); SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2); SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2);
SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
MachinePointerInfo::getConstantPool(), MachinePointerInfo::getConstantPool(),
false, false, 16); false, false, 16);
@ -6420,19 +6420,19 @@ SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
DAG.getIntPtrConstant(0))); DAG.getIntPtrConstant(0)));
Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load), DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
DAG.getIntPtrConstant(0)); DAG.getIntPtrConstant(0));
// Or the load with the bias. // Or the load with the bias.
SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
MVT::v2f64, Load)), MVT::v2f64, Load)),
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
MVT::v2f64, Bias))); MVT::v2f64, Bias)));
Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or), DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
DAG.getIntPtrConstant(0)); DAG.getIntPtrConstant(0));
// Subtract the bias. // Subtract the bias.
@ -6690,11 +6690,11 @@ SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
MachinePointerInfo::getConstantPool(), MachinePointerInfo::getConstantPool(),
false, false, 16); false, false, 16);
if (VT.isVector()) { if (VT.isVector()) {
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, return DAG.getNode(ISD::BITCAST, dl, VT,
DAG.getNode(ISD::XOR, dl, MVT::v2i64, DAG.getNode(ISD::XOR, dl, MVT::v2i64,
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
Op.getOperand(0)), Op.getOperand(0)),
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask))); DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Mask)));
} else { } else {
return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
} }
@ -6746,7 +6746,7 @@ SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
DAG.getConstant(32, MVT::i32)); DAG.getConstant(32, MVT::i32));
SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit); SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
DAG.getIntPtrConstant(0)); DAG.getIntPtrConstant(0));
} }
@ -7895,7 +7895,7 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
} }
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt); ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
DAG.getConstant(NewIntNo, MVT::i32), DAG.getConstant(NewIntNo, MVT::i32),
Op.getOperand(1), ShAmt); Op.getOperand(1), ShAmt);
@ -8329,7 +8329,7 @@ SDValue X86TargetLowering::LowerSHL(SDValue Op, SelectionDAG &DAG) const {
false, false, 16); false, false, 16);
Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend); Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, Op); Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
return DAG.getNode(ISD::MUL, dl, VT, Op, R); return DAG.getNode(ISD::MUL, dl, VT, Op, R);
} }
@ -8550,16 +8550,16 @@ SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
return DAG.getMergeValues(Ops, 2, dl); return DAG.getMergeValues(Ops, 2, dl);
} }
SDValue X86TargetLowering::LowerBIT_CONVERT(SDValue Op, SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
EVT SrcVT = Op.getOperand(0).getValueType(); EVT SrcVT = Op.getOperand(0).getValueType();
EVT DstVT = Op.getValueType(); EVT DstVT = Op.getValueType();
assert((Subtarget->is64Bit() && !Subtarget->hasSSE2() && assert((Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
Subtarget->hasMMX() && !DisableMMX) && Subtarget->hasMMX() && !DisableMMX) &&
"Unexpected custom BIT_CONVERT"); "Unexpected custom BITCAST");
assert((DstVT == MVT::i64 || assert((DstVT == MVT::i64 ||
(DstVT.isVector() && DstVT.getSizeInBits()==64)) && (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
"Unexpected custom BIT_CONVERT"); "Unexpected custom BITCAST");
// i64 <=> MMX conversions are Legal. // i64 <=> MMX conversions are Legal.
if (SrcVT==MVT::i64 && DstVT.isVector()) if (SrcVT==MVT::i64 && DstVT.isVector())
return Op; return Op;
@ -8642,7 +8642,7 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::SMULO: case ISD::SMULO:
case ISD::UMULO: return LowerXALUO(Op, DAG); case ISD::UMULO: return LowerXALUO(Op, DAG);
case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
case ISD::BIT_CONVERT: return LowerBIT_CONVERT(Op, DAG); case ISD::BITCAST: return LowerBITCAST(Op, DAG);
} }
} }
@ -11177,13 +11177,13 @@ static SDValue PerformBTCombine(SDNode *N,
static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
SDValue Op = N->getOperand(0); SDValue Op = N->getOperand(0);
if (Op.getOpcode() == ISD::BIT_CONVERT) if (Op.getOpcode() == ISD::BITCAST)
Op = Op.getOperand(0); Op = Op.getOperand(0);
EVT VT = N->getValueType(0), OpVT = Op.getValueType(); EVT VT = N->getValueType(0), OpVT = Op.getValueType();
if (Op.getOpcode() == X86ISD::VZEXT_LOAD && if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
VT.getVectorElementType().getSizeInBits() == VT.getVectorElementType().getSizeInBits() ==
OpVT.getVectorElementType().getSizeInBits()) { OpVT.getVectorElementType().getSizeInBits()) {
return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op); return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
} }
return SDValue(); return SDValue();
} }

2
llvm/lib/Target/X86/X86ISelLowering.h
View File

@ -740,7 +740,7 @@ namespace llvm {
SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const; SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
SelectionDAG &DAG) const; SelectionDAG &DAG) const;
SDValue LowerBIT_CONVERT(SDValue op, SelectionDAG &DAG) const; SDValue LowerBITCAST(SDValue op, SelectionDAG &DAG) const;
SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const; SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;