forked from OSchip/llvm-project
[AArch64] Regenerate 3 codegen test files. NFC
This commit is contained in:
David Green
parent
47bfc365fc
commit
527b8ccde5
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@ -1,3 +1,4 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O3 < %s -aarch64-enable-atomic-cfg-tidy=0 -aarch64-enable-gep-opt=false -verify-machineinstrs | FileCheck %s
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target triple = "arm64-apple-ios"
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@ -5,16 +6,20 @@ target triple = "arm64-apple-ios"
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; CSE between "icmp reg reg" and "sub reg reg".
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; Both can be in the same basic block or in different basic blocks.
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define i8* @t1(i8* %base, i32* nocapture %offset, i32 %size) nounwind {
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entry:
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; CHECK-LABEL: t1:
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; CHECK: subs
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; CHECK-NOT: cmp
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; CHECK-NOT: sub
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; CHECK: b.ge
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; CHECK: sub
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; CHECK-NEXT: add
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; CHECK-NOT: sub
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; CHECK: ret
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: ldr w9, [x1]
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; CHECK-NEXT: subs w8, w9, w2
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; CHECK-NEXT: b.ge LBB0_2
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; CHECK-NEXT: ; %bb.1:
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; CHECK-NEXT: mov x0, xzr
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; CHECK-NEXT: ret
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; CHECK-NEXT: LBB0_2: ; %if.end
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; CHECK-NEXT: sub w9, w9, w8
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; CHECK-NEXT: add x0, x0, w8, sxtw
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; CHECK-NEXT: str w9, [x1]
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; CHECK-NEXT: ret
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entry:
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%0 = load i32, i32* %offset, align 4
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%cmp = icmp slt i32 %0, %size
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%s = sub nsw i32 %0, %size
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@ -35,14 +40,19 @@ return:
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; CSE between "icmp reg imm" and "sub reg imm".
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define i8* @t2(i8* %base, i32* nocapture %offset) nounwind {
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entry:
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; CHECK-LABEL: t2:
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; CHECK: subs
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; CHECK-NOT: cmp
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; CHECK-NOT: sub
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; CHECK: b.lt
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; CHECK-NOT: sub
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; CHECK: ret
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: ldr w8, [x1]
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; CHECK-NEXT: subs w8, w8, #1
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; CHECK-NEXT: b.lt LBB1_2
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; CHECK-NEXT: ; %bb.1: ; %if.end
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; CHECK-NEXT: add x0, x0, w8, sxtw
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; CHECK-NEXT: str w8, [x1]
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; CHECK-NEXT: ret
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; CHECK-NEXT: LBB1_2:
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; CHECK-NEXT: mov x0, xzr
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; CHECK-NEXT: ret
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entry:
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%0 = load i32, i32* %offset, align 4
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%cmp = icmp slt i32 %0, 1
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br i1 %cmp, label %return, label %if.end
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@ -1,3 +1,4 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=arm64-apple-ios7.0 -frame-pointer=all -o - %s | FileCheck %s
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; When generating DAG selection tables, TableGen used to only flag an
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@ -13,11 +14,27 @@ declare void @bar(i8*)
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define i64 @test_chains() {
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; CHECK-LABEL: test_chains:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: sub sp, sp, #32
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
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; CHECK-NEXT: add x29, sp, #16
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; CHECK-NEXT: .cfi_def_cfa w29, 16
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; CHECK-NEXT: .cfi_offset w30, -8
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; CHECK-NEXT: .cfi_offset w29, -16
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; CHECK-NEXT: sub x0, x29, #1
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; CHECK-NEXT: bl _bar
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; CHECK-NEXT: ldurb w8, [x29, #-1]
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; CHECK-NEXT: add x8, x8, #1
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; CHECK-NEXT: and x0, x8, #0xff
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; CHECK-NEXT: sturb w8, [x29, #-1]
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; CHECK-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
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; CHECK-NEXT: add sp, sp, #32
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; CHECK-NEXT: ret
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%locvar = alloca i8
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call void @bar(i8* %locvar)
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; CHECK: bl {{_?bar}}
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%inc.1 = load i8, i8* %locvar
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%inc.2 = zext i8 %inc.1 to i64
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@ -25,13 +42,8 @@ define i64 @test_chains() {
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%inc.4 = trunc i64 %inc.3 to i8
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store i8 %inc.4, i8* %locvar
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; CHECK: ldurb {{w[0-9]+}}, [x29, [[LOCADDR:#-?[0-9]+]]]
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; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, #1
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; CHECK: and x0, x[[STRVAL:[0-9]+]], #0xff
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; CHECK: sturb w[[STRVAL]], [x29, [[LOCADDR]]]
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%ret.1 = load i8, i8* %locvar
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%ret.2 = zext i8 %ret.1 to i64
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ret i64 %ret.2
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; CHECK: ret
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}
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@ -1,3 +1,4 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve < %s | FileCheck %s
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;
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@ -6,8 +7,9 @@
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define <vscale x 2 x i64> @masked_sload_nxv2i8(<vscale x 2 x i8> *%a, <vscale x 2 x i1> %mask) {
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; CHECK-LABEL: masked_sload_nxv2i8:
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; CHECK: ld1sb { [[IN:z[0-9]+]].d }, [[PG:p[0-9]+]]/z, [x0]
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; CHECK-NEXT: ret
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1sb { z0.d }, p0/z, [x0]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i8> @llvm.masked.load.nxv2i8(<vscale x 2 x i8> *%a, i32 1, <vscale x 2 x i1> %mask, <vscale x 2 x i8> undef)
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%ext = sext <vscale x 2 x i8> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %ext
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@ -15,8 +17,9 @@ define <vscale x 2 x i64> @masked_sload_nxv2i8(<vscale x 2 x i8> *%a, <vscale x
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define <vscale x 2 x i64> @masked_sload_nxv2i16(<vscale x 2 x i16> *%a, <vscale x 2 x i1> %mask) {
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; CHECK-LABEL: masked_sload_nxv2i16:
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; CHECK: ld1sh { [[IN:z[0-9]+]].d }, [[PG:p[0-9]+]]/z, [x0]
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; CHECK-NEXT: ret
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1sh { z0.d }, p0/z, [x0]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i16> @llvm.masked.load.nxv2i16(<vscale x 2 x i16> *%a, i32 1, <vscale x 2 x i1> %mask, <vscale x 2 x i16> undef)
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%ext = sext <vscale x 2 x i16> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %ext
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@ -24,8 +27,9 @@ define <vscale x 2 x i64> @masked_sload_nxv2i16(<vscale x 2 x i16> *%a, <vscale
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define <vscale x 2 x i64> @masked_sload_nxv2i32(<vscale x 2 x i32> *%a, <vscale x 2 x i1> %mask) {
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; CHECK-LABEL: masked_sload_nxv2i32:
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; CHECK: ld1sw { [[IN:z[0-9]+]].d }, [[PG:p[0-9]+]]/z, [x0]
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; CHECK-NEXT: ret
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1sw { z0.d }, p0/z, [x0]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i32> @llvm.masked.load.nxv2i32(<vscale x 2 x i32> *%a, i32 1, <vscale x 2 x i1> %mask, <vscale x 2 x i32> undef)
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%ext = sext <vscale x 2 x i32> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %ext
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@ -33,8 +37,9 @@ define <vscale x 2 x i64> @masked_sload_nxv2i32(<vscale x 2 x i32> *%a, <vscale
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define <vscale x 4 x i32> @masked_sload_nxv4i8(<vscale x 4 x i8> *%a, <vscale x 4 x i1> %mask) {
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; CHECK-LABEL: masked_sload_nxv4i8:
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; CHECK: ld1sb { [[IN:z[0-9]+]].s }, [[PG:p[0-9]+]]/z, [x0]
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; CHECK-NEXT: ret
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1sb { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ret
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%load = call <vscale x 4 x i8> @llvm.masked.load.nxv4i8(<vscale x 4 x i8> *%a, i32 1, <vscale x 4 x i1> %mask, <vscale x 4 x i8> undef)
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%ext = sext <vscale x 4 x i8> %load to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %ext
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@ -42,8 +47,9 @@ define <vscale x 4 x i32> @masked_sload_nxv4i8(<vscale x 4 x i8> *%a, <vscale x
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define <vscale x 4 x i32> @masked_sload_nxv4i16(<vscale x 4 x i16> *%a, <vscale x 4 x i1> %mask) {
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; CHECK-LABEL: masked_sload_nxv4i16:
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; CHECK: ld1sh { [[IN:z[0-9]+]].s }, [[PG:p[0-9]+]]/z, [x0]
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; CHECK-NEXT: ret
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1sh { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ret
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%load = call <vscale x 4 x i16> @llvm.masked.load.nxv4i16(<vscale x 4 x i16> *%a, i32 1, <vscale x 4 x i1> %mask, <vscale x 4 x i16> undef)
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%ext = sext <vscale x 4 x i16> %load to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %ext
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@ -51,8 +57,9 @@ define <vscale x 4 x i32> @masked_sload_nxv4i16(<vscale x 4 x i16> *%a, <vscale
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define <vscale x 8 x i16> @masked_sload_nxv8i8(<vscale x 8 x i8> *%a, <vscale x 8 x i1> %mask) {
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; CHECK-LABEL: masked_sload_nxv8i8:
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; CHECK: ld1sb { [[IN:z[0-9]+]].h }, [[PG:p[0-9]+]]/z, [x0]
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; CHECK-NEXT: ret
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1sb { z0.h }, p0/z, [x0]
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; CHECK-NEXT: ret
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%load = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8(<vscale x 8 x i8> *%a, i32 1, <vscale x 8 x i1> %mask, <vscale x 8 x i8> undef)
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%ext = sext <vscale x 8 x i8> %load to <vscale x 8 x i16>
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ret <vscale x 8 x i16> %ext
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@ -60,11 +67,12 @@ define <vscale x 8 x i16> @masked_sload_nxv8i8(<vscale x 8 x i8> *%a, <vscale x
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define <vscale x 2 x i64> @masked_sload_passthru(<vscale x 2 x i32> *%a, <vscale x 2 x i1> %mask, <vscale x 2 x i32> %passthru) {
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; CHECK-LABEL: masked_sload_passthru:
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; CHECK: ld1sw { [[IN:z[0-9]+]].d }, [[PG1:p[0-9]+]]/z, [x0]
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; CHECK-NEXT: ptrue [[PG2:p[0-9]+]].d
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; CHECK-NEXT: sxtw z0.d, [[PG2]]/m, z0.d
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; CHECK-NEXT: mov z0.d, [[PG1]]/m, [[IN]].d
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; CHECK-NEXT: ret
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1sw { z1.d }, p0/z, [x0]
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; CHECK-NEXT: ptrue p1.d
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; CHECK-NEXT: sxtw z0.d, p1/m, z0.d
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; CHECK-NEXT: mov z0.d, p0/m, z1.d
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i32> @llvm.masked.load.nxv2i32(<vscale x 2 x i32> *%a, i32 1, <vscale x 2 x i1> %mask, <vscale x 2 x i32> %passthru)
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%ext = sext <vscale x 2 x i32> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %ext
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@ -73,7 +81,8 @@ define <vscale x 2 x i64> @masked_sload_passthru(<vscale x 2 x i32> *%a, <vscale
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; Return type requires splitting
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define <vscale x 16 x i32> @masked_sload_nxv16i8(<vscale x 16 x i8>* %a, <vscale x 16 x i1> %mask) {
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; CHECK-LABEL: masked_sload_nxv16i8:
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; CHECK: ld1b { z0.b }, p0/z, [x0]
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
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; CHECK-NEXT: sunpklo z1.h, z0.b
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; CHECK-NEXT: sunpkhi z3.h, z0.b
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; CHECK-NEXT: sunpklo z0.s, z1.h
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@ -89,7 +98,8 @@ define <vscale x 16 x i32> @masked_sload_nxv16i8(<vscale x 16 x i8>* %a, <vscale
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; Masked load requires promotion
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define <vscale x 4 x double> @masked_sload_4i8_4f32(<vscale x 4 x i8>* noalias %in, <vscale x 4 x i1> %mask) {
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; CHECK-LABEL: masked_sload_4i8_4f32:
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; CHECK: ld1sb { z0.s }, p0/z, [x0]
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1sb { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ptrue p1.d
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; CHECK-NEXT: sunpkhi z1.d, z0.s
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; CHECK-NEXT: sunpklo z0.d, z0.s
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