forked from OSchip/llvm-project
add X86-specific DAG optimization to simplify boolean test
- if a boolean test (X86ISD::CMP or X86ISD:SUB) checks a boolean value generated from X86ISD::SETCC, try to simplify the boolean value generation and checking by reusing the original EFLAGS with proper condition code - add hooks to X86 specific SETCC/BRCOND/CMOV, the major 3 places consuming EFLAGS part of patches fixing PR12312 llvm-svn: 161687
This commit is contained in:
Michael Liao
parent
a7020aee00
commit
5248e9913f
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@ -13782,6 +13782,72 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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}
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// Check whether a boolean test is testing a boolean value generated by
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// X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
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// code.
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//
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// Simplify the following patterns:
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// (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
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// (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
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// to (Op EFLAGS Cond)
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//
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// (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
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// (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
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// to (Op EFLAGS !Cond)
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//
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// where Op could be BRCOND or CMOV.
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//
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static SDValue BoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
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// Quit if not CMP and SUB with its value result used.
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if (Cmp.getOpcode() != X86ISD::CMP &&
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(Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
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return SDValue();
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// Quit if not used as a boolean value.
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if (CC != X86::COND_E && CC != X86::COND_NE)
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return SDValue();
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// Check CMP operands. One of them should be 0 or 1 and the other should be
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// an SetCC or extended from it.
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SDValue Op1 = Cmp.getOperand(0);
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SDValue Op2 = Cmp.getOperand(1);
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SDValue SetCC;
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const ConstantSDNode* C = 0;
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bool needOppositeCond = (CC == X86::COND_E);
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if ((C = dyn_cast<ConstantSDNode>(Op1)))
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SetCC = Op2;
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else if ((C = dyn_cast<ConstantSDNode>(Op2)))
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SetCC = Op1;
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else // Quit if all operands are not constants.
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return SDValue();
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if (C->getZExtValue() == 1)
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needOppositeCond = !needOppositeCond;
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else if (C->getZExtValue() != 0)
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// Quit if the constant is neither 0 or 1.
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return SDValue();
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// Skip 'zext' node.
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if (SetCC.getOpcode() == ISD::ZERO_EXTEND)
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SetCC = SetCC.getOperand(0);
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// Quit if not SETCC.
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// FIXME: So far we only handle the boolean value generated from SETCC. If
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// there is other ways to generate boolean values, we need handle them here
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// as well.
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if (SetCC.getOpcode() != X86ISD::SETCC)
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return SDValue();
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// Set the condition code or opposite one if necessary.
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CC = X86::CondCode(SetCC.getConstantOperandVal(0));
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if (needOppositeCond)
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CC = X86::GetOppositeBranchCondition(CC);
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return SetCC.getOperand(1);
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}
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/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
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static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI) {
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@ -13795,6 +13861,7 @@ static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
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SDValue TrueOp = N->getOperand(1);
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X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
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SDValue Cond = N->getOperand(3);
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if (CC == X86::COND_E || CC == X86::COND_NE) {
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switch (Cond.getOpcode()) {
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default: break;
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@ -13806,6 +13873,16 @@ static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
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}
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}
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SDValue Flags;
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Flags = BoolTestSetCCCombine(Cond, CC);
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if (Flags.getNode()) {
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SDValue Ops[] = { FalseOp, TrueOp,
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DAG.getConstant(CC, MVT::i8), Flags };
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return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
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Ops, array_lengthof(Ops));
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}
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// If this is a select between two integer constants, try to do some
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// optimizations. Note that the operands are ordered the opposite of SELECT
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// operands.
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@ -15285,19 +15362,50 @@ static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
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// Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
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static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
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unsigned X86CC = N->getConstantOperandVal(0);
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SDValue EFLAG = N->getOperand(1);
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DebugLoc DL = N->getDebugLoc();
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X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
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SDValue EFLAGS = N->getOperand(1);
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// Materialize "setb reg" as "sbb reg,reg", since it can be extended without
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// a zext and produces an all-ones bit which is more useful than 0/1 in some
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// cases.
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if (X86CC == X86::COND_B)
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if (CC == X86::COND_B)
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return DAG.getNode(ISD::AND, DL, MVT::i8,
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DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
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DAG.getConstant(X86CC, MVT::i8), EFLAG),
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DAG.getConstant(CC, MVT::i8), EFLAGS),
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DAG.getConstant(1, MVT::i8));
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SDValue Flags;
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Flags = BoolTestSetCCCombine(EFLAGS, CC);
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if (Flags.getNode()) {
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SDValue Cond = DAG.getConstant(CC, MVT::i8);
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return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
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}
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return SDValue();
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}
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// Optimize branch condition evaluation.
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//
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static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget *Subtarget) {
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DebugLoc DL = N->getDebugLoc();
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SDValue Chain = N->getOperand(0);
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SDValue Dest = N->getOperand(1);
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SDValue EFLAGS = N->getOperand(3);
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X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
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SDValue Flags;
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Flags = BoolTestSetCCCombine(EFLAGS, CC);
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if (Flags.getNode()) {
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SDValue Cond = DAG.getConstant(CC, MVT::i8);
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return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
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Flags);
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}
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return SDValue();
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}
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@ -15515,6 +15623,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);
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case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
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case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
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case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
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case X86ISD::SHUFP: // Handle all target specific shuffles
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case X86ISD::PALIGN:
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case X86ISD::UNPCKH:
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@ -0,0 +1,42 @@
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; RUN: llc < %s -march=x86-64 -mattr=+sse41,-avx | FileCheck %s
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define i32 @foo(<2 x i64> %c, i32 %a, i32 %b) {
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%t1 = call i32 @llvm.x86.sse41.ptestz(<2 x i64> %c, <2 x i64> %c)
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%t2 = icmp ne i32 %t1, 0
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%t3 = select i1 %t2, i32 %a, i32 %b
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ret i32 %t3
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; CHECK: foo
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; CHECK: ptest
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; CHECK-NOT: testl
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; CHECK: cmov
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; CHECK: ret
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}
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define i32 @bar(<2 x i64> %c) {
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entry:
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%0 = call i32 @llvm.x86.sse41.ptestz(<2 x i64> %c, <2 x i64> %c)
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%1 = icmp ne i32 %0, 0
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br i1 %1, label %if-true-block, label %endif-block
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if-true-block: ; preds = %entry
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ret i32 0
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endif-block: ; preds = %entry,
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ret i32 1
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; CHECK: bar
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; CHECK: ptest
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; CHECK-NOT: testl
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; CHECK: jne
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; CHECK: ret
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}
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define i32 @bax(<2 x i64> %c) {
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%t1 = call i32 @llvm.x86.sse41.ptestz(<2 x i64> %c, <2 x i64> %c)
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%t2 = icmp eq i32 %t1, 1
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%t3 = zext i1 %t2 to i32
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ret i32 %t3
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; CHECK: bax
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; CHECK: ptest
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; CHECK-NOT: cmpl
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; CHECK: ret
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}
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declare i32 @llvm.x86.sse41.ptestz(<2 x i64>, <2 x i64>) nounwind readnone
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