forked from OSchip/llvm-project
RuntimeDyldELF: refactor AArch64 relocations. NFC.
llvm-svn: 290606
This commit is contained in:
Eugene Leviant
parent
de1f4a4496
commit
5240a305a4
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@ -28,9 +28,34 @@
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using namespace llvm;
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using namespace llvm::object;
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using namespace llvm::support::endian;
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#define DEBUG_TYPE "dyld"
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static void or32le(void *P, int32_t V) { write32le(P, read32le(P) | V); }
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static void or32AArch64Imm(void *L, uint64_t Imm) {
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or32le(L, (Imm & 0xFFF) << 10);
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}
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template <class T> static void write(bool isBE, void *P, T V) {
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isBE ? write<T, support::big>(P, V) : write<T, support::little>(P, V);
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}
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static void write32AArch64Addr(void *L, uint64_t Imm) {
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uint32_t ImmLo = (Imm & 0x3) << 29;
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uint32_t ImmHi = (Imm & 0x1FFFFC) << 3;
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uint64_t Mask = (0x3 << 29) | (0x1FFFFC << 3);
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write32le(L, (read32le(L) & ~Mask) | ImmLo | ImmHi);
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}
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// Return the bits [Start, End] from Val shifted Start bits.
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// For instance, getBits(0xF0, 4, 8) returns 0xF.
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static uint64_t getBits(uint64_t Val, int Start, int End) {
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uint64_t Mask = ((uint64_t)1 << (End + 1 - Start)) - 1;
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return (Val >> Start) & Mask;
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}
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namespace {
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template <class ELFT> class DyldELFObject : public ELFObjectFile<ELFT> {
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@ -339,25 +364,14 @@ void RuntimeDyldELF::resolveAArch64Relocation(const SectionEntry &Section,
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default:
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llvm_unreachable("Relocation type not implemented yet!");
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break;
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case ELF::R_AARCH64_ABS64: {
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uint64_t *TargetPtr =
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reinterpret_cast<uint64_t *>(Section.getAddressWithOffset(Offset));
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if (isBE)
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support::ubig64_t::ref{TargetPtr} = Value + Addend;
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else
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support::ulittle64_t::ref{TargetPtr} = Value + Addend;
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case ELF::R_AARCH64_ABS64:
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write(isBE, TargetPtr, Value + Addend);
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break;
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}
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case ELF::R_AARCH64_PREL32: {
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uint64_t Result = Value + Addend - FinalAddress;
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assert(static_cast<int64_t>(Result) >= INT32_MIN &&
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static_cast<int64_t>(Result) <= UINT32_MAX);
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if (isBE)
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support::ubig32_t::ref{TargetPtr} =
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static_cast<uint32_t>(Result & 0xffffffffU);
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else
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support::ulittle32_t::ref{TargetPtr} =
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static_cast<uint32_t>(Result & 0xffffffffU);
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write(isBE, TargetPtr, static_cast<uint32_t>(Result & 0xffffffffU));
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break;
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}
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case ELF::R_AARCH64_CALL26: // fallthrough
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@ -365,132 +379,56 @@ void RuntimeDyldELF::resolveAArch64Relocation(const SectionEntry &Section,
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// Operation: S+A-P. Set Call or B immediate value to bits fff_fffc of the
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// calculation.
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uint64_t BranchImm = Value + Addend - FinalAddress;
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uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
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// "Check that -2^27 <= result < 2^27".
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assert(isInt<28>(BranchImm));
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// AArch64 code is emitted with .rela relocations. The data already in any
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// bits affected by the relocation on entry is garbage.
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TargetValue &= 0xfc000000U;
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// Immediate goes in bits 25:0 of B and BL.
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TargetValue |= static_cast<uint32_t>(BranchImm & 0xffffffcU) >> 2;
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support::ulittle32_t::ref{TargetPtr} = TargetValue;
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or32le(TargetPtr, (BranchImm & 0x0FFFFFFC) >> 2);
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break;
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}
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case ELF::R_AARCH64_MOVW_UABS_G3: {
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uint64_t Result = Value + Addend;
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uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
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// AArch64 code is emitted with .rela relocations. The data already in any
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// bits affected by the relocation on entry is garbage.
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TargetValue &= 0xffe0001fU;
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// Immediate goes in bits 20:5 of MOVZ/MOVK instruction
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TargetValue |= ((Result & 0xffff000000000000ULL) >> (48 - 5));
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// Shift must be "lsl #48", in bits 22:21
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assert((TargetValue >> 21 & 0x3) == 3 && "invalid shift for relocation");
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support::ulittle32_t::ref{TargetPtr} = TargetValue;
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case ELF::R_AARCH64_MOVW_UABS_G3:
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or32le(TargetPtr, ((Value + Addend) & 0xFFFF000000000000) >> 43);
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break;
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}
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case ELF::R_AARCH64_MOVW_UABS_G2_NC: {
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uint64_t Result = Value + Addend;
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uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
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// AArch64 code is emitted with .rela relocations. The data already in any
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// bits affected by the relocation on entry is garbage.
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TargetValue &= 0xffe0001fU;
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// Immediate goes in bits 20:5 of MOVZ/MOVK instruction
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TargetValue |= ((Result & 0xffff00000000ULL) >> (32 - 5));
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// Shift must be "lsl #32", in bits 22:21
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assert((TargetValue >> 21 & 0x3) == 2 && "invalid shift for relocation");
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support::ulittle32_t::ref{TargetPtr} = TargetValue;
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case ELF::R_AARCH64_MOVW_UABS_G2_NC:
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or32le(TargetPtr, ((Value + Addend) & 0xFFFF00000000) >> 27);
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break;
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}
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case ELF::R_AARCH64_MOVW_UABS_G1_NC: {
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uint64_t Result = Value + Addend;
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uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
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// AArch64 code is emitted with .rela relocations. The data already in any
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// bits affected by the relocation on entry is garbage.
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TargetValue &= 0xffe0001fU;
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// Immediate goes in bits 20:5 of MOVZ/MOVK instruction
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TargetValue |= ((Result & 0xffff0000U) >> (16 - 5));
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// Shift must be "lsl #16", in bits 22:2
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assert((TargetValue >> 21 & 0x3) == 1 && "invalid shift for relocation");
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support::ulittle32_t::ref{TargetPtr} = TargetValue;
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case ELF::R_AARCH64_MOVW_UABS_G1_NC:
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or32le(TargetPtr, ((Value + Addend) & 0xFFFF0000) >> 11);
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break;
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}
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case ELF::R_AARCH64_MOVW_UABS_G0_NC: {
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uint64_t Result = Value + Addend;
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uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
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// AArch64 code is emitted with .rela relocations. The data already in any
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// bits affected by the relocation on entry is garbage.
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TargetValue &= 0xffe0001fU;
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// Immediate goes in bits 20:5 of MOVZ/MOVK instruction
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TargetValue |= ((Result & 0xffffU) << 5);
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// Shift must be "lsl #0", in bits 22:21.
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assert((TargetValue >> 21 & 0x3) == 0 && "invalid shift for relocation");
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support::ulittle32_t::ref{TargetPtr} = TargetValue;
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case ELF::R_AARCH64_MOVW_UABS_G0_NC:
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or32le(TargetPtr, ((Value + Addend) & 0xFFFF) << 5);
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break;
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}
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case ELF::R_AARCH64_ADR_PREL_PG_HI21: {
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// Operation: Page(S+A) - Page(P)
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uint64_t Result =
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((Value + Addend) & ~0xfffULL) - (FinalAddress & ~0xfffULL);
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uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
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// Check that -2^32 <= X < 2^32
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assert(isInt<33>(Result) && "overflow check failed for relocation");
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// AArch64 code is emitted with .rela relocations. The data already in any
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// bits affected by the relocation on entry is garbage.
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TargetValue &= 0x9f00001fU;
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// Immediate goes in bits 30:29 + 5:23 of ADRP instruction, taken
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// from bits 32:12 of X.
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TargetValue |= ((Result & 0x3000U) << (29 - 12));
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TargetValue |= ((Result & 0x1ffffc000ULL) >> (14 - 5));
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support::ulittle32_t::ref{TargetPtr} = TargetValue;
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write32AArch64Addr(TargetPtr, Result >> 12);
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break;
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}
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case ELF::R_AARCH64_ADD_ABS_LO12_NC: {
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case ELF::R_AARCH64_ADD_ABS_LO12_NC:
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// Operation: S + A
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uint64_t Result = Value + Addend;
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// Immediate goes in bits 21:10 of LD/ST instruction, taken
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// from bits 11:0 of X
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*TargetPtr |= ((Result & 0xfff) << 10);
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or32AArch64Imm(TargetPtr, Value + Addend);
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break;
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}
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case ELF::R_AARCH64_LDST32_ABS_LO12_NC: {
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case ELF::R_AARCH64_LDST32_ABS_LO12_NC:
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// Operation: S + A
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uint64_t Result = Value + Addend;
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uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
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// AArch64 code is emitted with .rela relocations. The data already in any
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// bits affected by the relocation on entry is garbage.
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TargetValue &= 0xffc003ffU;
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// Immediate goes in bits 21:10 of LD/ST instruction, taken
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// from bits 11:2 of X
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TargetValue |= ((Result & 0xffc) << (10 - 2));
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support::ulittle32_t::ref{TargetPtr} = TargetValue;
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or32AArch64Imm(TargetPtr, getBits(Value + Addend, 2, 11));
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break;
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}
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case ELF::R_AARCH64_LDST64_ABS_LO12_NC: {
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case ELF::R_AARCH64_LDST64_ABS_LO12_NC:
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// Operation: S + A
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uint64_t Result = Value + Addend;
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uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
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// AArch64 code is emitted with .rela relocations. The data already in any
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// bits affected by the relocation on entry is garbage.
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TargetValue &= 0xffc003ffU;
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// Immediate goes in bits 21:10 of LD/ST instruction, taken
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// from bits 11:3 of X
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TargetValue |= ((Result & 0xff8) << (10 - 3));
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support::ulittle32_t::ref{TargetPtr} = TargetValue;
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or32AArch64Imm(TargetPtr, getBits(Value + Addend, 3, 11));
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break;
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}
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}
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}
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void RuntimeDyldELF::resolveARMRelocation(const SectionEntry &Section,
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