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[MC][ARM] add .w suffixes for RSB/RSBS T1 

See also:
F5.1.167 RSB, RSBS (register) T1 shift or rotate by value variant
of the Arm ARM.

Link: https://github.com/ClangBuiltLinux/linux/issues/1309

Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D99542
This commit is contained in:
Nick Desaulniers 2021-04-01 10:32:28 -07:00
parent e93c95dea1
commit 52338af569
2 changed files with 21 additions and 2 deletions
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11
llvm/lib/Target/ARM/ARMInstrThumb2.td
View File

@ -5064,8 +5064,8 @@ def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>;
def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>;
// Alias for RSB without the ".w" optional width specifier, and with optional
// implied destination register.
// Alias for RSB with and without the ".w" optional width specifier, with and
// without explicit destination register.
def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm",
(t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
def : t2InstAlias<"rsb${s}${p} $Rdn, $imm",
@ -5075,6 +5075,13 @@ def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm",
def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm",
(t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,
cc_out:$s)>;
def : t2InstAlias<"rsb${s}${p}.w $Rdn, $Rm",
(t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
def : t2InstAlias<"rsb${s}${p}.w $Rd, $Rn, $Rm",
(t2RSBrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
def : t2InstAlias<"rsb${s}${p}.w $Rd, $Rn, $ShiftedRm",
(t2RSBrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p,
cc_out:$s)>;
// SSAT/USAT optional shift operand.
def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",

12
llvm/test/MC/ARM/basic-thumb2-instructions.s
View File

@ -2278,14 +2278,26 @@ adds sp, #-4096
@ RSB (register)
@------------------------------------------------------------------------------
rsb r4, r8
rsb.w r4, r8
rsb r4, r9, r8
rsb.w r4, r9, r8
rsb r1, r4, r8, asr #3
rsb.w r1, r4, r8, asr #3
rsbs r2, r1, r7, lsl #1
rsbs.w r2, r1, r7, lsl #1
rsbs r0, r1, r2
rsbs.w r0, r1, r2
@ CHECK: rsb r4, r4, r8 @ encoding: [0xc4,0xeb,0x08,0x04]
@ CHECK: rsb r4, r4, r8 @ encoding: [0xc4,0xeb,0x08,0x04]
@ CHECK: rsb r4, r9, r8 @ encoding: [0xc9,0xeb,0x08,0x04]
@ CHECK: rsb r4, r9, r8 @ encoding: [0xc9,0xeb,0x08,0x04]
@ CHECK: rsb r1, r4, r8, asr #3 @ encoding: [0xc4,0xeb,0xe8,0x01]
@ CHECK: rsb r1, r4, r8, asr #3 @ encoding: [0xc4,0xeb,0xe8,0x01]
@ CHECK: rsbs r2, r1, r7, lsl #1 @ encoding: [0xd1,0xeb,0x47,0x02]
@ CHECK: rsbs r2, r1, r7, lsl #1 @ encoding: [0xd1,0xeb,0x47,0x02]
@ CHECK: rsbs r0, r1, r2 @ encoding: [0xd1,0xeb,0x02,0x00]
@ CHECK: rsbs r0, r1, r2 @ encoding: [0xd1,0xeb,0x02,0x00]
@------------------------------------------------------------------------------