maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate. 

llvm-svn: 138443
This commit is contained in:
Owen Anderson 2011-08-24 17:21:43 +00:00
parent 45403f31f1
commit 523004145e
2 changed files with 15 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
llvm/lib/Target/ARM/ARMInstrThumb2.td
View File

@ -14,6 +14,7 @@
// IT block predicate field
def it_pred : Operand<i32> {
let PrintMethod = "printMandatoryPredicateOperand";
let DecoderMethod = "DecodeITCond";
}
// IT block condition mask

14
llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -228,6 +228,8 @@ static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
#include "ARMGenDisassemblerTables.inc"
#include "ARMGenInstrInfo.inc"
@ -3289,3 +3291,15 @@ static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
return S;
}
static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Cond,
uint64_t Address, const void *Decoder) {
DecodeStatus S = Success;
if (Cond == 0xF) {
Cond = 0xE;
CHECK(S, Unpredictable);
}
Inst.addOperand(MCOperand::CreateImm(Cond));
return S;
}