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[AArch64] Add support for the SPE-EEF feature 

This is an addition to the existing Statistical Profiling extension, which
introduces an extra system register that is enabled by the new 'spe-eef'
subtarget feature.

Patch written by Simon Tatham.

Reviewed By: ostannard

Differential Revision: https://reviews.llvm.org/D92391
This commit is contained in:
Lucas Prates 2020-11-20 16:07:26 +00:00
parent da21f7ec14
commit 51fe17b047
5 changed files with 16 additions and 0 deletions
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3
llvm/lib/Target/AArch64/AArch64.td
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@ -415,6 +415,9 @@ def FeatureLS64 : SubtargetFeature<"ls64", "HasLS64",
def FeatureBRBE : SubtargetFeature<"brbe", "HasBRBE",
"true", "Enable Branch Record Buffer Extension">;
def FeatureSPE_EEF : SubtargetFeature<"spe-eef", "HasSPE_EEF",
"true", "Enable extra register in the Statistical Profiling Extension">;
def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
"true", "Enable fine grained virtualization traps extension">;

2
llvm/lib/Target/AArch64/AArch64InstrInfo.td
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@ -159,6 +159,8 @@ def HasLS64 : Predicate<"Subtarget->hasLS64()">,
AssemblerPredicate<(all_of FeatureLS64), "ls64">;
def HasBRBE : Predicate<"Subtarget->hasBRBE()">,
AssemblerPredicate<(all_of FeatureBRBE), "brbe">;
def HasSPE_EEF : Predicate<"Subtarget->hasSPE_EEF()">,
AssemblerPredicate<(all_of FeatureSPE_EEF), "spe-eef">;
def IsLE : Predicate<"Subtarget->isLittleEndian()">;
def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
def IsWindows : Predicate<"Subtarget->isTargetWindows()">;

1
llvm/lib/Target/AArch64/AArch64Subtarget.h
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@ -185,6 +185,7 @@ protected:
bool HasETE = false;
bool HasTRBE = false;
bool HasBRBE = false;
bool HasSPE_EEF = false;
// HasZeroCycleRegMove - Has zero-cycle register mov instructions.
bool HasZeroCycleRegMove = false;

4
llvm/lib/Target/AArch64/AArch64SystemOperands.td
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@ -1593,6 +1593,10 @@ foreach n = 0-31 in {
}
}
// Statistical Profiling Extension system register
let Requires = [{ {AArch64::FeatureSPE_EEF} }] in
def : RWSysReg<"PMSNEVFR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b001>;
// Cyclone specific system registers
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::ProcAppleA7} }] in

6
llvm/test/MC/AArch64/spe.s Normal file
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@ -0,0 +1,6 @@
// RUN: llvm-mc -triple aarch64 -mattr +spe-eef -show-encoding %s 2>%t | FileCheck %s
msr PMSNEVFR_EL1, x0
mrs x1, PMSNEVFR_EL1
// CHECK: msr PMSNEVFR_EL1, x0 // encoding: [0x20,0x99,0x18,0xd5]
// CHECK: mrs x1, PMSNEVFR_EL1 // encoding: [0x21,0x99,0x38,0xd5]