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Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elements 

so that it will continue to test what it was meant to test when I commit a
separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon.
Fix a DAG combiner crash exposed by this test change.

llvm-svn: 104380
This commit is contained in:
Bob Wilson 2010-05-21 21:05:32 +00:00
parent da9e3287f9
commit 51d9ee3ff6
2 changed files with 14 additions and 7 deletions
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7
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -6413,6 +6413,13 @@ SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
break;
}
// If the vector element type is not legal, the BUILD_VECTOR operands
// are promoted and implicitly truncated. Make that explicit here.
if (LHSOp.getValueType() != EltType)
LHSOp = DAG.getNode(ISD::TRUNCATE, LHS.getDebugLoc(), EltType, LHSOp);
if (RHSOp.getValueType() != EltType)
RHSOp = DAG.getNode(ISD::TRUNCATE, RHS.getDebugLoc(), EltType, RHSOp);
SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), EltType,
LHSOp, RHSOp);
if (FoldOp.getOpcode() != ISD::UNDEF &&

14
llvm/test/CodeGen/ARM/2009-11-02-NegativeLane.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -mcpu=cortex-a8 < %s | grep vdup.32
; RUN: llc -mcpu=cortex-a8 < %s | grep vdup.16
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "armv7-eabi"
@ -7,12 +7,12 @@ entry:
br i1 undef, label %return, label %bb
bb: ; preds = %bb, %entry
%0 = load float* undef, align 4 ; <float> [#uses=1]
%1 = insertelement <4 x float> undef, float %0, i32 2 ; <<4 x float>> [#uses=1]
%2 = insertelement <4 x float> %1, float undef, i32 3 ; <<4 x float>> [#uses=1]
%3 = fmul <4 x float> undef, %2 ; <<4 x float>> [#uses=1]
%4 = extractelement <4 x float> %3, i32 1 ; <float> [#uses=1]
store float %4, float* undef, align 4
%0 = load i16* undef, align 2
%1 = insertelement <8 x i16> undef, i16 %0, i32 2
%2 = insertelement <8 x i16> %1, i16 undef, i32 3
%3 = mul <8 x i16> %2, %2
%4 = extractelement <8 x i16> %3, i32 2
store i16 %4, i16* undef, align 2
br i1 undef, label %return, label %bb
return: ; preds = %bb, %entry