forked from OSchip/llvm-project
[InstructionSimplify] icmp (X+Y), (X+Z) simplification
This improves simplifications for pattern `icmp (X+Y), (X+Z)` -> `icmp Y,Z`
if only one of the operands has NSW set, e.g.:
icmp slt (x + 0), (x +nsw 1)
We can still safely rewrite this to:
icmp slt 0, 1
because we know that the LHS can't overflow if the RHS has NSW set and
C1 < C2 && C1 >= 0, or C2 < C1 && C1 <= 0
This simplification is useful because ScalarEvolutionExpander which is used to
generate code for SCEVs in different loop optimisers is not always able to put
back NSW flags across control-flow, thus inhibiting CFG simplifications.
Differential Revision: https://reviews.llvm.org/D89317
This commit is contained in:
Sjoerd Meijer
parent
b0c12474ed
commit
51d7df3fa1
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@ -2849,6 +2849,42 @@ static Value *simplifyICmpWithBinOpOnLHS(
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return nullptr;
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}
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// If only one of the icmp's operands has NSW flags, try to prove that:
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//
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// icmp slt (x + C1), (x +nsw C2)
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//
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// is equivalent to:
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//
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// icmp slt C1, C2
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//
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// which is true if x + C2 has the NSW flags set and:
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// *) C1 < C2 && C1 >= 0, or
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// *) C2 < C1 && C1 <= 0.
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//
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static bool trySimplifyICmpWithAdds(CmpInst::Predicate Pred, Value *LHS,
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Value *RHS) {
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// TODO: only support icmp slt for now.
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if (Pred != CmpInst::ICMP_SLT)
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return false;
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// Canonicalize nsw add as RHS.
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if (!match(RHS, m_NSWAdd(m_Value(), m_Value())))
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std::swap(LHS, RHS);
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if (!match(RHS, m_NSWAdd(m_Value(), m_Value())))
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return false;
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Value *X;
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const APInt *C1, *C2;
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if (!match(LHS, m_c_Add(m_Value(X), m_APInt(C1))) ||
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!match(RHS, m_c_Add(m_Specific(X), m_APInt(C2))))
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return false;
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return (C1->slt(*C2) && C1->isNonNegative()) ||
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(C2->slt(*C1) && C1->isNonPositive());
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}
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/// TODO: A large part of this logic is duplicated in InstCombine's
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/// foldICmpBinOp(). We should be able to share that and avoid the code
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/// duplication.
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@ -2898,8 +2934,9 @@ static Value *simplifyICmpWithBinOp(CmpInst::Predicate Pred, Value *LHS,
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return V;
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// icmp (X+Y), (X+Z) -> icmp Y,Z for equalities or if there is no overflow.
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if (A && C && (A == C || A == D || B == C || B == D) && NoLHSWrapProblem &&
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NoRHSWrapProblem) {
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bool CanSimplify = (NoLHSWrapProblem && NoRHSWrapProblem) ||
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trySimplifyICmpWithAdds(Pred, LHS, RHS);
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if (A && C && (A == C || A == D || B == C || B == D) && CanSimplify) {
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// Determine Y and Z in the form icmp (X+Y), (X+Z).
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Value *Y, *Z;
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if (A == C) {
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@ -1769,12 +1769,7 @@ define i1 @cmp_through_addrspacecast(i32 addrspace(1)* %p1) {
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define i1 @icmp_nsw_1(i32 %V) {
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; CHECK-LABEL: @icmp_nsw_1(
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; CHECK-NEXT: [[ADD5:%.*]] = add i32 [[V:%.*]], 5
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; CHECK-NEXT: [[ADD6:%.*]] = add nsw i32 [[V]], 6
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; CHECK-NEXT: [[S1:%.*]] = sext i32 [[ADD5]] to i64
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; CHECK-NEXT: [[S2:%.*]] = sext i32 [[ADD6]] to i64
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i64 [[S1]], [[S2]]
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; CHECK-NEXT: ret i1 [[CMP]]
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; CHECK-NEXT: ret i1 true
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;
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%add5 = add i32 %V, 5
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%add6 = add nsw i32 %V, 6
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@ -1786,10 +1781,7 @@ define i1 @icmp_nsw_1(i32 %V) {
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define i1 @icmp_nsw_2(i32 %V) {
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; CHECK-LABEL: @icmp_nsw_2(
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; CHECK-NEXT: [[ADD5:%.*]] = add i32 [[V:%.*]], 5
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; CHECK-NEXT: [[ADD6:%.*]] = add nsw i32 [[V]], 6
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[ADD5]], [[ADD6]]
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; CHECK-NEXT: ret i1 [[CMP]]
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; CHECK-NEXT: ret i1 true
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;
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%add5 = add i32 %V, 5
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%add6 = add nsw i32 %V, 6
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@ -1799,10 +1791,7 @@ define i1 @icmp_nsw_2(i32 %V) {
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define i1 @icmp_nsw_commute(i32 %V) {
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; CHECK-LABEL: @icmp_nsw_commute(
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; CHECK-NEXT: [[ADD5:%.*]] = add i32 5, [[V:%.*]]
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; CHECK-NEXT: [[ADD6:%.*]] = add nsw i32 [[V]], 6
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[ADD5]], [[ADD6]]
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; CHECK-NEXT: ret i1 [[CMP]]
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; CHECK-NEXT: ret i1 true
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;
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%add5 = add i32 5, %V
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%add6 = add nsw i32 %V, 6
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@ -1812,10 +1801,7 @@ define i1 @icmp_nsw_commute(i32 %V) {
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define i1 @icmp_nsw_commute2(i32 %V) {
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; CHECK-LABEL: @icmp_nsw_commute2(
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; CHECK-NEXT: [[ADD5:%.*]] = add i32 [[V:%.*]], 5
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; CHECK-NEXT: [[ADD6:%.*]] = add nsw i32 6, [[V]]
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[ADD5]], [[ADD6]]
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; CHECK-NEXT: ret i1 [[CMP]]
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; CHECK-NEXT: ret i1 true
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;
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%add5 = add i32 %V, 5
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%add6 = add nsw i32 6, %V
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@ -1825,10 +1811,7 @@ define i1 @icmp_nsw_commute2(i32 %V) {
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define i1 @icmp_nsw_commute3(i32 %V) {
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; CHECK-LABEL: @icmp_nsw_commute3(
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; CHECK-NEXT: [[ADD5:%.*]] = add i32 5, [[V:%.*]]
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; CHECK-NEXT: [[ADD6:%.*]] = add nsw i32 6, [[V]]
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[ADD5]], [[ADD6]]
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; CHECK-NEXT: ret i1 [[CMP]]
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; CHECK-NEXT: ret i1 true
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;
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%add5 = add i32 5, %V
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%add6 = add nsw i32 6, %V
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@ -1861,10 +1844,7 @@ define i1 @icmp_nsw_23(i32 %V) {
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define i1 @icmp_nsw_false(i32 %V) {
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; CHECK-LABEL: @icmp_nsw_false(
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; CHECK-NEXT: [[ADD5:%.*]] = add nsw i32 [[V:%.*]], 6
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; CHECK-NEXT: [[ADD6:%.*]] = add i32 [[V]], 5
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[ADD5]], [[ADD6]]
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; CHECK-NEXT: ret i1 [[CMP]]
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; CHECK-NEXT: ret i1 false
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;
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%add5 = add nsw i32 %V, 6
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%add6 = add i32 %V, 5
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@ -1908,12 +1888,22 @@ define i1 @icmp_nsw_false_4(i32 %V) {
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ret i1 %cmp
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}
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define i1 @icmp_nsw_false_5(i8 %V) {
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; CHECK-LABEL: @icmp_nsw_false_5(
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; CHECK-NEXT: [[ADD:%.*]] = add i8 [[V:%.*]], 121
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; CHECK-NEXT: [[ADDNSW:%.*]] = add nsw i8 [[V]], -104
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[ADD]], [[ADDNSW]]
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%add = add i8 %V, 121
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%addnsw = add nsw i8 %V, -104
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%cmp = icmp slt i8 %add, %addnsw
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ret i1 %cmp
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}
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define i1 @icmp_nsw_i8(i8 %V) {
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; CHECK-LABEL: @icmp_nsw_i8(
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; CHECK-NEXT: [[ADD5:%.*]] = add i8 [[V:%.*]], 5
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; CHECK-NEXT: [[ADD6:%.*]] = add nsw i8 [[V]], 6
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[ADD5]], [[ADD6]]
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; CHECK-NEXT: ret i1 [[CMP]]
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; CHECK-NEXT: ret i1 true
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;
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%add5 = add i8 %V, 5
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%add6 = add nsw i8 %V, 6
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@ -1923,23 +1913,17 @@ define i1 @icmp_nsw_i8(i8 %V) {
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define i1 @icmp_nsw_i16(i16 %V) {
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; CHECK-LABEL: @icmp_nsw_i16(
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; CHECK-NEXT: [[ADD5:%.*]] = add i16 [[V:%.*]], 5
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; CHECK-NEXT: [[ADD6:%.*]] = add nsw i16 [[V]], 6
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i16 [[ADD5]], [[ADD6]]
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; CHECK-NEXT: ret i1 [[CMP]]
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; CHECK-NEXT: ret i1 true
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;
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%add5 = add i16 %V, 5
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%add6 = add nsw i16 %V, 6
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%add5 = add i16 %V, 0
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%add6 = add nsw i16 %V, 1
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%cmp = icmp slt i16 %add5, %add6
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ret i1 %cmp
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}
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define i1 @icmp_nsw_i64(i64 %V) {
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; CHECK-LABEL: @icmp_nsw_i64(
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; CHECK-NEXT: [[ADD5:%.*]] = add i64 [[V:%.*]], 5
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; CHECK-NEXT: [[ADD6:%.*]] = add nsw i64 [[V]], 6
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i64 [[ADD5]], [[ADD6]]
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; CHECK-NEXT: ret i1 [[CMP]]
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; CHECK-NEXT: ret i1 true
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;
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%add5 = add i64 %V, 5
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%add6 = add nsw i64 %V, 6
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@ -1949,10 +1933,7 @@ define i1 @icmp_nsw_i64(i64 %V) {
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define <4 x i1> @icmp_nsw_vec(<4 x i32> %V) {
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; CHECK-LABEL: @icmp_nsw_vec(
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; CHECK-NEXT: [[ADD5:%.*]] = add <4 x i32> [[V:%.*]], <i32 5, i32 5, i32 5, i32 5>
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; CHECK-NEXT: [[ADD6:%.*]] = add nsw <4 x i32> [[V]], <i32 6, i32 6, i32 6, i32 6>
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt <4 x i32> [[ADD5]], [[ADD6]]
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; CHECK-NEXT: ret <4 x i1> [[CMP]]
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; CHECK-NEXT: ret <4 x i1> <i1 true, i1 true, i1 true, i1 true>
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;
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%add5 = add <4 x i32> %V, <i32 5, i32 5, i32 5, i32 5>
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%add6 = add nsw <4 x i32> %V, <i32 6, i32 6, i32 6, i32 6>
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@ -2064,4 +2045,26 @@ define i1 @icmp_nsw_11(i32 %V) {
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ret i1 %cmp
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}
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define i1 @icmp_nsw_nonpos(i32 %V) {
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; CHECK-LABEL: @icmp_nsw_nonpos(
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; CHECK-NEXT: ret i1 false
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;
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%add5 = add i32 %V, 0
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%add6 = add nsw i32 %V, -1
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%cmp = icmp slt i32 %add5, %add6
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ret i1 %cmp
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}
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define i1 @icmp_nsw_nonpos2(i32 %V) {
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; CHECK-LABEL: @icmp_nsw_nonpos2(
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; CHECK-NEXT: [[ADD5:%.*]] = add i32 [[V:%.*]], 1
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[ADD5]], [[V]]
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%add5 = add i32 %V, 1
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%add6 = add nsw i32 %V, 0
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%cmp = icmp slt i32 %add5, %add6
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ret i1 %cmp
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}
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attributes #0 = { null_pointer_is_valid }
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