maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

Add instruction encodings for PEEK and ENDIN. 

Previously these were marked with the wrong format.

llvm-svn: 170334
This commit is contained in:
Richard Osborne 2012-12-17 14:23:54 +00:00
parent cacda256a1
commit 51bf1b269a
2 changed files with 14 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
llvm/lib/Target/XCore/XCoreInstrInfo.td
View File

@ -891,6 +891,14 @@ def INITDP_2r : _F2R<0b000010, (outs), (ins GRRegs:$src, GRRegs:$t),
"init t[$t]:dp, $src", "init t[$t]:dp, $src",
[(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>; [(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>;
def PEEK_2r : _F2R<0b101110, (outs GRRegs:$dst), (ins GRRegs:$src),
"peek $dst, res[$src]",
[(set GRRegs:$dst, (int_xcore_peek GRRegs:$src))]>;
def ENDIN_2r : _F2R<0b100101, (outs GRRegs:$dst), (ins GRRegs:$src),
"endin $dst, res[$src]",
[(set GRRegs:$dst, (int_xcore_endin GRRegs:$src))]>;
// Two operand long // Two operand long
// getd, testlcl // getd, testlcl
def BITREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), def BITREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
@ -933,14 +941,6 @@ def SETRDY_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2),
"setrdy res[$src1], $src2", "setrdy res[$src1], $src2",
[(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>; [(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>;
def PEEK_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
"peek $dst, res[$src]",
[(set GRRegs:$dst, (int_xcore_peek GRRegs:$src))]>;
def ENDIN_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
"endin $dst, res[$src]",
[(set GRRegs:$dst, (int_xcore_endin GRRegs:$src))]>;
// One operand short // One operand short
// TODO edu, eeu, waitet, waitef, tstart, clrtp // TODO edu, eeu, waitet, waitef, tstart, clrtp
// setdp, setcp, setev, kcall // setdp, setcp, setev, kcall

6
llvm/test/MC/Disassembler/XCore/xcore.txt
View File

@ -158,3 +158,9 @@
# CHECK: zext r2, 32 # CHECK: zext r2, 32
0xd8 0x46 0xd8 0x46
# CHECK: peek r0, res[r5]
0x81 0xbf
# CHECK: endin r10, res[r1]
0x59 0x97