forked from OSchip/llvm-project
R600/SI: add gather4 and getlod intrinsics (v3)
This contains all the previous patches + getlod support on top of it. It doesn't use SDNodes anymore, so it's quite small. It also adds v16i8 to SReg_128, which is used for the sampler descriptor. Reviewed-by: Tom Stellard llvm-svn: 211228
This commit is contained in:
Marek Olsak
parent
11415c6120
commit
51b8e7b2e7
|
|
@ -712,6 +712,53 @@ multiclass MIMG_Sampler <bits<7> op, string asm> {
|
|||
defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4>;
|
||||
}
|
||||
|
||||
class MIMG_Gather_Helper <bits<7> op, string asm,
|
||||
RegisterClass dst_rc,
|
||||
RegisterClass src_rc> : MIMG <
|
||||
op,
|
||||
(outs dst_rc:$vdata),
|
||||
(ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
|
||||
i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
|
||||
SReg_256:$srsrc, SReg_128:$ssamp),
|
||||
asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
|
||||
#" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
|
||||
[]> {
|
||||
let mayLoad = 1;
|
||||
let mayStore = 0;
|
||||
|
||||
// DMASK was repurposed for GATHER4. 4 components are always
|
||||
// returned and DMASK works like a swizzle - it selects
|
||||
// the component to fetch. The only useful DMASK values are
|
||||
// 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
|
||||
// (red,red,red,red) etc.) The ISA document doesn't mention
|
||||
// this.
|
||||
// Therefore, disable all code which updates DMASK by setting these two:
|
||||
let MIMG = 0;
|
||||
let hasPostISelHook = 0;
|
||||
}
|
||||
|
||||
multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
|
||||
RegisterClass dst_rc,
|
||||
int channels> {
|
||||
def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_32>,
|
||||
MIMG_Mask<asm#"_V1", channels>;
|
||||
def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64>,
|
||||
MIMG_Mask<asm#"_V2", channels>;
|
||||
def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128>,
|
||||
MIMG_Mask<asm#"_V4", channels>;
|
||||
def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256>,
|
||||
MIMG_Mask<asm#"_V8", channels>;
|
||||
def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512>,
|
||||
MIMG_Mask<asm#"_V16", channels>;
|
||||
}
|
||||
|
||||
multiclass MIMG_Gather <bits<7> op, string asm> {
|
||||
defm _V1 : MIMG_Gather_Src_Helper<op, asm, VReg_32, 1>;
|
||||
defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2>;
|
||||
defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3>;
|
||||
defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Vector instruction mappings
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
|
|||
|
|
@ -987,31 +987,31 @@ defm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "IMAGE_SAMPLE_C_B">;
|
|||
//def IMAGE_SAMPLE_C_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_O", 0x0000003d>;
|
||||
//def IMAGE_SAMPLE_C_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL_O", 0x0000003e>;
|
||||
//def IMAGE_SAMPLE_C_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ_O", 0x0000003f>;
|
||||
//def IMAGE_GATHER4 : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4", 0x00000040>;
|
||||
//def IMAGE_GATHER4_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL", 0x00000041>;
|
||||
//def IMAGE_GATHER4_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L", 0x00000044>;
|
||||
//def IMAGE_GATHER4_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B", 0x00000045>;
|
||||
//def IMAGE_GATHER4_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL", 0x00000046>;
|
||||
//def IMAGE_GATHER4_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ", 0x00000047>;
|
||||
//def IMAGE_GATHER4_C : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C", 0x00000048>;
|
||||
//def IMAGE_GATHER4_C_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL", 0x00000049>;
|
||||
//def IMAGE_GATHER4_C_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L", 0x0000004c>;
|
||||
//def IMAGE_GATHER4_C_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B", 0x0000004d>;
|
||||
//def IMAGE_GATHER4_C_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL", 0x0000004e>;
|
||||
//def IMAGE_GATHER4_C_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ", 0x0000004f>;
|
||||
//def IMAGE_GATHER4_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_O", 0x00000050>;
|
||||
//def IMAGE_GATHER4_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL_O", 0x00000051>;
|
||||
//def IMAGE_GATHER4_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L_O", 0x00000054>;
|
||||
//def IMAGE_GATHER4_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_O", 0x00000055>;
|
||||
//def IMAGE_GATHER4_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL_O", 0x00000056>;
|
||||
//def IMAGE_GATHER4_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ_O", 0x00000057>;
|
||||
//def IMAGE_GATHER4_C_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_O", 0x00000058>;
|
||||
//def IMAGE_GATHER4_C_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL_O", 0x00000059>;
|
||||
//def IMAGE_GATHER4_C_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L_O", 0x0000005c>;
|
||||
//def IMAGE_GATHER4_C_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_O", 0x0000005d>;
|
||||
//def IMAGE_GATHER4_C_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL_O", 0x0000005e>;
|
||||
//def IMAGE_GATHER4_C_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ_O", 0x0000005f>;
|
||||
//def IMAGE_GET_LOD : MIMG_NoPattern_ <"IMAGE_GET_LOD", 0x00000060>;
|
||||
defm IMAGE_GATHER4 : MIMG_Gather <0x00000040, "IMAGE_GATHER4">;
|
||||
defm IMAGE_GATHER4_CL : MIMG_Gather <0x00000041, "IMAGE_GATHER4_CL">;
|
||||
defm IMAGE_GATHER4_L : MIMG_Gather <0x00000044, "IMAGE_GATHER4_L">;
|
||||
defm IMAGE_GATHER4_B : MIMG_Gather <0x00000045, "IMAGE_GATHER4_B">;
|
||||
defm IMAGE_GATHER4_B_CL : MIMG_Gather <0x00000046, "IMAGE_GATHER4_B_CL">;
|
||||
defm IMAGE_GATHER4_LZ : MIMG_Gather <0x00000047, "IMAGE_GATHER4_LZ">;
|
||||
defm IMAGE_GATHER4_C : MIMG_Gather <0x00000048, "IMAGE_GATHER4_C">;
|
||||
defm IMAGE_GATHER4_C_CL : MIMG_Gather <0x00000049, "IMAGE_GATHER4_C_CL">;
|
||||
defm IMAGE_GATHER4_C_L : MIMG_Gather <0x0000004c, "IMAGE_GATHER4_C_L">;
|
||||
defm IMAGE_GATHER4_C_B : MIMG_Gather <0x0000004d, "IMAGE_GATHER4_C_B">;
|
||||
defm IMAGE_GATHER4_C_B_CL : MIMG_Gather <0x0000004e, "IMAGE_GATHER4_C_B_CL">;
|
||||
defm IMAGE_GATHER4_C_LZ : MIMG_Gather <0x0000004f, "IMAGE_GATHER4_C_LZ">;
|
||||
defm IMAGE_GATHER4_O : MIMG_Gather <0x00000050, "IMAGE_GATHER4_O">;
|
||||
defm IMAGE_GATHER4_CL_O : MIMG_Gather <0x00000051, "IMAGE_GATHER4_CL_O">;
|
||||
defm IMAGE_GATHER4_L_O : MIMG_Gather <0x00000054, "IMAGE_GATHER4_L_O">;
|
||||
defm IMAGE_GATHER4_B_O : MIMG_Gather <0x00000055, "IMAGE_GATHER4_B_O">;
|
||||
defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <0x00000056, "IMAGE_GATHER4_B_CL_O">;
|
||||
defm IMAGE_GATHER4_LZ_O : MIMG_Gather <0x00000057, "IMAGE_GATHER4_LZ_O">;
|
||||
defm IMAGE_GATHER4_C_O : MIMG_Gather <0x00000058, "IMAGE_GATHER4_C_O">;
|
||||
defm IMAGE_GATHER4_C_CL_O : MIMG_Gather <0x00000059, "IMAGE_GATHER4_C_CL_O">;
|
||||
defm IMAGE_GATHER4_C_L_O : MIMG_Gather <0x0000005c, "IMAGE_GATHER4_C_L_O">;
|
||||
defm IMAGE_GATHER4_C_B_O : MIMG_Gather <0x0000005d, "IMAGE_GATHER4_C_B_O">;
|
||||
defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather <0x0000005e, "IMAGE_GATHER4_C_B_CL_O">;
|
||||
defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <0x0000005f, "IMAGE_GATHER4_C_LZ_O">;
|
||||
defm IMAGE_GET_LOD : MIMG_Sampler <0x00000060, "IMAGE_GET_LOD">;
|
||||
//def IMAGE_SAMPLE_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD", 0x00000068>;
|
||||
//def IMAGE_SAMPLE_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL", 0x00000069>;
|
||||
//def IMAGE_SAMPLE_C_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD", 0x0000006a>;
|
||||
|
|
@ -1773,6 +1773,58 @@ def : SextInReg <i16, 16>;
|
|||
/********** Image sampling patterns **********/
|
||||
/********** ======================= **********/
|
||||
|
||||
class SampleRawPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
|
||||
(name vt:$addr, v32i8:$rsrc, v16i8:$sampler, i32:$dmask, i32:$unorm,
|
||||
i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe),
|
||||
(opcode (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $da),
|
||||
(as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $slc),
|
||||
$addr, $rsrc, $sampler)
|
||||
>;
|
||||
|
||||
// Only the variants which make sense are defined.
|
||||
def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V2, v2i32>;
|
||||
def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V4, v4i32>;
|
||||
def : SampleRawPattern<int_SI_gather4_cl, IMAGE_GATHER4_CL_V4_V4, v4i32>;
|
||||
def : SampleRawPattern<int_SI_gather4_l, IMAGE_GATHER4_L_V4_V4, v4i32>;
|
||||
def : SampleRawPattern<int_SI_gather4_b, IMAGE_GATHER4_B_V4_V4, v4i32>;
|
||||
def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V4, v4i32>;
|
||||
def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V8, v8i32>;
|
||||
def : SampleRawPattern<int_SI_gather4_lz, IMAGE_GATHER4_LZ_V4_V2, v2i32>;
|
||||
def : SampleRawPattern<int_SI_gather4_lz, IMAGE_GATHER4_LZ_V4_V4, v4i32>;
|
||||
|
||||
def : SampleRawPattern<int_SI_gather4_c, IMAGE_GATHER4_C_V4_V4, v4i32>;
|
||||
def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V4, v4i32>;
|
||||
def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V8, v8i32>;
|
||||
def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V4, v4i32>;
|
||||
def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V8, v8i32>;
|
||||
def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V4, v4i32>;
|
||||
def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V8, v8i32>;
|
||||
def : SampleRawPattern<int_SI_gather4_c_b_cl, IMAGE_GATHER4_C_B_CL_V4_V8, v8i32>;
|
||||
def : SampleRawPattern<int_SI_gather4_c_lz, IMAGE_GATHER4_C_LZ_V4_V4, v4i32>;
|
||||
|
||||
def : SampleRawPattern<int_SI_gather4_o, IMAGE_GATHER4_O_V4_V4, v4i32>;
|
||||
def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V4, v4i32>;
|
||||
def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V8, v8i32>;
|
||||
def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V4, v4i32>;
|
||||
def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V8, v8i32>;
|
||||
def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V4, v4i32>;
|
||||
def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V8, v8i32>;
|
||||
def : SampleRawPattern<int_SI_gather4_b_cl_o, IMAGE_GATHER4_B_CL_O_V4_V8, v8i32>;
|
||||
def : SampleRawPattern<int_SI_gather4_lz_o, IMAGE_GATHER4_LZ_O_V4_V4, v4i32>;
|
||||
|
||||
def : SampleRawPattern<int_SI_gather4_c_o, IMAGE_GATHER4_C_O_V4_V4, v4i32>;
|
||||
def : SampleRawPattern<int_SI_gather4_c_o, IMAGE_GATHER4_C_O_V4_V8, v8i32>;
|
||||
def : SampleRawPattern<int_SI_gather4_c_cl_o, IMAGE_GATHER4_C_CL_O_V4_V8, v8i32>;
|
||||
def : SampleRawPattern<int_SI_gather4_c_l_o, IMAGE_GATHER4_C_L_O_V4_V8, v8i32>;
|
||||
def : SampleRawPattern<int_SI_gather4_c_b_o, IMAGE_GATHER4_C_B_O_V4_V8, v8i32>;
|
||||
def : SampleRawPattern<int_SI_gather4_c_b_cl_o, IMAGE_GATHER4_C_B_CL_O_V4_V8, v8i32>;
|
||||
def : SampleRawPattern<int_SI_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V4, v4i32>;
|
||||
def : SampleRawPattern<int_SI_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V8, v8i32>;
|
||||
|
||||
def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V1, i32>;
|
||||
def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V2, v2i32>;
|
||||
def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V4, v4i32>;
|
||||
|
||||
/* SIsample for simple 1D texture lookup */
|
||||
def : Pat <
|
||||
(SIsample i32:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
|
||||
|
|
|
|||
|
|
@ -56,11 +56,61 @@ let TargetPrefix = "SI", isTarget = 1 in {
|
|||
|
||||
class Sample : Intrinsic <[llvm_v4f32_ty], [llvm_anyvector_ty, llvm_v32i8_ty, llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
|
||||
|
||||
// Fully-flexible SAMPLE instruction.
|
||||
class SampleRaw : Intrinsic <
|
||||
[llvm_v4f32_ty], // vdata(VGPR)
|
||||
[llvm_anyint_ty, // vaddr(VGPR)
|
||||
llvm_v32i8_ty, // rsrc(SGPR)
|
||||
llvm_v16i8_ty, // sampler(SGPR)
|
||||
llvm_i32_ty, // dmask(imm)
|
||||
llvm_i32_ty, // unorm(imm)
|
||||
llvm_i32_ty, // r128(imm)
|
||||
llvm_i32_ty, // da(imm)
|
||||
llvm_i32_ty, // glc(imm)
|
||||
llvm_i32_ty, // slc(imm)
|
||||
llvm_i32_ty, // tfe(imm)
|
||||
llvm_i32_ty], // lwe(imm)
|
||||
[IntrNoMem]>;
|
||||
|
||||
def int_SI_sample : Sample;
|
||||
def int_SI_sampleb : Sample;
|
||||
def int_SI_sampled : Sample;
|
||||
def int_SI_samplel : Sample;
|
||||
|
||||
// Basic gather4
|
||||
def int_SI_gather4 : SampleRaw;
|
||||
def int_SI_gather4_cl : SampleRaw;
|
||||
def int_SI_gather4_l : SampleRaw;
|
||||
def int_SI_gather4_b : SampleRaw;
|
||||
def int_SI_gather4_b_cl : SampleRaw;
|
||||
def int_SI_gather4_lz : SampleRaw;
|
||||
|
||||
// Gather4 with comparison
|
||||
def int_SI_gather4_c : SampleRaw;
|
||||
def int_SI_gather4_c_cl : SampleRaw;
|
||||
def int_SI_gather4_c_l : SampleRaw;
|
||||
def int_SI_gather4_c_b : SampleRaw;
|
||||
def int_SI_gather4_c_b_cl : SampleRaw;
|
||||
def int_SI_gather4_c_lz : SampleRaw;
|
||||
|
||||
// Gather4 with offsets
|
||||
def int_SI_gather4_o : SampleRaw;
|
||||
def int_SI_gather4_cl_o : SampleRaw;
|
||||
def int_SI_gather4_l_o : SampleRaw;
|
||||
def int_SI_gather4_b_o : SampleRaw;
|
||||
def int_SI_gather4_b_cl_o : SampleRaw;
|
||||
def int_SI_gather4_lz_o : SampleRaw;
|
||||
|
||||
// Gather4 with comparison and offsets
|
||||
def int_SI_gather4_c_o : SampleRaw;
|
||||
def int_SI_gather4_c_cl_o : SampleRaw;
|
||||
def int_SI_gather4_c_l_o : SampleRaw;
|
||||
def int_SI_gather4_c_b_o : SampleRaw;
|
||||
def int_SI_gather4_c_b_cl_o : SampleRaw;
|
||||
def int_SI_gather4_c_lz_o : SampleRaw;
|
||||
|
||||
def int_SI_getlod : SampleRaw;
|
||||
|
||||
def int_SI_imageload : Intrinsic <[llvm_v4i32_ty], [llvm_anyvector_ty, llvm_v32i8_ty, llvm_i32_ty], [IntrNoMem]>;
|
||||
|
||||
def int_SI_resinfo : Intrinsic <[llvm_v4i32_ty], [llvm_i32_ty, llvm_v32i8_ty, llvm_i32_ty], [IntrNoMem]>;
|
||||
|
|
|
|||
|
|
@ -168,7 +168,7 @@ def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, i1], 64,
|
|||
(add SGPR_64Regs, VCCReg, EXECReg)
|
||||
>;
|
||||
|
||||
def SReg_128 : RegisterClass<"AMDGPU", [v4i32], 128, (add SGPR_128)>;
|
||||
def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v16i8], 128, (add SGPR_128)>;
|
||||
|
||||
def SReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add SGPR_256)>;
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,508 @@
|
|||
;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
|
||||
|
||||
;CHECK-LABEL: @gather4_v2
|
||||
;CHECK: IMAGE_GATHER4 {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_v2() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.v2i32(<2 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4
|
||||
;CHECK: IMAGE_GATHER4 {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4_cl
|
||||
;CHECK: IMAGE_GATHER4_CL {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_cl() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.cl.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4_l
|
||||
;CHECK: IMAGE_GATHER4_L {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_l() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.l.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4_b
|
||||
;CHECK: IMAGE_GATHER4_B {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_b() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.b.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4_b_cl
|
||||
;CHECK: IMAGE_GATHER4_B_CL {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_b_cl() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.b.cl.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4_b_cl_v8
|
||||
;CHECK: IMAGE_GATHER4_B_CL {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_b_cl_v8() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.b.cl.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4_lz_v2
|
||||
;CHECK: IMAGE_GATHER4_LZ {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_lz_v2() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.lz.v2i32(<2 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4_lz
|
||||
;CHECK: IMAGE_GATHER4_LZ {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_lz() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.lz.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
|
||||
;CHECK-LABEL: @gather4_o
|
||||
;CHECK: IMAGE_GATHER4_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4_cl_o
|
||||
;CHECK: IMAGE_GATHER4_CL_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_cl_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.cl.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4_cl_o_v8
|
||||
;CHECK: IMAGE_GATHER4_CL_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_cl_o_v8() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.cl.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4_l_o
|
||||
;CHECK: IMAGE_GATHER4_L_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_l_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.l.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4_l_o_v8
|
||||
;CHECK: IMAGE_GATHER4_L_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_l_o_v8() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.l.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4_b_o
|
||||
;CHECK: IMAGE_GATHER4_B_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_b_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.b.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4_b_o_v8
|
||||
;CHECK: IMAGE_GATHER4_B_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_b_o_v8() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.b.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4_b_cl_o
|
||||
;CHECK: IMAGE_GATHER4_B_CL_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_b_cl_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.b.cl.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4_lz_o
|
||||
;CHECK: IMAGE_GATHER4_LZ_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_lz_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.lz.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
|
||||
;CHECK-LABEL: @gather4_c
|
||||
;CHECK: IMAGE_GATHER4_C {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4_c_cl
|
||||
;CHECK: IMAGE_GATHER4_C_CL {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_cl() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.cl.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4_c_cl_v8
|
||||
;CHECK: IMAGE_GATHER4_C_CL {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_cl_v8() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.cl.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4_c_l
|
||||
;CHECK: IMAGE_GATHER4_C_L {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_l() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.l.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4_c_l_v8
|
||||
;CHECK: IMAGE_GATHER4_C_L {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_l_v8() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.l.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4_c_b
|
||||
;CHECK: IMAGE_GATHER4_C_B {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_b() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.b.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4_c_b_v8
|
||||
;CHECK: IMAGE_GATHER4_C_B {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_b_v8() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.b.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4_c_b_cl
|
||||
;CHECK: IMAGE_GATHER4_C_B_CL {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_b_cl() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.b.cl.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4_c_lz
|
||||
;CHECK: IMAGE_GATHER4_C_LZ {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_lz() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.lz.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
|
||||
;CHECK-LABEL: @gather4_c_o
|
||||
;CHECK: IMAGE_GATHER4_C_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4_c_o_v8
|
||||
;CHECK: IMAGE_GATHER4_C_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_o_v8() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4_c_cl_o
|
||||
;CHECK: IMAGE_GATHER4_C_CL_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_cl_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.cl.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4_c_l_o
|
||||
;CHECK: IMAGE_GATHER4_C_L_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_l_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.l.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4_c_b_o
|
||||
;CHECK: IMAGE_GATHER4_C_B_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_b_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.b.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4_c_b_cl_o
|
||||
;CHECK: IMAGE_GATHER4_C_B_CL_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_b_cl_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.b.cl.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4_c_lz_o
|
||||
;CHECK: IMAGE_GATHER4_C_LZ_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_lz_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.lz.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @gather4_c_lz_o_v8
|
||||
;CHECK: IMAGE_GATHER4_C_LZ_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @gather4_c_lz_o_v8() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.lz.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
%r2 = extractelement <4 x float> %r, i32 2
|
||||
%r3 = extractelement <4 x float> %r, i32 3
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
|
||||
declare <4 x float> @llvm.SI.gather4.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.cl.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.l.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.b.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.b.cl.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.b.cl.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.lz.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.lz.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
|
||||
declare <4 x float> @llvm.SI.gather4.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.cl.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.cl.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.l.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.l.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.b.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.b.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.b.cl.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.lz.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
|
||||
declare <4 x float> @llvm.SI.gather4.c.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.cl.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.cl.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.l.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.l.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.b.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.b.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.b.cl.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.lz.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
|
||||
declare <4 x float> @llvm.SI.gather4.c.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.cl.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.l.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.b.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.b.cl.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.lz.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.gather4.c.lz.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
|
||||
declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
|
||||
|
||||
attributes #0 = { "ShaderType"="0" }
|
||||
attributes #1 = { nounwind readnone }
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
|
||||
|
||||
;CHECK-LABEL: @getlod
|
||||
;CHECK: IMAGE_GET_LOD {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, -1, 0, 0, 0, 0, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @getlod() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.getlod.i32(i32 undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r0, float %r1)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @getlod_v2
|
||||
;CHECK: IMAGE_GET_LOD {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @getlod_v2() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.getlod.v2i32(<2 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r0, float %r1)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @getlod_v4
|
||||
;CHECK: IMAGE_GET_LOD {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
define void @getlod_v4() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.getlod.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
%r0 = extractelement <4 x float> %r, i32 0
|
||||
%r1 = extractelement <4 x float> %r, i32 1
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r0, float %r1)
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
declare <4 x float> @llvm.SI.getlod.i32(i32, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.getlod.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
declare <4 x float> @llvm.SI.getlod.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
|
||||
|
||||
declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
|
||||
|
||||
attributes #0 = { "ShaderType"="0" }
|
||||
attributes #1 = { nounwind readnone }
|
||||
Loading…
Reference in New Issue