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[M68k] Introduce DReg bead 

This is required in order to determine during disassembly whether a
Reg bead without associated DA bead is referring to a data register.

Differential Revision: https://reviews.llvm.org/D98534
This commit is contained in:
Ricky Taylor 2021-03-11 20:35:04 +00:00
parent 5a5a531214
commit 51884c6bef
6 changed files with 40 additions and 36 deletions
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34
llvm/lib/Target/M68k/M68kInstrArithmetic.td
View File

@ -38,7 +38,7 @@
/// | | | EFFECTIVE ADDRESS
/// x x x x | REG | OP MODE | MODE | REG
/// ----------------------------------------------------
class MxArithEncoding<MxBead4Bits CMD, MxEncOpMode OPMODE, MxBeadReg REG,
class MxArithEncoding<MxBead4Bits CMD, MxEncOpMode OPMODE, MxBead REG,
MxEncEA EA, MxEncExt EXT>
: MxEncoding<EA.Reg, EA.DA, EA.Mode, OPMODE.B0, OPMODE.B1, OPMODE.B2, REG,
CMD,EXT.Imm, EXT.B8, EXT.Scale, EXT.WL, EXT.DAReg>;
@ -53,7 +53,7 @@ class MxArithEncoding<MxBead4Bits CMD, MxEncOpMode OPMODE, MxBeadReg REG,
/// Ry - source
/// M - address mode switch
class MxArithXEncoding<MxBead4Bits CMD, MxEncSize SIZE, MxBead1Bit MODE,
MxBeadReg SRC, MxBeadReg DST>
MxBeadDReg SRC, MxBeadDReg DST>
: MxEncoding<SRC, MODE, MxBead2Bits<0b00>, SIZE, MxBead1Bit<0b1>, DST, CMD>;
/// Encoding for Immediate forms
@ -88,13 +88,13 @@ let Defs = [CCR] in {
let Constraints = "$src = $dst" in {
// $reg, $ccr <- $reg op $reg
class MxBiArOp_RFRR_xEA<string MN, SDNode NODE, MxType TYPE, bits<4> CMD>
class MxBiArOp_RFRR_xEA<string MN, SDNode NODE, MxType TYPE, bits<4> CMD, MxBead REG>
: MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, TYPE.ROp:$opd),
MN#"."#TYPE.Prefix#"\t$opd, $dst",
[(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.VT:$opd))],
MxArithEncoding<MxBead4Bits<CMD>,
!cast<MxEncOpMode>("MxOpMode"#TYPE.Size#TYPE.RLet#"EA"),
MxBeadReg<0>,
REG,
!cast<MxEncEA>("MxEncEA"#TYPE.RLet#"_2"),
MxExtEmpty>>;
@ -110,7 +110,7 @@ class MxBiArOp_RFRR_EAd<string MN, SDNode NODE, MxType TYPE, bits<4> CMD>
[(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.VT:$opd))],
MxArithEncoding<MxBead4Bits<CMD>,
!cast<MxEncOpMode>("MxOpMode"#TYPE.Size#"EAd"),
MxBeadReg<2>, MxEncEAd_0, MxExtEmpty>>;
MxBeadDReg<2>, MxEncEAd_0, MxExtEmpty>>;
// $reg <- $reg op $imm
class MxBiArOp_RFRI_xEA<string MN, SDNode NODE, MxType TYPE, bits<4> CMD>
@ -119,7 +119,7 @@ class MxBiArOp_RFRI_xEA<string MN, SDNode NODE, MxType TYPE, bits<4> CMD>
[(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.IPat:$opd))],
MxArithEncoding<MxBead4Bits<CMD>,
!cast<MxEncOpMode>("MxOpMode"#TYPE.Size#TYPE.RLet#"EA"),
MxBeadReg<0>, MxEncEAi,
MxBeadDReg<0>, MxEncEAi,
!cast<MxEncExt>("MxExtI"#TYPE.Size#"_2")>>;
// Again, there are two ways to write an immediate to Dn register either dEA
@ -141,7 +141,7 @@ class MxBiArOp_RFRM<string MN, SDNode NODE, MxType TYPE, MxOperand OPD, ComplexP
[(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, (TYPE.Load PAT:$opd)))],
MxArithEncoding<MxBead4Bits<CMD>,
!cast<MxEncOpMode>("MxOpMode"#TYPE.Size#TYPE.RLet#"EA"),
MxBeadReg<0>, EA, EXT>>;
MxBeadDReg<0>, EA, EXT>>;
} // Constraints
@ -157,7 +157,7 @@ class MxBiArOp_FMR<string MN, SDNode NODE, MxType TYPE,
[],
MxArithEncoding<MxBead4Bits<CMD>,
!cast<MxEncOpMode>("MxOpMode"#TYPE.Size#"EA"#TYPE.RLet),
MxBeadReg<1>, EA, EXT>>;
MxBeadDReg<1>, EA, EXT>>;
class MxBiArOp_FMI<string MN, SDNode NODE, MxType TYPE,
MxOperand MEMOpd, ComplexPattern MEMPat,
@ -262,9 +262,9 @@ multiclass MxBiArOp_DF<string MN, SDNode NODE, bit isComm,
let isCommutable = isComm in {
def NAME#"8dd" : MxBiArOp_RFRR_xEA<MN, NODE, MxType8d, CMD>;
def NAME#"16dd" : MxBiArOp_RFRR_xEA<MN, NODE, MxType16d, CMD>;
def NAME#"32dd" : MxBiArOp_RFRR_xEA<MN, NODE, MxType32d, CMD>;
def NAME#"8dd" : MxBiArOp_RFRR_xEA<MN, NODE, MxType8d, CMD, MxBeadDReg<0>>;
def NAME#"16dd" : MxBiArOp_RFRR_xEA<MN, NODE, MxType16d, CMD, MxBeadDReg<0>>;
def NAME#"32dd" : MxBiArOp_RFRR_xEA<MN, NODE, MxType32d, CMD, MxBeadDReg<0>>;
} // isComm
@ -291,7 +291,7 @@ multiclass MxBiArOp_AF<string MN, SDNode NODE, bit isComm,
def NAME#"32ri" : MxBiArOp_RFRI_xEA<MN, NODE, MxType32r, CMD>;
let isCommutable = isComm in
def NAME#"32rr" : MxBiArOp_RFRR_xEA<MN, NODE, MxType32r, CMD>;
def NAME#"32rr" : MxBiArOp_RFRR_xEA<MN, NODE, MxType32r, CMD, MxBeadReg<0>>;
} // MxBiArOp_AF
@ -313,7 +313,7 @@ class MxBiArOp_RFRRF<string MN, SDNode NODE, MxType TYPE, bits<4> CMD>
[(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.VT:$opd, CCR))],
MxArithXEncoding<MxBead4Bits<CMD>,
!cast<MxEncSize>("MxEncSize"#TYPE.Size),
MxBead1Bit<0>, MxBeadReg<2>, MxBeadReg<0>>>;
MxBead1Bit<0>, MxBeadDReg<2>, MxBeadDReg<0>>>;
} // Constraints
} // Uses, Defs
@ -372,7 +372,7 @@ class MxCmp_RR<MxType TYPE>
[(set CCR, (MxCmp TYPE.VT:$lhs, TYPE.VT:$rhs))],
MxArithEncoding<MxBead4Bits<0xB>,
!cast<MxEncOpMode>("MxOpMode"#TYPE.Size#"dEA"),
MxBeadReg<1>, MxEncEAd_0, MxExtEmpty>>;
MxBeadDReg<1>, MxEncEAd_0, MxExtEmpty>>;
class MxCmp_RI<MxType TYPE>
: MxInst<(outs), (ins TYPE.IOp:$imm, TYPE.ROp:$reg),
@ -412,7 +412,7 @@ class MxCmp_RM<MxType TYPE, MxOperand MEMOpd, ComplexPattern MEMPat,
[(set CCR, (MxCmp (load MEMPat:$mem), TYPE.ROp:$reg))],
MxArithEncoding<MxBead4Bits<0xB>,
!cast<MxEncOpMode>("MxOpMode"#TYPE.Size#"dEA"),
MxBeadReg<0>, EA, EXT>>;
MxBeadDReg<0>, EA, EXT>>;
} // let mayLoad = 1
} // let Defs = [CCR]
@ -474,7 +474,7 @@ def MxExtOpmode_lb : MxBead3Bits<0b111>;
/// 0 1 0 0 1 0 0 | OPMODE | 0 0 0 | REG
/// ---------------------------------------------------
class MxExtEncoding<MxBead3Bits OPMODE>
: MxEncoding<MxBeadReg<0>, MxBead3Bits<0b000>, OPMODE,
: MxEncoding<MxBeadDReg<0>, MxBead3Bits<0b000>, OPMODE,
MxBead3Bits<0b100>, MxBead4Bits<0b0100>>;
let Defs = [CCR] in
@ -508,7 +508,7 @@ def MxUDiMuOpmode : MxBead3Bits<0b011>;
/// x x x x | REG | OP MODE | MODE | REG
/// ----------------------------------------------------
class MxDiMuEncoding<MxBead4Bits CMD, MxBead3Bits OPMODE, MxEncEA EA, MxEncExt EXT>
: MxEncoding<EA.Reg, EA.DA, EA.Mode, OPMODE, MxBeadReg<0>, CMD,
: MxEncoding<EA.Reg, EA.DA, EA.Mode, OPMODE, MxBeadDReg<0>, CMD,
EXT.Imm, EXT.B8, EXT.Scale, EXT.WL, EXT.DAReg>;
let Defs = [CCR] in {

6
llvm/lib/Target/M68k/M68kInstrBits.td
View File

@ -32,7 +32,7 @@
/// ------------+---------+---------+---------+---------
/// 0 0 0 0 | REG | 1 0 0 | MODE | REG
/// ------------+---------+---------+---------+---------
class MxBTSTEnc_R<MxBeadReg REG, MxEncEA EA, MxEncExt EXT>
class MxBTSTEnc_R<MxBeadDReg REG, MxEncEA EA, MxEncExt EXT>
: MxEncoding<EA.Reg, EA.DA, EA.Mode, MxBead3Bits<0b100>, REG, MxBead4Bits<0b0000>,
EXT.Imm, EXT.B8, EXT.Scale, EXT.WL, EXT.DAReg>;
@ -52,7 +52,7 @@ let Defs = [CCR] in {
class MxBTST_RR<MxType TYPE>
: MxInst<(outs), (ins TYPE.ROp:$dst, TYPE.ROp:$bitno), "btst\t$bitno, $dst",
[(set CCR, (MxBt TYPE.VT:$dst, TYPE.VT:$bitno))],
MxBTSTEnc_R<MxBeadReg<1>, MxEncEAd_0, MxExtEmpty>>;
MxBTSTEnc_R<MxBeadDReg<1>, MxEncEAd_0, MxExtEmpty>>;
class MxBTST_RI<MxType TYPE>
: MxInst<(outs), (ins TYPE.ROp:$dst, TYPE.IOp:$bitno), "btst\t$bitno, $dst",
@ -63,7 +63,7 @@ class MxBTST_MR<MxType TYPE, MxOperand MEMOpd, ComplexPattern MEMPat,
MxEncEA EA, MxEncExt EXT>
: MxInst<(outs), (ins MEMOpd:$dst, TYPE.ROp:$bitno), "btst\t$bitno, $dst",
[(set CCR, (MxBt (TYPE.Load MEMPat:$dst), TYPE.VT:$bitno))],
MxBTSTEnc_R<MxBeadReg<1>, EA, EXT>>;
MxBTSTEnc_R<MxBeadDReg<1>, EA, EXT>>;
class MxBTST_MI<MxType TYPE, MxOperand MEMOpd, ComplexPattern MEMPat,
MxEncEA EA, MxEncExt EXT>

17
llvm/lib/Target/M68k/M68kInstrFormats.td
View File

@ -95,16 +95,17 @@ class MxBead4Bits <bits<4> b> : MxBead<0x4, b{0}, b{1}, b{2}, b{3}>;
class MxBeadDAReg <bits<3> o, bit a = 0> : MxBead<0x5, o{0}, o{1}, o{2}, a>;
class MxBeadDA <bits<3> o, bit a = 0> : MxBead<0x6, o{0}, o{1}, o{2}, a>;
class MxBeadReg <bits<3> o, bit a = 0> : MxBead<0x7, o{0}, o{1}, o{2}, a>;
class MxBead8Disp <bits<3> o, bit a = 0> : MxBead<0x8, o{0}, o{1}, o{2}, a>;
class MxBeadDReg <bits<3> o, bit a = 0> : MxBead<0x8, o{0}, o{1}, o{2}, a>;
class MxBead8Disp <bits<3> o, bit a = 0> : MxBead<0x9, o{0}, o{1}, o{2}, a>;
/// Add Immediate to the instruction. 8-bit version is padded with zeros to fit
/// the word.
class MxBead8Imm <bits<3> o, bit a = 0> : MxBead<0x9, o{0}, o{1}, o{2}, a>;
class MxBead16Imm <bits<3> o, bit a = 0> : MxBead<0xA, o{0}, o{1}, o{2}, a>;
class MxBead32Imm <bits<3> o, bit a = 0> : MxBead<0xB, o{0}, o{1}, o{2}, a>;
class MxBead8Imm <bits<3> o, bit a = 0> : MxBead<0xA, o{0}, o{1}, o{2}, a>;
class MxBead16Imm <bits<3> o, bit a = 0> : MxBead<0xB, o{0}, o{1}, o{2}, a>;
class MxBead32Imm <bits<3> o, bit a = 0> : MxBead<0xC, o{0}, o{1}, o{2}, a>;
/// Encodes an immediate 0-7(alt. 1-8) into 3 bit field
class MxBead3Imm <bits<3> o, bit a = 0> : MxBead<0xC, o{0}, o{1}, o{2}, a>;
class MxBead3Imm <bits<3> o, bit a = 0> : MxBead<0xD, o{0}, o{1}, o{2}, a>;
class MxEncoding<MxBead n0 = MxBeadTerm, MxBead n1 = MxBeadTerm,
@ -202,7 +203,7 @@ class MxEncEA<MxBead reg, MxBead mode, MxBead da = MxBeadIgnore> {
// FIXME: Is there a way to factorize the addressing mode suffix (i.e.
// 'r', 'd', 'a' etc.) and use something like multiclass to replace?
def MxEncEAr_0: MxEncEA<MxBeadDAReg<0>, MxBead2Bits<0b00>>;
def MxEncEAd_0: MxEncEA<MxBeadReg<0>, MxBead2Bits<0b00>, MxBead1Bit<0>>;
def MxEncEAd_0: MxEncEA<MxBeadDReg<0>, MxBead2Bits<0b00>, MxBead1Bit<0>>;
def MxEncEAa_0: MxEncEA<MxBeadReg<0>, MxBead2Bits<0b00>, MxBead1Bit<1>>;
def MxEncEAj_0: MxEncEA<MxBeadReg<0>, MxBead2Bits<0b01>, MxBead1Bit<0>>;
def MxEncEAo_0: MxEncEA<MxBeadReg<0>, MxBead2Bits<0b01>, MxBead1Bit<1>>;
@ -214,7 +215,7 @@ def MxEncEAa_0_reflected : MxEncEA<MxBeadReg<0>, MxBead3Bits<0b001>>;
def MxEncEAr_0_reflected : MxEncEA<MxBeadReg<0>, MxBead2Bits<0b00>, MxBeadDA<0>>;
def MxEncEAr_1: MxEncEA<MxBeadDAReg<1>, MxBead2Bits<0b00>>;
def MxEncEAd_1: MxEncEA<MxBeadReg<1>, MxBead2Bits<0b00>, MxBead1Bit<0>>;
def MxEncEAd_1: MxEncEA<MxBeadDReg<1>, MxBead2Bits<0b00>, MxBead1Bit<0>>;
def MxEncEAa_1: MxEncEA<MxBeadReg<1>, MxBead2Bits<0b00>, MxBead1Bit<1>>;
def MxEncEAj_1: MxEncEA<MxBeadReg<1>, MxBead2Bits<0b01>, MxBead1Bit<0>>;
def MxEncEAo_1: MxEncEA<MxBeadReg<1>, MxBead2Bits<0b01>, MxBead1Bit<1>>;
@ -223,7 +224,7 @@ def MxEncEAp_1: MxEncEA<MxBeadReg<1>, MxBead2Bits<0b10>, MxBead1Bit<1>>;
def MxEncEAf_1: MxEncEA<MxBeadReg<1>, MxBead2Bits<0b11>, MxBead1Bit<0>>;
def MxEncEAr_2: MxEncEA<MxBeadDAReg<2>, MxBead2Bits<0b00>>;
def MxEncEAd_2: MxEncEA<MxBeadReg<2>, MxBead2Bits<0b00>, MxBead1Bit<0>>;
def MxEncEAd_2: MxEncEA<MxBeadDReg<2>, MxBead2Bits<0b00>, MxBead1Bit<0>>;
def MxEncEAa_2: MxEncEA<MxBeadReg<2>, MxBead2Bits<0b00>, MxBead1Bit<1>>;
def MxEncEAj_2: MxEncEA<MxBeadReg<2>, MxBead2Bits<0b01>, MxBead1Bit<0>>;
def MxEncEAo_2: MxEncEA<MxBeadReg<2>, MxBead2Bits<0b01>, MxBead1Bit<1>>;

6
llvm/lib/Target/M68k/M68kInstrShiftRotate.td
View File

@ -38,11 +38,11 @@ def MxROOP_RO : MxBead2Bits<0b11>;
/// 1 1 1 0 | REG/IMM | D | SIZE |R/I| OP | REG
/// ------------+---------+---+------+---+------+---------
class MxSREncoding_R<MxBead1Bit DIRECTION, MxBead2Bits ROOP, MxEncSize SIZE>
: MxEncoding<MxBeadReg<0>, ROOP, MxBead1Bit<1>, SIZE, DIRECTION,
MxBeadReg<2>, MxBead4Bits<0b1110>>;
: MxEncoding<MxBeadDReg<0>, ROOP, MxBead1Bit<1>, SIZE, DIRECTION,
MxBeadDReg<2>, MxBead4Bits<0b1110>>;
class MxSREncoding_I<MxBead1Bit DIRECTION, MxBead2Bits ROOP, MxEncSize SIZE>
: MxEncoding<MxBeadReg<0>, ROOP, MxBead1Bit<0>, SIZE, DIRECTION,
: MxEncoding<MxBeadDReg<0>, ROOP, MxBead1Bit<0>, SIZE, DIRECTION,
MxBead3Imm<2, 1>, MxBead4Bits<0b1110>>;
// $reg <- $reg op $reg

11
llvm/lib/Target/M68k/MCTargetDesc/M68kBaseInfo.h
View File

@ -58,11 +58,12 @@ enum {
DAReg = 0x5,
DA = 0x6,
Reg = 0x7,
Disp8 = 0x8,
Imm8 = 0x9,
Imm16 = 0xA,
Imm32 = 0xB,
Imm3 = 0xC,
DReg = 0x8,
Disp8 = 0x9,
Imm8 = 0xA,
Imm16 = 0xB,
Imm32 = 0xC,
Imm3 = 0xD,
};
// Ctrl payload

2
llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp
View File

@ -121,6 +121,7 @@ unsigned M68kMCCodeEmitter::encodeReg(unsigned ThisByte, uint8_t Bead,
Reg = false;
DA = true;
break;
case M68kBeads::DReg:
case M68kBeads::Reg:
Reg = true;
DA = false;
@ -351,6 +352,7 @@ void M68kMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
break;
case M68kBeads::DAReg:
case M68kBeads::DA:
case M68kBeads::DReg:
case M68kBeads::Reg:
Offset +=
encodeReg(ThisByte, Bead, MI, Desc, Buffer, Offset, Fixups, STI);