forked from OSchip/llvm-project
Revert r130454; apparently this doesn't actually work.
llvm-svn: 130462
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51cc833af7
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@ -822,9 +822,26 @@ void ARMFastISel::ARMSimplifyAddress(Address &Addr, EVT VT) {
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// Since the offset is too large for the load/store instruction
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// get the reg+offset into a register.
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if (needsLowering) {
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Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
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/*Op0IsKill*/false, Addr.Offset, MVT::i32);
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ARMCC::CondCodes Pred = ARMCC::AL;
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unsigned PredReg = 0;
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TargetRegisterClass *RC = isThumb ? ARM::tGPRRegisterClass :
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ARM::GPRRegisterClass;
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unsigned BaseReg = createResultReg(RC);
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if (!isThumb)
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emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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BaseReg, Addr.Base.Reg, Addr.Offset,
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Pred, PredReg,
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static_cast<const ARMBaseInstrInfo&>(TII));
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else {
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assert(AFI->isThumb2Function());
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emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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BaseReg, Addr.Base.Reg, Addr.Offset, Pred, PredReg,
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static_cast<const ARMBaseInstrInfo&>(TII));
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}
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Addr.Offset = 0;
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Addr.Base.Reg = BaseReg;
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}
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}
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@ -1,11 +0,0 @@
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; RUN: llc -O0 -regalloc=linearscan < %s
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; This isn't exactly a useful set of command-line options, but check that it
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; doesn't crash. (It was crashing because a register was getting redefined.)
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target triple = "thumbv7-apple-macosx10.6.7"
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define i32 @f(i32* %x) nounwind ssp {
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%y = getelementptr inbounds i32* %x, i32 5000
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%tmp103 = load i32* %y, align 4
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ret i32 %tmp103
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}
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