forked from OSchip/llvm-project
Refactor code a bit to share commonalities. No functional change intended.
llvm-svn: 161745
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921cf137b3
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5145a0d967
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@ -8540,10 +8540,12 @@ SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
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DebugLoc dl = Op.getDebugLoc();
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if (isFP) {
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unsigned SSECC = 8;
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#ifndef NDEBUG
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EVT EltVT = Op0.getValueType().getVectorElementType();
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assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT;
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assert(EltVT == MVT::f32 || EltVT == MVT::f64);
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#endif
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unsigned SSECC;
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bool Swap = false;
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// SSE Condition code mapping:
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@ -8556,7 +8558,7 @@ SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
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// 6 - NLE
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// 7 - ORD
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switch (SetCCOpcode) {
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default: break;
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default: llvm_unreachable("Unknown SetCC condition");
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case ISD::SETOEQ:
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case ISD::SETEQ: SSECC = 0; break;
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case ISD::SETOGT:
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@ -8570,34 +8572,33 @@ SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
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case ISD::SETUO: SSECC = 3; break;
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case ISD::SETUNE:
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case ISD::SETNE: SSECC = 4; break;
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case ISD::SETULE: Swap = true;
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case ISD::SETULE: Swap = true; // Fallthrough
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case ISD::SETUGE: SSECC = 5; break;
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case ISD::SETULT: Swap = true;
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case ISD::SETULT: Swap = true; // Fallthrough
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case ISD::SETUGT: SSECC = 6; break;
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case ISD::SETO: SSECC = 7; break;
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case ISD::SETUEQ:
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case ISD::SETONE: SSECC = 8; break;
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}
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if (Swap)
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std::swap(Op0, Op1);
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// In the two special cases we can't handle, emit two comparisons.
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if (SSECC == 8) {
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unsigned CC0, CC1;
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unsigned CombineOpc;
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if (SetCCOpcode == ISD::SETUEQ) {
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SDValue UNORD, EQ;
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UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
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DAG.getConstant(3, MVT::i8));
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EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
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DAG.getConstant(0, MVT::i8));
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return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
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CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
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} else {
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assert(SetCCOpcode == ISD::SETONE);
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CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
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}
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if (SetCCOpcode == ISD::SETONE) {
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SDValue ORD, NEQ;
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ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
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DAG.getConstant(7, MVT::i8));
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NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
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DAG.getConstant(4, MVT::i8));
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return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
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}
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llvm_unreachable("Illegal FP comparison");
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SDValue Cmp0 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
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DAG.getConstant(CC0, MVT::i8));
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SDValue Cmp1 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
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DAG.getConstant(CC1, MVT::i8));
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return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
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}
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// Handle all other FP comparisons here.
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return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
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